CN103853135A - Regulating access to slave devices - Google Patents

Regulating access to slave devices Download PDF

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Publication number
CN103853135A
CN103853135A CN201310650319.4A CN201310650319A CN103853135A CN 103853135 A CN103853135 A CN 103853135A CN 201310650319 A CN201310650319 A CN 201310650319A CN 103853135 A CN103853135 A CN 103853135A
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port
equipment
coupled
storage devices
volatile storage
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CN103853135B (en
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W.库杜斯
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Silicon Laboratories Inc
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Silicon Laboratories Inc
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Abstract

The present invention relates to regulating access of slave devices. A method includes receiving a request from a master device to access a slave device of a plurality of slave devices that are associated with a slave port of bus switching fabric. The slave port is shared in common among the slave devices. The method includes, in response to the request, multiplexing use of the slave port among the slave devices.

Description

Regulate the access from equipment
Background technology
For the initiation bus agent being called as " main frame (master) " (for example, processor) and target bus agency or " slave (slave) " are (for example, memory device) between transmit the object of data, the computer system with multiple main frames and slave can comprise bus structure (fabric).In typical bus operation, main frame is by being driven into address signal in bus so that slave is come given slave to initiate bus operation (such as read or write) as target together with suitable control signal and data-signal (if data are written to slave).For following object, on bus, respond by generating suitable signal as the slave of the target of bus operation: as be to and from the transmission data of main frame; Misdirection; Or signaling main frame retry bus operation.
Bus is the limited system resource that conventionally in any one time, individual host is coupled to single slave.Therefore, in the time that multiple main frames are attempted accessing identical slave simultaneously, bus matrix can be time-multiplexed they request and can comprise and carry out the arbitration between requesting host to regulate (in possible multiple main frames of competition bus access) which main frame can access bus arbitration (arbitration) circuit or " moderator " of bus.
Summary of the invention
In the exemplary embodiment, a kind of method comprises from main equipment reception multiple requests from equipment from equipment from port association with bus switch structure for access.From port between equipment share.Described method comprises, in response to described request, from the multiplexing use from port between equipment.
In another exemplary embodiment, a kind of device comprises from multiplexer; With the bus matrix circuit comprising from port and master port.From port multiple between equipment share.Be suitable for initiating in response to the main frame that is coupled to master port from multiplexer for the multiple requests from equipment from equipment of access and optionally by first from device coupled to from port.
In another exemplary embodiment again, a kind of device comprises and comprises processing core; Non-volatile memory device; Volatile storage devices; Multiplexer; Integrated circuit with bus matrix circuit.Processing core is suitable for communicating with non-volatile and volatile storage devices.Bus matrix circuit comprises from port, and is coupled to the master port of processing core.Multiplexer is suitable in response to optionally one of non-volatile and volatile storage devices being coupled to from port from processing the request for accessing storage device of core.
According to following accompanying drawing, description and claim, advantage and other desired characters will become apparent.
Brief description of the drawings
Fig. 1 is according to the schematic diagram of the system of exemplary embodiment.
Fig. 2 is the schematic diagram of the micro controller unit (MCU) according to exemplary embodiment.
Fig. 3 describes according to exemplary embodiment for regulating the process flow diagram of technology of the access from equipment to MCU.
Fig. 4 is according to the schematic diagram of the motor control system of exemplary implementation.
Embodiment
Micro controller unit (MCU) can comprise that access is stored in the processing core of the machine-executable instruction (for example, " program ") in the non-volatile memory device of MCU (such as for example, flash memory device).As the result of program operation, (processing is endorsed further to access, write data to it and neutralize therefrom reading out data) can be stored in the routine data such as stack, heap, temporary variable etc. in volatile storage devices (such as, the static random-access memory (SRAM) of MCU).Herein disclosed is and allow to process core switching mode access program instruction efficiently that the object of the arbitration cycle causing is favourable and technology and the system of routine data owing to processing core between the access of non-volatile and volatile memory for minimizing or preventing.
As example more specifically, the MCU 24 in Fig. 1 depicted example system 10.For this example, MCU 24 controls the each side of one or more assemblies 70.As example, depend on application-specific, assembly 70 can comprise one or more following parts: motor, household electrical appliance, stock's control terminal, computing machine, flat computer, intelligent power meter, wave point, cellular interface, interactive touch-screen user interface etc.The all or part of of the assembly of MCU 24 can be the part of integrated circuit (IC) or semiconductor packages 30.For example,, on all or part of single nude film (die) that can be fabricated in semiconductor packages 30 of the assembly of MCU 24 or for example, on multiple nude films (, multicore module).
As further discussed in detail, MCU 24 comprises bus matrix circuit or the module 200 of for example, for example, communication between main frame (, processing core) and the slave (, volatibility and non-volatile memory device) that regulates MCU 24.MCU 24 is configured to the port of the common shared bus matrix module 200 of part slave that allows MCU 24 from side (slave side) multiplexer 282, and this can provide following advantage then: in allowing main frame such as the processing core of MCU 24 to switch between non-volatile and volatile memory access, cause a small amount of (if any) bus arbitration cycle.
With reference to figure 2, according to exemplary embodiment, MCU 24 comprises the main frame (or " main equipment ") such as processing core 150.As example, in certain embodiments, processing core 150 can be 32 cores such as senior RISC machine (ARM) is processed core of operation Reduced Instruction Set Computer (RISC) instruction set.As disclosed herein, process core 150 conventionally with such as one or more non-volatile memory device 165(for example, flash memory device) and volatile storage devices 167(for example, static random-access memory (SRAM) memory device) and so on multiple other slaves (or " from equipment ") of MCU 24 communicate.For example described below, depicted example non-volatile memory device 165 and two volatile storage devices 167-0 and 167-1 in Fig. 2, but it should be understood that according to other exemplary embodiments MCU 24 and can comprise many other these kind equipments.
According to exemplary embodiment disclosed herein, non-volatile memory device 165 is stored the data 220 that represent the programmed instruction moving for processing core 150; And volatile storage devices 167-0 and 167-1 storage can processed core 150 upgrades and read due to the operation of programmed instruction routine data 224.By this way, routine data 224 can be associated with stack, heap, variable, array etc.It should be noted, process core 150 can read and write program instruction data and routine data to other volatibility and the non-volatile memory device of MCU 24.
It should be noted, depend on specific embodiment MCU 24 and can comprise main frame and the slave except the main frame shown in Fig. 2 and slave.For example, slave can comprise the assembly except memory stores assembly, such as mathematics accelerator for example, from the external environment condition of MCU 24 and digital assembly receive simulating signal assembly (such as, AD converter (ADC), comparer etc.), such as for example, USB (universal serial bus) (USB) interface, universal asynchronous receiver/transmitter (UART), System Management Bus (SMB) interface, serial outside (SPI) interface etc.
MCU 24 comprises herein the bus switch matrix or the bus switch structure that are commonly referred to " bus matrix circuit " or " bus matrix module 200 ".In the exemplary embodiment, bus matrix module 200 can be integrated circuit (for example, be manufactured on single nude film or on multiple nude films); And in further embodiment, bus matrix module 200 can be integrated circuit group.Bus matrix module 200 regulates the host groups of MCU 24 and from the communication between unit.For the exemplary embodiment of Fig. 2, bus matrix module 200 comprises the specific master port M describing in the master port 248(Fig. 2 that is coupled to the main frame such as processing core 150 and direct memory access (DMA) controller 204 0and M 1).By this way, each main frame transmits address, control and data signal 205 with corresponding master port 248, such as the M for being coupled to Fig. 2 0the address of the processing core 150 of port, control and data signal 205.Given main frame can have multiple bus ports.In such cases, each bus port can be coupled to the independent master port of bus matrix module 200.The master port 248 of main frame also can be re-used and then be coupled to bus matrix master port.
Bus matrix module 200 further comprise be optionally coupled to slave (such as, non-volatile 165 and volatibility 167 memory devices) address, control and data signal from specific for port S shown in port 252(Fig. 2 0, S 1, S 2, S 3), as further discussed herein.By this way, bus matrix module 200 conventionally comprise by module 200 control with optionally by the address of main frame and slave, control and data signal for example, the circuit such as switch (, transistor) and so on being coupled.Depend on specific embodiment, bus matrix module 200 can all be formed by nextport hardware component NextPort or can being combined to form by hardware and software.
Such as address corresponding to providing in the lump of processing that given main frame core 150 can request access slave to bus matrix module 200 to select from one of port 252, to make bus matrix module 200 to be coupled to main frame with the slave from port association of selecting.According to exemplary embodiment, the instruction from port of being selected by main frame shows as the corresponding corresponding signal from selection port 250 of bus matrix module 200.These instructions can be for example derived from the address bit of decoding, with make specific address space can be utilize given discernible from port (with associated slave).Because multiple main frames may be attempted accessing identical from port simultaneously, according to exemplary embodiment, bus matrix module 200 is identical for example, from multiplexing arbitration of execution time between multiple main frames of port (, the strategy based on fairness such as the strategy based on round-robin method (round robin), strategy based on priority or consider the strategy of the combination of fairness and priority) in request.In other words, the access of the arbitration control to slave adapts to (accommodate) scene that wherein multiple main frames are competed the access to given slave simultaneously.According to exemplary embodiment, because bus matrix module 200 forms the ability of multiple concurrent (concurrent) principal and subordinate link, allow main frame and slave between concurrent or concurrent access.
According to system disclosed herein and technology, MCU 24 allows to use common shared the single of bus matrix module 200 between multiple slaves to visit these slaves from port 252.This type of layout has following specific advantages: reduced at accessed slave and be for example assigned to the independent stand-by period that originally can be caused from port in the time that processing core 150 is switched to another from port by access from one from port.For exemplary embodiment described herein, MCU 24 operations are stored in the programmed instruction as program instruction data 220 in non-volatile memory device 165; And MCU 24 processes the routine data 224 being retained in volatile storage devices 167-0 and 167-1.To be multiplexed into and singlely there is following specific advantages from port 252 from equipment: prevent that bus matrix module 200 stops one or more cycles in the time that given main frame is switched to the next one from a slave.According to system disclosed herein and technology, address decoding scheme merges to multiple slave addresses scopes the address realm from port 252 of sharing due to the slave causing from multiplexed port.In the time being programmed by this way, bus matrix module 200 is considered as given main frame to switch between slave, although this type of switching may occur, thereby avoids making bus matrix module 200 " to stop ".It should be noted, from side multiplexer 282 comprise for by suitable slave bus coupling to the single additional decode logic from port 252 (not shown in Figure 2), as the figure from side multiplexer 282 in Fig. 2 illustrates about the feature from multiplexed port.
According to exemplary implementation, in the time that processing core 150 moves specific program or application, for the object of the routine data associated with retrieval of search program instruction and storage in the situation that not causing any bus matrix arbitration punishment (penalty), process core 150 and can access non-volatile memory device (such as, the nonvolatile devices 165 shown in Fig. 2) and volatile storage devices 167(such as volatile storage devices 167-0 and 167-1) the two.These access relate to the communication by single bus then.
More specifically, according to exemplary embodiment, MCU 24 can adopt " von Neumann " type framework, this means that the single bus of MCU 24 use transmits the two signal of representation program instruction and data.Utilize this type of framework, process core 150 and use the time-multiplexed bus operation (read cycle, write cycle time etc.) in bus to visit non-volatile memory device 165 and volatile storage devices 167.Because each programmed instruction can comprise instruction fetch and fetch data the two, disclosed herein have following specific advantages from equipment multiplex technique: conventionally avoid owing to fetching data and instruction causes the drain bus cycle, as those skilled in the art can understand.
According to exemplary embodiment, MCU 24 comprises from address decoder 270 with from side multiplexer 282.Be coupled to from select port 250(Fig. 2 depicted example from selecting port S from address decoder 270 0, S 1, S 2and S 3) with allow the common shared bus matrix module 200 of (associated with multiple slaves) multiple address realms from port 252.In this regard, any these multiple address realms can be used to select jointly shared from port 252.As example more specifically, non-volatile memory device 165, volatile storage devices 167-0 and volatile storage devices 167-1 can carry out addressing with three different address realms; And for this example, these slaves can be shared S 0from port 252.Be configured to by selecting S from address decoder 270 0from port, main frame is responded for the request of any one access to these three different address realms.
Conventionally control slave from side multiplexer 282 and say the multiplexing of multiple slaves to the coupling from port 252 and for what jointly share from port.For the exemplary embodiment of Fig. 2, from side multiplexer 282 multiplexing S between non-volatile memory device 165, volatile storage devices 167-0 and volatile storage devices 167-1 0from the use of port 252.In addition,, for the exemplary embodiment of describing in Fig. 2, allow volatile storage devices 167-0 and 167-1 to be distributed to separately respectively S from side multiplexer 282 1and S 2from port 252(not with S 0share from port 252), as (via bridge 260) is coupled to S 3configure from the register data 266 of the system configuration register 264 of port 252.Thereby many distortion and embodiment are within the scope of the appended claims expected.
More specifically, according to exemplary embodiment, register data 266 can be that processed core 150 is programmable and comprise and have each position that can be used to optionally to programme from the correlation logic rank of port assignment.For exemplary embodiment as herein described, utilization is located corresponding to the giving of register data 266 of slave individually, and register data 266 is controlled at least which slave is shared S 0from port 252.For the exemplary embodiment of Fig. 2, register data 266 comprises to be controlled individually whether volatile storage devices 167-0 and 167-1 and shares S 0from two positions of port 252; And these two positions are represented by following two corresponding signals: be asserted into (for example, being driven into logical one value) configuration volatile storage devices 167-0 and non-volatile memory device 165(and depend on its distribution may with volatile storage devices 167-1) shared S 0substitute and be assigned with S from port 252( 1from port 252) SHARE_VMD0 signal, and be asserted into (for example, being driven into logical one value) configuration volatile storage devices 167-1 and non-volatile memory device 165(and depend on its distribution may with volatile storage devices 167-0) shared S 0substitute and be assigned to S from port 252( 2from port 252) SHARE_VMD1 signal.
Now turn to from the exemplary embodiment of address decoder 270, according to some embodiment, the selectivity from request port 250 of carrying out control bus matrix module 200 based on following address space signal from address decoder 270 is asserted: be asserted into (for example, being driven into logical one value) and indicate address in the address space of the non-volatile memory device 165 NVMD_ADDR_SPACE signal as the host access of target; Be asserted into (for example, being driven into logical one value) and indicate the APB_ADDR_SPACE signal of the host access using the address of system configuration register 264 as target; Be asserted into (for example, being driven into logical one value) and indicate address in the address space of the volatile storage devices 167-0 VMD0_ADDR_SPACE signal as the host access of target; Be asserted into (for example, being driven into logical one value) and indicate address in the address space of the volatile storage devices 167-1 VMD1_ADDR_SPACE signal as the host access of target.For example, these signals can be decoded address wire signals.
Conventionally SHARE_VMD0 and SHARE_VMD01 signal to be responded from address decoder 270, optionally effectively the address realm of volatile storage devices 167-0 and 167-1 to be mapped to the address realm of non-volatile memory device 165 to make these signals can be used to the object in order selecting from port.
More specifically, according to exemplary embodiment, comprise its output signal is coupled to S from address decoder 270 0from select port 250 OR(or) door 272.OR door 272 receive NVMD_ADDR_SPACE signal and by the AND(that receives VMD0_ADDR_SPACE signal and SHARE_VMD0 signal with) signal that provides of the lead-out terminal of door 274.The output signal being provided by the AND door 276 that receives VMD1_ADDR_SPACE signal and SHARE_VMD1 signal is also provided OR door 272.For example, thereby OR door 272 is asserted (, being driven into logical one value) S 0thereby select port using in response to the address space of non-volatile memory device 165 as the host requests of target, the address space of volatile storage devices 167-0, as the host requests of target, (supposition volatile storage devices 167-0 is configured to shared S 0from port 252) or host requests using the address space of volatile storage devices 167-1 as target (supposition volatile storage devices 167-1 is configured to share S 0from port 252) select S 0from port 252.
Further comprise its output signal is coupled to S from address decoder 270 1from selecting the AND door 278 of port 250.AND door 278 receives the SHARE_VMD0 signal of VMD0_ADDR_SPACE signal and negate.For example, thereby AND door 278 is asserted (, being driven into logical one value) S 1thereby select port using in response to the address space of volatile storage devices 167-0 is assigned to S as host requests and the volatile storage devices 167-0 of target 1from port 252 instead of shared S 0select S from port 252 1from port 252.
Also comprise its output signal is coupled to S from address decoder 270 2from selecting the AND door 280 of port 250.AND door 280 receives the SHARE_VMD1 signal of VMD1_ADDR_SPACE signal and negate.For example, thereby AND door 280 is asserted (, being driven into logical one value) S 2thereby select port using in response to the address space of volatile storage devices 167-1 is assigned to S as host requests and the volatile storage devices 167-1 of target 2from port 252 instead of shared S 0select S from port 252 2from port 252.Finally, the embodiment describing for Fig. 2, offers S from address decoder 270 by APB_ADDR_SPACE signal 3from selecting port 250, for this example, system configuration register 264 is exclusively used in S 3from port 252, to make in response to S is selected to as the host requests of target in the address of system configuration register 264 3from port 252.
According to exemplary embodiment, optionally slave (such as non-volatile memory device 165, volatile storage devices 167-0 and volatile storage devices 167-1) is coupled to from port 252 from side multiplexer 282.Comprise from side multiplexer 282 and have the address from equipment for selecting, control and data signal and be provided to S 0from the OR door 288 of multiple lead-out terminals of port 252.More specifically, OR door 288 comprise from non-volatile memory device 165 receive be strobed (gate) address, control and data signal first group of input terminal of 166.These gating signals are provided by multiple lead-out terminal of AND door 284.AND door 284 comprises the input terminal of the lead-out terminal that is coupled to one group of input terminal of signal 166 and is coupled to AND door 286 (, controls when signal 166 is coupled to S to control gating 0from port 252).AND door 286 receives as host requests and S 0the signal (being called " REQ_S0 ") being asserted in the time that the moderator from one of equipment and bus matrix module 200 of port 252 associations is granted access.AND door 286 is asserted the NVMD_ADDR_SPACE signal of (for example, being driven into logical one value) while also receiving the address space associated with non-volatile memory device 165 when host requests.
OR door 288 comprises from volatile storage devices 167-0 and receives the address that is strobed, control and data signal second group of input terminal of 168.These signals that are strobed are provided by multiple lead-out terminal of AND door 290.AND door 290 comprises that the input terminal of the lead-out terminal that is coupled to one group of input terminal of signal 168 and is coupled to AND door 292 is to control gating.AND door 292 is asserted the signal " VMD0_ADDR_SPACE " of (for example, being driven into logical one value) when receiving REQ_S0 signal and receiving the address space associated with volatile storage devices 167-0 when host requests.AND door 292 also receives SHARE_VMD0 signal.Therefore, when host requests access volatile storage devices 167-0, this access are granted and MCU 24(via system configuration register 264) be configured to share S with volatile storage devices 167-0 0during from port 252, AND door 290 is coupled to the signal from volatile storage devices 167-0 168 OR door 288(and is coupled to S 0from port 252).
OR door 288 comprises from volatile storage devices 167-1 and receives the address that is strobed, control and data signal 169 the 3rd group of input terminal.These signals that are strobed are provided by multiple lead-out terminal of AND door 294.AND door 294 comprises that another input terminal of the input terminal that is coupled to one group of input terminal of signal 169 and comprises the lead-out terminal that is coupled to AND door 296 is to control gating.AND door 296 is asserted the signal " VMD1_ADDR_SPACE " of (for example, being driven into logical one value) when receiving REQ_S0 signal and receiving the address space associated with volatile storage devices 167-1 when host requests.AND door 296 also receives SHARE_VMD1 signal.Therefore, when host requests access volatile storage devices 167-1, this access are granted and MCU 24(via system configuration register 264) be configured to share S with volatile storage devices 167-1 0during from port 252, AND door 294 is coupled to the signal from volatile storage devices 167-1 169 OR door 288(and is coupled to S 0from port 252).
As shown in Figure 2, according to exemplary embodiment, the signal 168 of volatile storage devices 167-0 can be coupled to S1 and visit from the address realm of port 252 volatile storage devices 167-0 can be used be assigned to S1 from port 252.Similarly, the signal 169 of volatile storage devices 167-1 can be coupled to S 2from port 252, so that can being used, volatile storage devices 167-1 is assigned to S 2visit from the address realm of port 252.In addition, as shown in Figure 2, according to exemplary embodiment, bridge 260 can be coupled to S 3from port 252.Except system configuration register 264, other equipment (input equipment etc.) can be coupled to the terminal 262 of bridge 260 and can be to pass through S 3addressable from port 252.
Other distortion are within the scope of the appended claims expected.For example, according to further embodiment, two slaves can be shared S 0from port 252 and do not there is the S of going to 1from the replacement path of port 252.As example more specifically, according to specific embodiment, the two can (for example,, with one or more volatile storage devices 167) share S from equipment for non-volatile memory device 165 and mathematics accelerator 0from port 252, and non-volatile memory device 165 and mathematics accelerator facility can not have and go to another replacement path from port 252.This type of layout can have following advantage: eliminate the arbitration cycle in the time that main frame is transformed into mathematics accelerator and returns from non-volatile memory device 165.
As another example, according to further embodiment, two slaves can be shared S 1from port.For example, according to exemplary embodiment, volatile storage devices 167-0 and 167-1 can use from the multiplex circuit of side multiplexer 282 and share S 1from port 252.This embodiment has following advantage: by two volatile storage devices 167-0 and 167-1 in conjunction with make equipment 167-0 and 167-1 show the single memory device of picture (for example, single SRAM equipment) the same, thus reduce the arbitration stand-by period in the time that host access is changed between its address realm.
With reference to figure 3, thereby according to exemplary embodiment, a kind of method 300 comprises from main frame and receives (piece 304) for access and the request from equipment of the multiple targets from equipment from port association of bus switch structure.According to method 300, in response to this request, from multiplexing between equipment (piece 308) from equipment to the use from port to allow host access target from equipment.
With reference to figure 4, MCU 24 can be used to various application.As example, the MCU 24 that Fig. 4 describes wherein the object motor control system 400 in order to control motor 474 generates/receives the transmitter control application of input and output signal (I/O signal).By this way, for the interface that comprises driver, sensor with motor interface 470() object that communicates, MCU 24 can generate signals at its I/O terminal 450 places; And together with this communication, I/O terminal 450 can transmit waveform (for example, pulse-length modulation (PWM) signal) with motor interface, receives electric current and the voltage of sensing, transmit data etc. via one or more universal serial bus.For following object, the I/O terminal 440 of MCU 24 can generate/receive the signal for communicating with the user control interface 476 of system 400, described object transmits the state of motor 474 or motor interface 470, transmit the failure condition detecting, receive order and the signal etc. of user's guiding.
Although disclose the embodiment of limited quantity herein, have benefited from the disclosure and those skilled in the art will recognize that various amendments and the distortion by its generation.This means additional claim and contains all these type of amendments and distortion.

Claims (20)

1. a method, comprising:
From handle and bus switch structure from equipment, receive request from equipment as the main equipment of target from port association multiple, described from port multiple from sharing between equipment; And
In response to this request, multiple from the multiplexing use from port between equipment.
2. method according to claim 1, wherein said request instruction is with target from the associated address of equipment, and multiplexing use from port comprises based on described address and carrys out select target from equipment.
3. method according to claim 1, further comprises by bus switch structure based on consider whether at least one other main frame is competed that multiple at least one from equipment are optionally coupled to master port from port from the arbitration agreement of the access of equipment simultaneously.
4. method according to claim 1, further comprises:
At main equipment be coupled to multiple from transmission procedure instruction and routine data between equipment from port.
5. method according to claim 1, wherein receives the address that described request comprises that decoding is provided by main equipment.
6. method according to claim 1, wherein the multiplexing use from port is included at least multiplexing use from port between non-volatile memory device and volatile storage devices.
7. method according to claim 1, further comprises:
Carry out program register data with register and share multiple from equipment from port to identify.
8. a device, comprising:
Bus matrix circuit, comprises from port and master port, described from port multiple between equipment share; And
Multiplexer, be suitable in response to initiated by the main frame that is coupled to master port for multiple the first requests from equipment from equipment of access and optionally by first from device coupled to from port.
9. device according to claim 8, wherein comprises at least one volatile storage devices and at least one non-volatile memory device from equipment.
10. device according to claim 8, further comprises:
From address decoder, be used to indicate as to the selection from port of multiple responses from the associated multiple address realms of equipment.
11. devices according to claim 8, wherein said multiplexer is suitable for optionally multiple from device coupled to from port.
12. devices according to claim 8, further comprise and are coupled to the register of bus matrix circuit with storage data, described register is suitable for being configured in multiple from sharing from port between equipment able to programmely.
13. 1 kinds of devices, comprising:
Integrated circuit, comprises and processes core, non-volatile memory device, volatile storage devices, multiplexer and bus matrix circuit, wherein:
Described processing core is suitable for communicating with non-volatile and volatile storage devices;
Described bus matrix circuit comprises from port and the master port that is coupled to described processing core; And
Described multiplexer is suitable for optionally one of non-volatile and volatile storage devices being coupled to from port in response to the request of and one of the volatile storage devices non-volatile for access from processing core.
14. devices according to claim 13, wherein:
Bus matrix circuit is suitable for optionally master port being coupled to from port; And
Bus matrix circuit is suitable for the application based on arbitration agreement at least partly and controls described coupling.
15. devices according to claim 13, further comprise the register that is coupled to bus matrix circuit, described register be suitable for storing data with able to programme be configured in multiple from sharing from port between equipment.
16. devices according to claim 15, wherein processor core is suitable for transmitting the request from port for access to bus matrix circuit, described request instruction and address from port association, and multiplexer is suitable for selecting the non-volatile or volatile storage devices associated with address for serving described request.
17. devices according to claim 13, wherein bus matrix circuit is suitable for making processing core non-volatile and volatile storage devices is considered as jointly as independent from equipment.
18. devices according to claim 13, wherein bus matrix circuit further comprises at least one additional master port, described device further comprises the direct memory access controller that is coupled to described at least one additional master port.
19. devices according to claim 13, wherein integrated circuit further comprise for share from port based on non-memory stores from equipment.
20. devices according to claim 13, further comprise the bus for processing core being coupled to bus matrix circuit.
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