CN103905015A - Wireless low-jitter transmission method for high-precision digital asynchronous pulse - Google Patents
Wireless low-jitter transmission method for high-precision digital asynchronous pulse Download PDFInfo
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Abstract
The invention relates to a wireless low-jitter transmission method for a high-precision digital asynchronous pulse in the field of pulse wireless transmission and communication, and the wireless low-jitter transmission method is particularly suitable for wireless low-jitter transmission of a radar pulse. Pulse shaping is carried out on a transmitting terminal, a time-digital conversion module is used for converting the time difference between an asynchronous pulse signal obtained after pulse shaping and a rising edge or a falling edge of a local clock into a digital signal, and the steps of digital sampling, encoding, modulation and the like are conducted on the digital signal; on a receiving terminal, a timing error estimation module, a loop smoothing module, an NCO module, an interpolation and filtering module and the like are used for improving the precision of the local clock, output pulse phase position errors are reduced on the premise that the bandwidth is not sacrificed, and finally a high-precision low-jitter pulse signal is output. According to the wireless low-jitter transmission method, a full-digital processing method is adopted, and the high-precision asynchronous low-jitter pulse transmission effect can be realized without local clock synchronization. Main circuit components are obtained through FPGAs or ASICs, so that the design difficulty and the modulation difficulty are low.
Description
Technical field
The present invention relates to the wireless low jitter transmission method of a kind of high accuracy number asynchronous pulse in pulse wireless transport communication field, be specially adapted to the wireless low jitter transmission of radar pulse.
Background technology
Conventional pulse digital sampling wireless transmission method, can judge having or not of pulse signal accurately at receiving terminal, and rising edge, the trailing edge shake of the pulse signal still receiving are larger.Reduce along shake, just need to improve sampling clock frequency, thereby improve the sample rate of paired pulses.If to being low to moderate nanosecond along the requirement of shake, required clock frequency is even higher up to 1GHz.Under current technical conditions, this is difficult to realize.Existing synchronous low jitter transmission method, the low jitter transmission of its pulse will be take sacrificial system bandwidth as cost; Can only process pulse edge and clock along synchronous situation at transmitting terminal, cause it in radar pulse transmission, to apply limited; And adopt analog phase-locked loop circuit to reduce along shake at receiving terminal, and system debug is wasted time and energy, and the lifting of precision is limited.
Summary of the invention
Technical problem to be solved by this invention is to avoid the weak point in above-mentioned background and a kind of high accuracy pulse digital wireless low jitter transmission method based on asynchronous clock is provided, do not sacrificing under the prerequisite of bandwidth, reduce to export impulse phase error, finally export high-precision low jitter pulse signal.At transmitting terminal, radar pulse and local clock are passed through to time figure modular converter, the time difference of radar pulse and local clock rising edge or trailing edge is converted into digital signal, then complete the modulation transmissions to this signal.At receiving terminal, utilize timing error estimation module, loop filtering module, numerical control NCO module, interpolation filtering module etc., adopt feedback control loop design, improve local clock precision, thereby realize the low jitter transmission of pulse.Main circuit parts sampling FPGA or the ASIC of the inventive method realize, high conformity, and debugging difficulty is low, easily realizes the wireless transmission that pulse jitter is less than 3ns.
The object of the present invention is achieved like this, and it comprises step:
Transmitting terminal:
1) input asynchronous pulse signal is carried out to shaping pulse, realize the pulse straightening in Wireline transmission;
2) adopt time figure modular converter that the time difference between the asynchronous pulse signal after shaping pulse and rising edge or the trailing edge of local clock is converted into digital signal;
3) to step 2) generate digital signal carry out impulse sampling, coding and modulation, form digital modulation signals, in digital modulation signals, include pulse information and time difference information;
4) digital modulation signals is carried out to D/A switch, be converted to modulated-analog signal;
5) radio frequency unit carries out up-conversion and power amplification to modulated-analog signal, is converted to high-frequency signal, and high-frequency signal is sent into wireless channel by antenna;
Receiving terminal:
6) radio frequency unit passes through the high-frequency signal in antenna reception wireless channel, and high-frequency signal is carried out after low noise amplification, down-conversion and AGC amplify being converted to analogue zero intermediate-freuqncy signal;
7) analogue zero intermediate-freuqncy signal is carried out to mould/number conversion, be converted to digital zero intermediate-freuqncy signal;
8) the fractional spaced and basic point of interpolation in the optimal sampling position that feeds back according to numerical control NCO unit, carries out digital interpolation to the sampled value of digital zero intermediate frequency signals;
9) baseband signal after digital interpolation is carried out to matched filtering;
10) signal after matched filtering is carried out to carrier wave recovery, the frequency deviation producing in transmitting procedure for compensating signal and skew;
11) time domain waveform of signal after carrier wave recovery is adjudicated, afterwards, proceed to step 12) and step 15) simultaneously;
12) the court verdict information obtaining according to step 11), adopts Gardner algorithm, estimates the timing error information of the rear signal of carrier wave recovery;
13) timing error information estimating is passed through to loop filtering module filtering noise;
14) numerical control NCO unit calculates the fractional spaced and basic point of interpolation in optimal sampling position according to the timing error information that estimates, proceeds to step 8);
15) court verdict information step 11) being obtained is carried out decoding coupling;
16) the optimal sampling position that provides according to numerical control NCO unit is fractional spaced carries out pulse-recovery to the signal after decoding coupling, the asynchronous pulse signal of output low jitter;
Complete the wireless low jitter transmission of high accuracy number asynchronous pulse.
The present invention is compared with background technology, and tool has the following advantages:
The wireless low jitter transmission method of the high accuracy number asynchronous pulse that 1, the present invention proposes, compared with transmitting with conventional lock-out pulse wireless low jitter, more realistic application demand, processing accuracy is higher, realize and debug more simple and fast, and not take sacrificial system bandwidth as cost.Existing lock-out pulse wireless low jitter transmission method can only be processed at make a start pulse edge and clock along synchronous situation, and this is the practical application that does not meet radar pulse transmission, causes it in radar pulse transmission, to apply limited; Existing lock-out pulse wireless low jitter transmission method adopts analog phase-locked loop circuit to reduce along the mode of shake at receiving terminal, due to time of delay in conventional analog circuits is long and lockin signal between the shortcomings such as precision is low, not only system debug is wasted time and energy, and limited for the lifting of burst transmissions timing accuracy; Existing lock-out pulse wireless low jitter transmission method, the low jitter transmission of its pulse need to, take spread bandwidth as cost, cause the waste of system resource.The wireless low jitter transmission method of the high accuracy number asynchronous pulse that the present invention proposes, the synchronised clock that produces pulse is provided without system, less demanding to system clock, reduce the design difficulty of modulation /demodulation, without expanding system bandwidth, realized the total digitalization design of system, system processing accuracy is higher, more easily debugging.
2, the main circuit parts of the inventive method adopt FPGA or ASIC to realize, and high conformity, easily realizes the wireless transmission that pulse jitter is less than 3ns.
Accompanying drawing explanation
Fig. 1 is the electric functional-block diagram of the wired side signal of the present invention to wireless side inter-process embodiment.
Fig. 2 is the electric functional-block diagram of wireless side signal of the present invention to wired side inter-process embodiment.
In Fig. 1,1 is shaping pulse module, and 2 is time figure conversion module, and 3 is impulse sampling, coding, modulation module, and 4 is D/A switch module, and 5 is radio frequency unit module.Wherein time figure conversion module is generally by trigger, the device compositions such as amplifier, impulse sampling, coding, modulation module are generally made up of FPGA or ASIC, and radio frequency unit module generally comprises the parts such as local oscillator, I/Q modulator, upconverter, power amplifier, antenna.
In Fig. 2,6 is radio frequency unit module, 7 is mould/number conversion module, 8 is interpolation filtering module, and 9 is matched filtering module, and 10 is carrier recovery block, 11 is information judging module, 12 is timing error estimation module, and 13 is loop filtering module, and 14 is numerical control NCO module, 15 is decoding matching module, and 16 is pulse-recovery module.Wherein radio frequency unit module generally comprises the parts such as antenna, low noise amplifier, low-converter, AGC, i/q demodulator, local oscillator.
Embodiment
Referring to figs. 1 through Fig. 2.Fig. 1 is the electric functional-block diagram of the wired side signal of the present invention to wireless side inter-process embodiment, and it comprises shaping pulse module 1, time figure modular converter 2, impulse sampling, coding, modulation module 3, D/A switch module 4, radio frequency unit module 5; Wherein shaping pulse module 1, time figure modular converter 2, impulse sampling, coding, modulation module 3, D/A switch module 4 forms modulating unit.Shaping pulse module 1 completes the pulse straightening in Wireline transmission; The time difference between the asynchronous pulse signal after shaping pulse and rising edge or the trailing edge of local clock is converted into digital signal by time figure modular converter 2; Impulse sampling, coding, modulation module 3 are to step 2) generate digital signal carry out impulse sampling, coding and modulation, generate comprise pulse information and time difference information digital modulation signals; D/A switch module 4 is carried out D/A switch to digital modulation signals, is converted to modulated-analog signal; Modulated-analog signal is transformed to radiofrequency signal by radio frequency unit module 5 and enters wireless transmission.
Fig. 2 is the electric functional-block diagram of wireless side signal of the present invention to wired side inter-process embodiment, it comprises radio frequency unit module 6, mould/number conversion module 7, interpolation filtering module 8, matched filtering module 9, carrier recovery block 10, information judging module 11, timing error estimation module 12, loop filtering module 13, numerical control NCO module 14, decoding matching module 15, pulse-recovery module 16; Wherein mould/number conversion module 7, interpolation filtering module 8, matched filtering module 9, carrier recovery block 10, information judging module 11, timing error estimation module 12, loop filtering module 13, numerical control NCO module 14, decoding matching module 15, pulse-recovery module 16 forms demodulating unit.The radiofrequency signal of wireless transmission is transformed to analogue zero intermediate-freuqncy signal by radio frequency unit module 6; Analogue zero intermediate-freuqncy signal enters mould/number conversion module 7, is converted to digital zero intermediate-freuqncy signal; Utilize interpolation filtering module 8, the sampled value of digital zero intermediate frequency signals is carried out to digital interpolation, by timing error estimation module 12, loop filtering module 13, the feedback loop that numerical control NCO module 14 forms obtains the fractional spaced and basic point of interpolation in optimal sampling position, for interpolation filter module and pulse-recovery module, then pass through matched filtering module 9, carrier recovery block 10, information judging module 11, decoding matching module 15, pulse-recovery module 16 completes digital demodulation, decoding, pulse-recovery; The asynchronous pulse signal of final output low jitter.
The signal transmission of technical solution of the present invention is carried out according to the following steps:
Transmitting terminal:
1) input asynchronous pulse signal is carried out to shaping pulse, realize the pulse straightening in Wireline transmission, embodiment is completed by the pulse shaping module 1 in Fig. 1;
2) adopt time figure modular converter that the time difference between the asynchronous pulse signal after shaping pulse and rising edge or the trailing edge of local clock is converted into digital signal, embodiment is completed by the time figure modular converter 2 in Fig. 1;
3) to step 2) generate digital signal carry out impulse sampling, coding and modulation, form digital modulation signals; In digital modulation signals, include pulse information and time difference information, embodiment is completed by the impulse sampling in Fig. 1, coding, modulation module 3;
4) digital modulation signals is carried out to D/A switch, be converted to modulated-analog signal, embodiment is completed by the D/A switch module 4 in Fig. 1;
5) radio frequency unit carries out up-conversion and power amplification to modulated-analog signal, is converted to high-frequency signal, and high-frequency signal is sent into wireless channel by antenna, and embodiment is completed by the radio frequency unit module 5 in Fig. 1;
Receiving terminal:
6) radio frequency unit passes through the high-frequency signal in antenna reception wireless channel, and high-frequency signal is carried out after low noise amplification, down-conversion and AGC amplify being converted to analogue zero intermediate-freuqncy signal, and embodiment is completed by the radio frequency unit module 6 in Fig. 2;
7) analogue zero intermediate-freuqncy signal is carried out to mould/number conversion, be converted to digital zero intermediate-freuqncy signal, embodiment is completed by the mould/number conversion module 7 in Fig. 2;
8) the fractional spaced and basic point of interpolation in the optimal sampling position that feeds back according to numerical control NCO unit, carries out digital interpolation to the sampled value of digital zero intermediate frequency signals, and embodiment is completed by the interpolation filtering module 8 in Fig. 2;
9) baseband signal after digital interpolation is carried out to matched filtering, embodiment is completed by the matched filtering module 9 in Fig. 2;
10) signal after matched filtering is carried out to carrier wave recovery, the frequency deviation producing in transmitting procedure for compensating signal and skew, embodiment is completed by the carrier recovery block 10 in Fig. 2;
11) time domain waveform of signal after carrier wave recovery is adjudicated; Afterwards, proceed to step 12) and step 15), embodiment is completed by the information judging module 11 in Fig. 2 simultaneously;
12) the court verdict information obtaining according to step 11), adopts Gardner algorithm, estimates the timing error information of the rear signal of carrier wave recovery, and embodiment is completed by the timing error estimation module 12 in Fig. 2;
13) timing error information estimating is passed through to loop filtering module filtering noise, embodiment is completed by the loop filtering module 13 in Fig. 2;
14) numerical control NCO unit calculates the fractional spaced and basic point of interpolation in optimal sampling position according to the timing error information that estimates; Proceed to step 8), embodiment is completed by the numerical control NCO module 14 in Fig. 2;
15) court verdict information step 11) being obtained is carried out decoding coupling, and embodiment is completed by the decoding matching module 15 in Fig. 2;
16) the optimal sampling position that provides according to numerical control NCO unit is fractional spaced carries out pulse-recovery to the signal after decoding coupling, the asynchronous pulse signal of output low jitter, and embodiment is completed by the pulse-recovery module 16 in Fig. 2.
Claims (1)
1. a wireless low jitter transmission method for high accuracy number asynchronous pulse, is characterized in that comprising step:
Transmitting terminal:
1) input asynchronous pulse signal is carried out to shaping pulse, realize the pulse straightening in Wireline transmission;
2) adopt time figure modular converter that the time difference between the asynchronous pulse signal after shaping pulse and rising edge or the trailing edge of local clock is converted into digital signal;
3) to step 2) generate digital signal carry out impulse sampling, coding and modulation, form digital modulation signals; In digital modulation signals, include pulse information and time difference information;
4) digital modulation signals is carried out to D/A switch, be converted to modulated-analog signal;
5) radio frequency unit carries out up-conversion and power amplification to modulated-analog signal, is converted to high-frequency signal, and high-frequency signal is sent into wireless channel by antenna;
Receiving terminal:
6) radio frequency unit passes through the high-frequency signal in antenna reception wireless channel, and high-frequency signal is carried out after low noise amplification, down-conversion and AGC amplify being converted to analogue zero intermediate-freuqncy signal;
7) analogue zero intermediate-freuqncy signal is carried out to mould/number conversion, be converted to digital zero intermediate-freuqncy signal;
8) the fractional spaced and basic point of interpolation in the optimal sampling position that feeds back according to numerical control NCO unit, carries out digital interpolation to the sampled value of digital zero intermediate frequency signals;
9) baseband signal after digital interpolation is carried out to matched filtering;
10) signal after matched filtering is carried out to carrier wave recovery, the frequency deviation producing in transmitting procedure for compensating signal and skew;
11) time domain waveform of signal after carrier wave recovery is adjudicated; Afterwards, proceed to step 12 simultaneously) and step 15);
12) according to step 11) the court verdict information that obtains, adopt Gardner algorithm, the timing error information of signal after estimating carrier wave and recovering;
13) timing error information estimating is passed through to loop filtering module filtering noise;
14) numerical control NCO unit calculates the fractional spaced and basic point of interpolation in optimal sampling position according to the timing error information that estimates; Proceed to step 8);
15) to step 11) the court verdict information that obtains carries out decoding coupling;
16) the optimal sampling position that provides according to numerical control NCO unit is fractional spaced carries out pulse-recovery to the signal after decoding coupling, the asynchronous pulse signal of output low jitter;
Complete the wireless low jitter transmission of high accuracy number asynchronous pulse.
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109314625A (en) * | 2016-06-10 | 2019-02-05 | At&T知识产权部有限合伙公司 | For the method and apparatus with the radio distributing antenna system with internal reference signals |
CN111371450A (en) * | 2020-03-20 | 2020-07-03 | 中国电子科技集团公司第五十四研究所 | High-precision low-jitter clock recovery system |
CN111896078A (en) * | 2020-07-09 | 2020-11-06 | 合肥联睿微电子科技有限公司 | Bluetooth communication-based meter calibration method |
CN114301552A (en) * | 2022-01-06 | 2022-04-08 | 中电科思仪科技股份有限公司 | Digital modulation signal testing method and system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5710517A (en) * | 1995-08-01 | 1998-01-20 | Schlumberger Technologies, Inc. | Accurate alignment of clocks in mixed-signal tester |
CN102684653A (en) * | 2012-05-29 | 2012-09-19 | 中国电子科技集团公司第五十四研究所 | Digital synchronous pulse wireless low-jitter transmission method |
CN102820872A (en) * | 2012-08-27 | 2012-12-12 | 中国电子科技集团公司第五十四研究所 | Wireless low-jitter transmission method for digital asynchronous pulse |
-
2014
- 2014-04-15 CN CN201410150428.4A patent/CN103905015B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5710517A (en) * | 1995-08-01 | 1998-01-20 | Schlumberger Technologies, Inc. | Accurate alignment of clocks in mixed-signal tester |
CN102684653A (en) * | 2012-05-29 | 2012-09-19 | 中国电子科技集团公司第五十四研究所 | Digital synchronous pulse wireless low-jitter transmission method |
CN102820872A (en) * | 2012-08-27 | 2012-12-12 | 中国电子科技集团公司第五十四研究所 | Wireless low-jitter transmission method for digital asynchronous pulse |
Non-Patent Citations (1)
Title |
---|
翟海涛: "高速数传系统中匹配滤波及定时同步算法改进及实现研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》, no. 2, 15 December 2011 (2011-12-15) * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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CN109314625A (en) * | 2016-06-10 | 2019-02-05 | At&T知识产权部有限合伙公司 | For the method and apparatus with the radio distributing antenna system with internal reference signals |
CN111371450A (en) * | 2020-03-20 | 2020-07-03 | 中国电子科技集团公司第五十四研究所 | High-precision low-jitter clock recovery system |
CN111371450B (en) * | 2020-03-20 | 2022-12-09 | 中国电子科技集团公司第五十四研究所 | High-precision low-jitter clock recovery system |
CN111896078A (en) * | 2020-07-09 | 2020-11-06 | 合肥联睿微电子科技有限公司 | Bluetooth communication-based meter calibration method |
CN111896078B (en) * | 2020-07-09 | 2022-05-13 | 合肥联睿微电子科技有限公司 | Bluetooth communication-based meter calibration method |
CN114301552A (en) * | 2022-01-06 | 2022-04-08 | 中电科思仪科技股份有限公司 | Digital modulation signal testing method and system |
CN114301552B (en) * | 2022-01-06 | 2023-09-26 | 中电科思仪科技股份有限公司 | Digital modulation signal testing method and system |
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