CN103926568A - Balance feed sampling receiver - Google Patents
Balance feed sampling receiver Download PDFInfo
- Publication number
- CN103926568A CN103926568A CN201410181280.0A CN201410181280A CN103926568A CN 103926568 A CN103926568 A CN 103926568A CN 201410181280 A CN201410181280 A CN 201410181280A CN 103926568 A CN103926568 A CN 103926568A
- Authority
- CN
- China
- Prior art keywords
- sampling
- pulse signal
- circuit
- resistance
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
Abstract
The invention provides a balance feed sampling receiver. The balance feed sampling receiver comprises a sampling pulse signal generating circuit, a sample integral retaining circuit and a differential amplification circuit, wherein the sampling pulse signal generating circuit is used for shaping a double-end drive pulse signal to generate a pair of balanced picosecond sampling pulse signals, the front end of the sample integral retaining circuit is electrically connected to the sampling pulse signal generating circuit and the input end of a pulse signal to be sampled, the sample integral retaining circuit is used for carrying out downsampling on the pulse signal to be sampled through the balanced picosecond sampling pulse signals and carrying out underclocking and reconstructing on the base band waveform of the pulse signal to be sampled, the front end of the differential amplification circuit is electrically connected to the sampling integral retaining circuit, and the differential amplification circuit is used for carrying out differential amplification processing on the base band waveform of the reconstructed pulse signal to be sampled and obtaining a low-frequency base band signal widened in the time domain. The balance feed sampling receiver can integrally reconstruct the pulse signal to be sampled, the sampling bandwidth is high and adjustable, and the application requirement of an ultra wide band radar system is met.
Description
Technical field
The present invention relates to electronic technology field, relate in particular to a kind of balanced feeding sampling receiver.
Background technology
The application in society now of ULTRA-WIDEBAND RADAR and communication system is very extensive, such as road surface survey, the inner reinforcing bar detection of bridge, geophysical survey, liquid plane sense should, the detection of unexploded ordnance and classification, mineral exploration, the short range communications of interior of building etc.Ultra-wideband pulse is owing to having the extremely narrow duration of pulse, can effective immune external interference, improve signal transmission rate, and ULTRA-WIDEBAND RADAR is surveyed and had very high detection accuracy and range resolution.Therefore, increasing radar system all adopts transmitted information.For wide band impulse ejection signal, receiver, when Real-time Collection echoed signal, use A/D conversion chip at a high speed, makes system cost higher, and the frequency band that transmits is when too high, and the high-speed a/d on market is also difficult to meet application demand now.So adopt equivalent sampling receiver to gather radar echo signal in a large amount of radio ultra wide band systems, to reduce the demand to data switching rate.
In realizing process of the present invention, applicant finds that in prior art, equivalent sampling receiver is mainly divided into single-ended sampling and balance sampled form, the dynamic range of single-ended sampling receiver is less, and can not directly be connected with conventional dipole antenna, easily between antenna feed point and receiver inlet, produce reflected signal, affect the Effect on Detecting of ULTRA-WIDEBAND RADAR system.
Summary of the invention
(1) technical matters that will solve
In view of above-mentioned technical matters, the invention provides a kind of balanced feeding sampling receiver, to improve as far as possible sampling bandwidth, complete reconstructed sample echoed signal.
(2) technical scheme
Balanced feeding sampling receiver of the present invention comprises: sampling pulse signal circuit for generating, for both-end drive pulse signal is carried out to the sampling pulse signal that shaping produces the picosecond of a pair of balance; Sampling integration holding circuit, its front end is electrically connected to sampling pulse signal circuit for generating and treats sampling pulse signal input end, for utilizing the sampling pulse signal of the picosecond of balance to treat sampling pulse signal, carry out down-sampling, sampling pulse signal baseband waveform is treated in frequency reducing reconstruct; And differential amplifier circuit, its front end is electrically connected to sampling integration holding circuit, for the sampling pulse signal baseband waveform for the treatment of to reconstruct, carries out differential amplification processing, obtains in low frequency baseband signal broadened in time domain.
(3) beneficial effect
The sampling pulse signal circuit for generating that ultra broadband balanced feeding sampling receiver of the present invention utilizes step-recovery diode (SRD) to form produces the sampling Gauss narrow pulse signal of the picosecond of a pair of balance, required sampling pulse signal is provided to sampling integration holding circuit; In sampling integration holding circuit, the balanced sample integration holding circuit that adopts integrated sampling gate chip, sampling integrating capacitor and impact damper holding circuit to form is treated sampling pulse signal and is carried out down-sampling, send into again differential amplifier circuit and carry out signal amplification, complete reconstruct and the extraction of sampling pulse signal treated in realization, obtain its low frequency baseband signal broadened in time domain, the performance requirement of reduction to A/D conversion chip, saves cost.The receiver structure of this invention is simple, function admirable, is easy to miniaturization integrated, can complete reconstruct treat sampling pulse signal, and sampling bandwidth is high and adjustable, meets the application demand of ULTRA-WIDEBAND RADAR system.
Accompanying drawing explanation
Fig. 1 is according to the structural representation of embodiment of the present invention balanced feeding sampling receiver;
Fig. 2 is the circuit diagram of drive signal generation circuit and sampling pulse signal circuit for generating in balanced feeding sampling receiver shown in Fig. 1;
Fig. 3 is the circuit diagram of integration maintenance amplifying circuit of sampling in balanced feeding sampling receiver shown in Fig. 1.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.It should be noted that, in accompanying drawing or instructions description, similar or identical part is all used identical figure number.The implementation that does not illustrate in accompanying drawing or describe is form known to a person of ordinary skill in the art in affiliated technical field.In addition, although the demonstration of the parameter that comprises particular value can be provided herein, should be appreciated that, parameter is without definitely equaling corresponding value, but can in acceptable error margin or design constraint, be similar to corresponding value.The direction term of mentioning in embodiment, such as " on ", D score, 'fornt', 'back', " left side ", " right side " etc., be only the direction with reference to accompanying drawing.Therefore, the direction term of use is to be not used for limiting the scope of the invention for explanation.
The present invention adopts radio frequency triode, step-recovery diode (SRD) to form sampling pulse signal circuit for generating, utilize integrated sampling gate chip, sampling integrating capacitor and impact damper holding circuit to form balanced sample integration holding circuit, use integrated differential amplifier to form differential amplifier circuit, treat sampling pulse signal and carry out down-sampling, can complete reconstruct treat sampling pulse signal, sampling bandwidth is high and adjustable, the performance requirement of reduction to A/D conversion chip, save cost, can meet the application demand of ULTRA-WIDEBAND RADAR system.
In one exemplary embodiment of the present invention, provide a kind of balanced feeding sampling receiver.Fig. 1 is according to the structural representation of embodiment of the present invention balanced feeding sampling receiver.
In the present embodiment, adopt a pulse signal generator to simulate generation and treat sampling pulse signal.This pulse signal generator generation amplitude is ± 0.7V, and pulse width is 1ns, and the positive polarity of a pair of symmetry that signal repetition frequency is 500kHz treats that sampling pulse signal and negative polarity treat sampling pulse signal.
The present invention is not as limit, this treats that sampling pulse signal can also be the sinusoidal signal of a pair of single spin-echo, triangular signal or square-wave signal, also can be periodicity radar echo signal, this amplitude for the treatment of sampling pulse signal can be between between ± 0.1V～± 1.5V, pulse width can be between 500ps～1us, and signal repetition frequency can be between 100KHz～2MHz.
Please refer to Fig. 1, Fig. 2 and Fig. 3, the present embodiment balanced feeding sampling receiver comprises: trigger pip produces circuit, for generation of single-ended trigger pip; Drive signal generation circuit, its front end is electrically connected to trigger pip and produces circuit, for utilizing the single-ended trigger pip of input to produce both-end drive pulse signal; Sampling pulse signal circuit for generating, its front end is electrically connected to drive signal generation circuit, for both-end drive pulse signal being carried out to the sampling pulse signal of the equilibratory picosecond of shaping; Sampling integration holding circuit, its front end is electrically connected to sampling pulse signal circuit for generating and treats sampling pulse signal input end, for utilizing the sampling pulse signal of the picosecond of balance to treat sampling pulse signal, carry out down-sampling, sampling pulse signal baseband waveform is treated in frequency reducing reconstruct; And differential amplifier circuit, its front end is electrically connected to sampling integration holding circuit, for the sampling pulse signal baseband waveform for the treatment of to reconstruct, carries out differential amplification processing, obtains in low frequency baseband signal broadened in time domain.
Below respectively each ingredient of the present embodiment balanced feeding sampling receiver is elaborated.
1, trigger pip produces circuit
In the present embodiment, it is a square-wave generator that trigger pip produces circuit, and its generation amplitude is 5V, and pulse width is 30ns, the square-wave signal that signal repetition frequency is 500kHz.
The present invention is not as limit, and the amplitude of this trigger pip can be between 3V～10V, and pulse width can be between 10ns～100ns, and signal repetition frequency can be between 100KHz～2MHz.
In addition, in the present invention, also can not comprise this single-ended trigger pip and produce circuit, and directly by external world's input, be met a single-ended trigger pip of above-mentioned condition, can realize the present invention equally.
2, drive signal generation circuit
Fig. 2 is the schematic diagram of drive signal generation circuit and sampling pulse signal circuit for generating in balanced feeding sampling receiver shown in Fig. 1.Please refer to Fig. 2, this drive signal generation circuit comprises: radio frequency transistor switching circuit and charge-discharge circuit.Wherein:
Radio frequency transistor switching circuit, wherein, the base stage of radio frequency triode Q1 (BFG35) is connected to single-ended trigger pip input end, and collector is connected to positive source+VCC by the first resistance R 1, and emitter is connected to power cathode-VCC by the second resistance R 2;
Charge-discharge circuit, comprising: the first charge and discharge capacitance C1, and its first end is electrically connected to the collector of radio frequency triode Q1; The second charge and discharge capacitance C2, its first end is electrically connected to the emitter of radio frequency triode Q1;
The both-end drive pulse signal that this drive signal generation circuit produces is exported by the second end of the first charge and discharge capacitance C1 and the second end of the second charge and discharge capacitance C2.
In this drive signal generation circuit, radio frequency triode Q1 has fast conducting and closed function, in conjunction with charge-discharge circuit, single-ended trigger pip to base stage input is carried out shaping, thereby produces respectively the fast negative polarity drive pulse signal in edge and positive polarity drive pulse signal at collector and emitter.
The both-end drive pulse signal amplitude of drive signal generation circuit output can be between between ± 10V～± 15V, and pulse width can be between 10ns～80ns, and pulse repetition rate can be between 100KHz～2MHz.
In addition, in the present invention, also can not comprise this drive signal generation circuit, and directly by external world's input one, be met the both-end drive pulse signal of above-mentioned condition, can realize the present invention equally.
3, sampling pulse signal circuit for generating
Please refer to Fig. 2, this sampling pulse signal circuit for generating comprises: step-recovery diode (SRD) pulse shaping circuit and coupled circuit module.Wherein:
Step-recovery diode (SRD) pulse shaping circuit comprises: the first step-recovery diode (SRD) (SRD) D1, its positive terminal is connected to one of them negative polarity drive pulse signal input end of both-end drive pulse signal, and is connected to positive source+VCC by the 3rd resistance R 3; Its negative pole end is connected to wherein another positive polarity drive pulse signal input end of both-end drive pulse signal, and is connected to power cathode-VCC by the 4th resistance (R4); The second step-recovery diode (SRD) (SRD) D2, its positive terminal is connected to the positive terminal of the first step-recovery diode (SRD) D1 by the 3rd coupling capacitance C3, and is connected to positive source+VCC by the 5th resistance R 5; The 3rd step-recovery diode (SRD) (SRD) D3, its negative pole end is connected to the negative pole end of the first step-recovery diode (SRD) D1 by the 4th coupling capacitance C4, and is connected to power cathode-VCC by the 7th resistance R 7; Wherein, the 6th resistance R 6 of connecting between the negative pole end of the second step-recovery diode (SRD) D2 and the positive terminal of the 3rd step-recovery diode (SRD) D3.
Coupled circuit module comprises: the 5th coupling capacitance C5, and its first end is connected to the negative pole end of the second step-recovery diode (SRD) D2, and its second end is as the negative pulse output terminal of sampling pulse signal; The 6th coupling capacitance C6, its first end is connected to the positive terminal of the 3rd step-recovery diode (SRD) D3, and its second end is as the positive pulse output terminal of sampling pulse signal.
For the first step-recovery diode (SRD) D1 in step-recovery diode (SRD) pulse shaping circuit, the second step-recovery diode (SRD) D2 and the 3rd step-recovery diode (SRD) D3, under forward bias state, step-recovery diode (SRD) is in conducting state, charge storage is near the PN junction of step-recovery diode (SRD), when drive pulse signal arrives, the electric charge of storage is constantly extracted, until that electric charge is extracted is complete, step-recovery diode (SRD) becomes cut-off state from conducting state, produce step response effect, the edge of anticathode drive pulse signal and positive polarity drive pulse signal carries out shaping, produce the sampling Gauss narrow pulse signal of the picosecond of a pair of balance, wherein, the first step-recovery diode (SRD) D1 carries out shaping to the forward position of the positive polarity of balance and negative polarity drive pulse signal, shaping is carried out on the rear edge of the second step-recovery diode (SRD) D2 anticathode drive pulse signal, the 3rd step-recovery diode (SRD) D3 aligns the rear edge of polarity driven pulse signal and carries out shaping, and the sampling Gauss narrow pulse signal forward position of the picosecond of this balance and rear edge determine by the snap time of step-recovery diode (SRD).
5, sampling integration holding circuit
Fig. 3 is the schematic diagram of integration maintenance amplifying circuit of sampling in balanced feeding sampling receiver shown in Fig. 1.Please refer to Fig. 3, this sampling integration holding circuit comprises: sampling gate circuit, integration holding circuit and buffer circuits.Wherein:
Sampling gate circuit, comprise: the first sampling integrated pipe Q2, its upper end is connected to anodal bias voltage+bias voltage (+5V), be connected to the negative pulse output terminal of sampling pulse signal simultaneously, its lower end is connected to negative pole bias voltage-bias voltage (5V), be connected to the positive pulse output terminal of sampling pulse signal, its left end is connected to the negative polarity signal output part for the treatment of sampling pulse signal simultaneously, and its right-hand member is connected to the first end of the 9th resistance R 9; The second sampling integrated pipe Q3, its upper end is connected to anodal bias voltage+bias voltage, be connected to the negative pulse output terminal of sampling pulse signal simultaneously, its lower end is connected to negative pole bias voltage-bias voltage, be connected to the positive pulse output terminal of sampling pulse signal simultaneously, its left end is connected to the positive signal output terminal for the treatment of sampling pulse signal, and its right-hand member is connected to the first end of the 11 resistance R 11;
Integration holding circuit, comprising: the 8th sampling integrating capacitor C8 and the tenth resistance R 10 in parallel, and its first end is all connected to the right-hand member of the first sampling integrated pipe Q2 by the 9th resistance R 9, and its second end is all connected to ground; The 9th sampling integrating capacitor C9 and the 12 resistance R 12 in parallel, its first end is all connected to the right-hand member of the second sampling integrated pipe Q3 by the 11 resistance R 11, and its second end is all connected to ground;
Buffer circuits, comprise: two-way operational amplifier U1, the input end in the same way (pin 5) of its second road operational amplifier U1B is connected to the first end of the 8th sampling integrating capacitor C8, reverse input end (pin 6) is connected to the output terminal (pin 7) of operational amplifier U1B, and output terminal is connected to the first end of the tenth capacitor C 10; The input end in the same way (pin 3) of its first via operational amplifier U1A is connected to the first end of the 9th sampling integrating capacitor C9, reverse input end (pin 2) is connected to the output terminal (pin 1) of operational amplifier U1A, output terminal is connected to the first end of the 11 capacitor C 11, the pin 8 of two-way operational amplifier U1 is connected to positive source+VCC, and pin 4 is connected to power cathode-VCC;
This integration holding circuit of sampling, sampling pipe, under the acting in conjunction of bias voltage and sampling Gauss narrow pulse signal, becomes conducting state from cut-off state, and sampling integrating capacitor treats that sampling pulse signal is sampled and integration, realizes the accumulation to signal; Signal in sampling integrating capacitor, through the maintenance effect of impact damper, obtains the baseband signal for the treatment of sampling pulse signal through down-sampling frequency reducing reconstruct.
6, differential amplifier circuit
Please refer to Fig. 3, this differential amplifier circuit comprises: filtering match circuit and differential amplifier (U2), wherein:
Filtering match circuit, comprise: the tenth filter capacitor C10, its first end is connected to the output terminal (pin 7) of the second road operational amplifier U1B, its second end is connected to the reverse input end (pin 2) of differential operational amplifier U2, the first end of the 13 resistance R 13 is connected to the second end of the tenth filter capacitor C10, and its second end is connected to ground; The 11 filter capacitor C11, its first end is connected to the output terminal (pin 1) of first via operational amplifier U1A, its second end is connected to the input end in the same way (pin 3) of differential operational amplifier U2, the first end of the 14 resistance R 14 is connected to the second end of the 11 filter capacitor C11, and its second end is connected to ground;
Differential amplifier U2, its annexation is as follows: reverse input end is connected to the second end of the tenth filter capacitor C10; Input end is connected to the second end of the 11 filter capacitor C11 in the same way; Pin 1 is connected by the 15 resistance R 15 with pin 8; Pin 7 is connected to positive source+VCC; Pin 4 is connected to power cathode-VCC; Pin 5 is connected to ground; Pin 6 is connected to this balanced feeding sampling receiver output terminal by the 12 every straight filter capacitor C12.
In the present embodiment balanced feeding sampling receiver, radio frequency triode is high-speed switching devices, equilibratory drive pulse signal under the effect of trigger pip; The step effect of utilizing step-recovery diode (SRD), step-recovery diode (SRD) pulse shaping circuit carries out shaping to drive pulse signal, produces the sampling Gauss narrow pulse signal of the picosecond of a pair of balance at sampling pulse signal circuit for generating output terminal; Sampling pulse signal circuit for generating output terminal is connected with sampling integration holding circuit, sampling pulse signal is provided, sampling gate circuit is treated sampled signal and is sampled, sampled signal is accumulated in sampling integrating capacitor, by the maintenance effect of impact damper, acquisition broadened low frequency baseband signal in time domain, then amplifies through differential amplifier circuit, obtains sampled output signal.
In the present embodiment balanced feeding sampling receiver, the course of work of sampling pulse signal circuit for generating is as follows:
Step 1, when trigger pip is during in low level, radio frequency triode Q1 is in closing cut-off state, power supply+VCC charges by 1 pair of the first capacitor C 1 of the first resistance R, power supply-VCC charges by 2 pairs of the second capacitor C 2 of the second resistance R, and the first step-recovery diode (SRD) D1, the second step-recovery diode (SRD) D2 and the 3rd step-recovery diode (SRD) D3 are all in forward bias state;
Step 2, when trigger pip is high level by low transition, radio frequency triode Q1 fast conducting, by the charge and discharge process of the first charge and discharge capacitance C1 and the second charge and discharge capacitance C2, at the collector and emitter of radio frequency triode Q1, produce fast forward position negative polarity drive pulse signal and the positive polarity drive pulse signal of a pair of balance;
Step 3, according to the step response of step-recovery diode (SRD), SRD is stored charge when forward bias, under reverse-bias state, electric charge is extracted, until all stored charge is extracted completely, SRD ends immediately, thereby produces narrow sampling pulse signal;
The value of step 4, adjusting supply voltage+VCC ,-VCC and the first charge and discharge capacitance C1, the second charge and discharge capacitance C2 is big or small, can regulate width and the voltage amplitude of sampling pulse, and capacitance is larger, and pulse height is larger, and pulse width is also wider simultaneously.The size of+VCC ,-VCC, the resistance of the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7 is all relevant to the model of selected step-recovery diode (SRD), and those skilled in the art can choose suitable value according to the model of choosing step-recovery diode (SRD).The electric capacity of the first charge and discharge capacitance C1, the second charge and discharge capacitance C2 is equal, and value is between 100pF～10nF; The electric capacity of the 3rd coupling capacitance C3, the 4th coupling capacitance C4 is equal, and value is between 100pF～10nF; The electric capacity of the 5th coupling capacitance C5, the 6th coupling capacitance C6 is equal, and value is between 100pF～10nF; The resistance of the first resistance R 1 and the second resistance R 2 is equal, and value is between 1k Ω～5k Ω Ω.
The course of work of integration maintenance amplifying circuit of sampling in the present embodiment balanced feeding sampling receiver is as follows:
Step 1, when sampling pulse signal does not arrive, the first sampling integrated pipe Q2 and the second sampling integrated pipe Q3 under the effect of bias voltage in reverse-bias state;
Step 2, when balanced sample pulse signal arrives, when the forward bias voltage on being added in the first sampling integrated pipe Q2 and the second sampling integrated pipe Q3 is greater than the forward voltage of sampling integrated pipe, sampling integrated pipe conducting, the 8th sampling integrating capacitor C8 and the 9th sampling integrating capacitor C9 treat the sampling pulse signal integration of sampling; The maintenance effect of the two-way impact damper forming through two-way operational amplifier U1, produces and treats sampling pulse signal broadened low frequency baseband signal in time domain; Wherein, the 8th sampling integrating capacitor C8 is equal with the 9th sampling integrating capacitor C9 electric capacity, and value is between 10pF～1nF, and the tenth resistance R 10 and the 12 resistance R 12 resistance are equal, and value is between 100k Ω～1M Ω.The resistance of the 9th resistance R 9 and the 11 resistance R 11 is equal, and value is between 10 Ω～100 Ω.
The amplification of step 3, low frequency baseband signal process differential amplifier U1, finally produces sampled output signal; Wherein the tenth equates every straight filter capacitor C11 electric capacity every straight filter capacitor C10 and the 11, value is between 100nF～1uF, the 13 resistance R 13 and the 14 resistance R 14 resistance equate, value is between 10k Ω～100k Ω, the 12 coupling capacitance C12 value is between 100nF～1uF, the value of the 15 resistance R 15 is relevant to the model of differential amplification multiple and differential amplifier, and those skilled in the art can choose suitable value according to the model of required enlargement factor and differential amplifier.
Step 4, by regulate the width of sampling pulse and voltage amplitude, bias voltage+bias voltage and-size of bias voltage, can regulate the size of the aperture time of opening the door of sampling gate, thereby regulate the sampling bandwidth of receiver, the pulsewidth of sampling pulse is less, the aperture time of opening the door of sampling gate less, receiver sampling bandwidth is larger; The width General Requirements of sampling pulse is not more than 500ps, and voltage amplitude is not less than 500mV; + bias voltage and-size of bias voltage is between 2V～12V.
Actual test shows, the sampling pulse signal that in the present embodiment balanced feeding sampling receiver, sampling pulse signal circuit for generating produces, pulse width is at 180ps～300ps, for picosecond magnitude, crest voltage amplitude is ± 3.5V～+ 4.5V, positive negative pulse stuffing symmetry is good, and the hangover of main pulse rear end is little, ring level is low, has higher sampling bandwidth; The integration maintenance amplifying circuit of sampling in the present embodiment balanced feeding sampling receiver, under the effect of sampling pulse, sampling pulse signal waveform is treated in down-sampling frequency reducing reconstruct, the signal waveform of reconstruct is low frequency baseband signal broadened in time domain, treat that with former sampling pulse signal waveform is almost consistent, without clutter and hangover, introduce; This invention sampling bandwidth is high, and applicable pulse repetition rate is high, the application of the ULTRA-WIDEBAND RADAR system of broader bandwidth.
So far, by reference to the accompanying drawings the present embodiment be have been described in detail.According to above, describe, those skilled in the art should have clearly understanding to balanced feeding sampling receiver of the present invention.
In addition, the above-mentioned definition to each element and method is not limited in various concrete structures, shape or the mode of mentioning in embodiment, and those of ordinary skills can change simply or replace it, for example:
(1), in the present embodiment, trigger pip produces circuit and also can be produced by fpga chip, is convenient to the system integration;
(2) give step-recovery diode (SRD) D1, D2 and D3 provide forward biased voltage source+VCC and-VCC can replace with constant current source;
(3), in the present embodiment, treat that sampling pulse signal produces circuit and also can be substituted by receiving antenna, by the synchronous radar echo signal receiving as treating sampling pulse signal;
(4) sampling integrated pipe Q2, Q3 can build with discrete radio frequency schottky diode, but must guarantee that selected radio frequency schottky diode has higher consistance, and ON time is short, is with wide.
In sum, this invention utilizes radio frequency triode and step-recovery diode (SRD) to produce the sampling Gauss narrow pulse signal of a pair of picosecond, as the sampling pulse signal of sampling integration maintenance amplifying circuit; Sampling integration maintenance amplifying circuit utilization sampling integrated pipe, sampling integrating capacitor, operational amplifier, filter capacitor and differential amplifier are treated sampling pulse signal and are carried out down-sampling under the effect of sampling pulse, sampling pulse signal is treated in reconstruct, obtains low frequency baseband signal broadened in time domain.This invention circuit structure is simple, and sampling bandwidth is high and adjustable, and sampling function admirable, can meet the application demand of ULTRA-WIDEBAND RADAR system.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (12)
1. a balanced feeding sampling receiver, is characterized in that, comprising:
Sampling pulse signal circuit for generating, for carrying out to both-end drive pulse signal the sampling pulse signal that shaping produces the picosecond of a pair of balance;
Sampling integration holding circuit, its front end is electrically connected to sampling pulse signal circuit for generating and treats sampling pulse signal input end, for utilizing the sampling pulse signal of the picosecond of balance to treat sampling pulse signal, carry out down-sampling, sampling pulse signal baseband waveform is treated in frequency reducing reconstruct; And
Differential amplifier circuit, its front end is electrically connected to sampling integration holding circuit, for the sampling pulse signal baseband waveform for the treatment of to reconstruct, carries out differential amplification processing, obtains in low frequency baseband signal broadened in time domain.
2. balanced feeding sampling receiver according to claim 1, is characterized in that, described sampling pulse signal circuit for generating comprises: step-recovery diode (SRD) pulse shaping circuit and coupled circuit module, wherein:
Step-recovery diode (SRD) pulse shaping circuit, comprise: the first step-recovery diode (SRD) (D1), its positive terminal is connected to one of them negative polarity drive pulse signal input end of both-end drive pulse signal, and is connected to positive source (+VCC) by the 3rd resistance (R3); Its negative pole end is connected to wherein another positive polarity drive pulse signal input end of both-end drive pulse signal, and is connected to power cathode (VCC) by the 4th resistance (R4); The second step-recovery diode (SRD) (D2), its positive terminal is connected to the positive terminal of the first step-recovery diode (SRD) (D1) by the 3rd coupling capacitance (C3), and is connected to positive source (+VCC) by the 5th resistance (R5); The 3rd step-recovery diode (SRD) (D3), its negative pole end is connected to the negative pole end of the first step-recovery diode (SRD) (D1) by the 4th coupling capacitance (C4), and is connected to power cathode (VCC) by the 7th resistance (R7); Wherein, the 6th resistance (R6) of connecting between the negative pole end of the second step-recovery diode (SRD) (D2) and the positive terminal of the 3rd step-recovery diode (SRD) (D3); And
Coupled circuit module, comprising: the 5th coupling capacitance (C5), and its first end is connected to the negative pole end of the second step-recovery diode (SRD) (D2), and its second end is as the negative pulse output terminal of sampling pulse signal; The 6th coupling capacitance (C6), its first end is connected to the positive terminal of the 3rd step-recovery diode (SRD) (D3), and its second end is as the positive pulse output terminal of sampling pulse signal.
3. balanced feeding sampling receiver according to claim 2, is characterized in that, the electric capacity of described the 3rd coupling capacitance (C3) and the 4th coupling capacitance (C4) is equal, and value is between 100pF～10nF; The electric capacity of described the 5th coupling capacitance (C5) and the 6th coupling capacitance (C6) is equal, and value is between 100pF～10nF.
4. balanced feeding sampling receiver according to claim 2, is characterized in that, described sampling integration holding circuit comprises: sampling gate circuit, integration holding circuit and buffer circuits, wherein:
Sampling gate circuit, comprise: the first sampling integrated pipe (Q2), its upper end is connected to anodal bias voltage (+bias voltage), be connected to the negative pulse output terminal of sampling pulse signal simultaneously, its lower end is connected to negative pole bias voltage (bias voltage), be connected to the positive pulse output terminal of sampling pulse signal, its left end is connected to the negative polarity signal output part for the treatment of sampling pulse signal simultaneously; And second sampling integrated pipe (Q3), its upper end is connected to anodal bias voltage, be connected to the negative pulse output terminal of sampling pulse signal simultaneously, its lower end is connected to negative pole bias voltage, be connected to the positive pulse output terminal of sampling pulse signal, its left end is connected to the positive signal output terminal for the treatment of sampling pulse signal simultaneously;
Integration holding circuit, comprise: the 8th sampling integrating capacitor (C8) and the tenth resistance (R10) in parallel, both first ends are all connected to the right-hand member of the first sampling integrated pipe (Q2) by the 9th resistance (R9), its second end is all connected to ground; And the 9th sampling integrating capacitor (C9) and the 12 resistance (R12) in parallel, both first ends are all connected to the right-hand member of the second sampling integrated pipe (Q3) by the 11 resistance (R11), and its second end is all connected to ground; And
Buffer circuits, comprise: two-way operational amplifier (U1), this two-way operational amplifier (U1) comprising: the input end in the same way of the second road operational amplifier (U1B) (pin 5) is connected to the first end of the 8th sampling integrating capacitor (C8), reverse input end (pin 6) is connected to the output terminal (pin 7) of the second road operational amplifier (U1B), and output terminal is as the second output terminal of sampling integration holding circuit; The input end in the same way of first via operational amplifier (U1A) (pin 3) is connected to the first end of the 9th sampling integrating capacitor (C9), reverse input end (pin 2) is connected to the output terminal (pin 1) of first via operational amplifier (U1A), and output terminal is as the first output terminal of sampling integration holding circuit; Wherein, the pin 8 of first via operational amplifier (U1A) and the second road operational amplifier (U1B) is connected to positive source (+VCC), and pin 4 is connected to power cathode (VCC).
5. balanced feeding sampling receiver according to claim 4, is characterized in that, described the 8th sampling integrating capacitor (C8) is equal with the 9th sampling integrating capacitor (C9) electric capacity, and value is between 10pF～1nF; Described the tenth resistance (R10) and the 12 resistance (R12) resistance are equal, and value is between 100k Ω～1M Ω; The resistance of described the 9th resistance (R9) and the 11 resistance (R11) is equal, and value is between 10 Ω～100 Ω.
6. balanced feeding sampling receiver according to claim 4, is characterized in that, the voltage magnitude of described anodal bias voltage (+bias voltage) and negative pole bias voltage (bias voltage) is between 2V～12V.
7. balanced feeding sampling receiver according to claim 4, is characterized in that, described differential amplifier circuit comprises: filtering match circuit and differential amplifier (U2), wherein:
Filtering match circuit, comprising: the tenth filter capacitor (C10), and its first end is connected to the output terminal of the second road operational amplifier (U1B), and its second end is connected to ground by the 13 resistance (R13); The 11 filter capacitor (C11), its first end is connected to the output terminal of first via operational amplifier (U1A), and its second end is connected to ground by the 14 resistance (R14);
Differential amplifier (U2), its reverse input end (pin 2) is connected to the second end of the tenth filter capacitor (C10); Input end (pin 3) is connected to the second end of the 11 filter capacitor (C11) in the same way; Pin 1 is connected by the 15 resistance (R15) with pin 8; Pin 7 is connected to positive source (+VCC); Pin 4 is connected to power cathode (VCC); Pin 5 is connected to ground; Pin 6 is connected to this balanced feeding sampling receiver output terminal by the 12 every straight filter capacitor (C12).
8. balanced feeding sampling receiver according to claim 7, is characterized in that: the described the tenth equates every straight filter capacitor (C11) electric capacity every straight filter capacitor (C10) and the 11, and value is between 100nF～1uF; Described the 13 resistance (R13) and the 14 resistance (R14) resistance are equal, and value is between 10k Ω～100k Ω; Described the 12 coupling capacitance (C12) value is between 100nF～1uF.
9. according to the balanced feeding sampling receiver described in any one in claim 1 to 8, it is characterized in that, also comprise:
Drive signal generation circuit, for utilizing the single-ended trigger pip of input to produce both-end drive pulse signal.
10. balanced feeding sampling receiver according to claim 9, is characterized in that, described drive signal generation circuit comprises:
Radio frequency transistor switching circuit, wherein, the base stage of radio frequency triode (Q1) is connected to single-ended trigger pip input end, collector is connected to positive source (+VCC) by the first resistance (R1), and emitter is connected to power cathode (VCC) by the second resistance (R2);
Charge-discharge circuit, comprising: the first charge and discharge capacitance (C1), and its first end is electrically connected to the collector of radio frequency triode (Q1); The second charge and discharge capacitance (C2), its first end is electrically connected to the emitter of radio frequency triode (Q1);
The both-end drive pulse signal that this drive signal generation circuit produces is by the second end output of the second end and second charge and discharge capacitance (C2) of the first charge and discharge capacitance (C1).
11. balanced feeding sampling receivers according to claim 10, is characterized in that, the resistance of described the first resistance (R1) and the second resistance (R2) is equal, and value is between 1k Ω～5k Ω; The electric capacity of the first charge and discharge capacitance (C1), the second charge and discharge capacitance (C2) is equal, and value is between 100pF～10nF.
12. according to the balanced feeding sampling receiver described in any one in claim 1 to 8, it is characterized in that, also comprises: trigger pip produces circuit, for generation of single-ended trigger pip;
It is square-wave generator that this trigger pip produces circuit, and the amplitude of its generation unit trigger pip is between 3V～10V, and pulse width is between 10ns～100ns, and signal repetition frequency is between 100KHz～2MHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410181280.0A CN103926568B (en) | 2014-04-30 | 2014-04-30 | Balanced feeding sampling receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410181280.0A CN103926568B (en) | 2014-04-30 | 2014-04-30 | Balanced feeding sampling receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103926568A true CN103926568A (en) | 2014-07-16 |
| CN103926568B CN103926568B (en) | 2016-08-24 |
Family
ID=51144857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410181280.0A Active CN103926568B (en) | 2014-04-30 | 2014-04-30 | Balanced feeding sampling receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103926568B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105203912A (en) * | 2015-10-27 | 2015-12-30 | 西安浩能电气科技有限公司 | Steep front edge index repeat pulse generating device used for generator rotor inter-turn short circuit |
| CN106772269A (en) * | 2017-03-03 | 2017-05-31 | 南京邮电大学 | A kind of equivalent sampling circuit of application ground penetrating radar echo signals collection |
| CN107192989A (en) * | 2017-06-13 | 2017-09-22 | 电子科技大学 | A kind of microwave radio receiver |
| CN110943607A (en) * | 2019-12-20 | 2020-03-31 | 武汉永力科技股份有限公司 | Single-cycle three-phase six-switch power factor correction PWM modulator |
| US10686643B1 (en) | 2019-03-04 | 2020-06-16 | International Business Machines Corporation | Discrete time analog front end circuit implemented in a receiver device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5345471A (en) * | 1993-04-12 | 1994-09-06 | The Regents Of The University Of California | Ultra-wideband receiver |
| US5523760A (en) * | 1993-04-12 | 1996-06-04 | The Regents Of The University Of California | Ultra-wideband receiver |
| CN102121983A (en) * | 2010-01-07 | 2011-07-13 | 中国科学院电子学研究所 | Ultra-wideband radar pulse transmitter and method |
-
2014
- 2014-04-30 CN CN201410181280.0A patent/CN103926568B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5345471A (en) * | 1993-04-12 | 1994-09-06 | The Regents Of The University Of California | Ultra-wideband receiver |
| US5523760A (en) * | 1993-04-12 | 1996-06-04 | The Regents Of The University Of California | Ultra-wideband receiver |
| CN102121983A (en) * | 2010-01-07 | 2011-07-13 | 中国科学院电子学研究所 | Ultra-wideband radar pulse transmitter and method |
Non-Patent Citations (2)
| Title |
|---|
| 李奎芳等: "平衡取样积分电路分析及应用", 《长江大学学报（自然版）》, vol. 3, no. 4, 31 December 2006 (2006-12-31), pages 34 - 36 * |
| 赵陈亮: "典型超宽带信号的发射与接收技术", 《中国优秀硕士学位论文全文数据库 信息科技辑》, 15 July 2013 (2013-07-15), pages 57 - 59 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105203912A (en) * | 2015-10-27 | 2015-12-30 | 西安浩能电气科技有限公司 | Steep front edge index repeat pulse generating device used for generator rotor inter-turn short circuit |
| CN106772269A (en) * | 2017-03-03 | 2017-05-31 | 南京邮电大学 | A kind of equivalent sampling circuit of application ground penetrating radar echo signals collection |
| CN107192989A (en) * | 2017-06-13 | 2017-09-22 | 电子科技大学 | A kind of microwave radio receiver |
| US10686643B1 (en) | 2019-03-04 | 2020-06-16 | International Business Machines Corporation | Discrete time analog front end circuit implemented in a receiver device |
| CN110943607A (en) * | 2019-12-20 | 2020-03-31 | 武汉永力科技股份有限公司 | Single-cycle three-phase six-switch power factor correction PWM modulator |
| CN110943607B (en) * | 2019-12-20 | 2021-04-06 | 武汉永力科技股份有限公司 | Single-cycle three-phase six-switch power factor correction PWM modulator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103926568B (en) | 2016-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103926568A (en) | Balance feed sampling receiver | |
| CN102147460B (en) | System and method for receiving ultra wide band pulsed radar | |
| CN102121983B (en) | Ultra-wideband radar pulse transmitter and method | |
| CN103731123B (en) | A kind of ultra-wideband impulse signal generation device based on memristor | |
| CN101964647A (en) | Pulse width signal duty ratio detection circuit | |
| US20210359668A1 (en) | Narrow pulse generation circuit used in sequential equivalent sampling system | |
| CN106772269B (en) | Equivalent sampling circuit for echo signal acquisition by using ground penetrating radar | |
| CN103227624B (en) | Second-order differential Gaussian pulse generator based on SRD | |
| CN202424487U (en) | IGBT drive circuit being cable to generate turn-off reverse voltage | |
| CN103929089B (en) | Fast rise time step pulse generator | |
| CN104639094A (en) | Filtering circuit | |
| CN203858282U (en) | Intermediate-frequency broadband digital peak detection circuit | |
| CN104052435A (en) | Amplitude increasing and width reducing circuit unit and pulse signal generating circuit and generator comprising amplitude increasing and width reducing circuit unit | |
| CN208316694U (en) | A kind of narrow-pulse generation circuit in sequential equivalent system | |
| CN107241085A (en) | Significantly Gao Zhongying nanosecond equalizing pulse signal generator | |
| CN205961074U (en) | Tunable formula ultra wide band burst pulse that triggers produces device | |
| CN101119109A (en) | Waveform shaping circuit | |
| CN110347096A (en) | A kind of equivalent sampling circuit based on delays time to control | |
| CN208621756U (en) | Moment discrimination circuit system | |
| CN101726729B (en) | High-precision receiver of geological radar | |
| CN210244120U (en) | Equivalent sampling circuit based on time delay control | |
| CN205899029U (en) | Laser drive circuit and laser rangefinder | |
| CN205643698U (en) | Ultrasonic emission circuit and range unit and car and aircraft and robot | |
| CN106441561A (en) | Miniaturized swing infrared circuit system | |
| Cai et al. | Design of low-cost ground penetrating radar receiving circuit based on equivalent sampling |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |