CN103926915A - Three-phase four-wire system APF control-panel debugging method - Google Patents
Three-phase four-wire system APF control-panel debugging method Download PDFInfo
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- CN103926915A CN103926915A CN201410137344.7A CN201410137344A CN103926915A CN 103926915 A CN103926915 A CN 103926915A CN 201410137344 A CN201410137344 A CN 201410137344A CN 103926915 A CN103926915 A CN 103926915A
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Abstract
Provided is a three-phase four-wire system APF control-panel debugging method. The method depends on a standard testing source which provides a voltage source and a current source, wherein the maximum effective value of three voltages of the voltage source is 57 volts, the maximum effective value of three currents of the current source is 5 amperes, the maximum harmonic number of the current source is 50, and a load current sampling channel, an inverter current sampling channel and a grid side voltage sampling channel are tested. When the load current sampling channel is tested, a primary circuit outputs a current signal through the standard source and is connected with a control panel through a 5 A/5 mA current transformer; when the inverter current sampling channel is tested, the primary circuit outputs a current signal through the standard source and is connected with the control panel through a specially customized 5 A/200 mA current transformer; when the grid side voltage sampling channel is tested, the primary circuit outputs a voltage signal through the standard source and is connected with the control panel through a specially customized 50 V/220 V voltage transformer. By means of the method, the control panel does not need to be debugged on site, and reliability of the control panel is guaranteed.
Description
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technical field
The present invention relates to a kind of three-phase four-wire system APF control panel adjustment method, belong to power matching network controlling of quality technical field.
background technology
Development along with electric system, due to the inadequate standard of the management of power use, the impact of single-phase load, electrical network general layout is unreasonable and the low-voltage network three-phase imbalance problem that causes of the problems such as timeliness of load has caused material impact to electric system, and the dynamic electric network electric energy quality of power distribution network is declined day by day.Active Power Filter-APF (Active Power Filter is called for short APF) is the effective way that solves power quality problem.Three-phase and four-line electric system works in asymmetric or non-equilibrium state conventionally, due to the existence of the neutral line, adopts phase three-wire three APF to be difficult to effectively solve harmonic problem on the neutral line and the unbalancedness of system.Simultaneously, this large-power occasions device that applies to is in development experimental cost problem and safety problem, for this problem, a kind of three-phase four-wire system APF control panel adjustment method is proposed, the method is without just completing at the scene the debugging of control panel, therefore guaranteed to a certain extent experiment safety and reduced experimental cost, and can use for reference and other large-power occasions.
summary of the invention
The object of the invention is, in order to reduce experiment risk and cost, determine the reliability of control panel before entering high-power scene, the present invention proposes a kind of three-phase four-wire system APF control panel adjustment method.
Technical scheme of the present invention is, three-phase four-wire system APF control panel adjustment method of the present invention relies on standard testing source, its maximum effective value in voltage providing three roads is that voltage source, the maximum effective value of three road electric currents of 57 volts is 5 peaces, maximum overtone order is the current source of 50 times, and load current sampling channel, inverter current sampling channel and voltage on line side sampling channel are tested.
The inventive method step is as follows:
(1) check whether three-phase four-wire system APF control panel has and disconnect or rosin joint situation that whether reversal connection of electrochemical capacitor checks whether misconnection of auxiliary power supply line;
(2) upper electro-detection three-phase four-wire system APF control chip on board whether abnormal, check on three-phase four-wire system APF control panel, whether corresponding DSP development board, FPGA development board power pins is connected;
(3) by DSP emulator, be connected with DSP development board, on CCS software, observed samples passage zero wafts situation to determine that whether respective channel is normal;
(4) by DSP emulator, be connected with DSP development board, at the scene whether the zero situation of wafing of observed samples passage on CCS software, normally work under parameter in conjunction with testing power supply checking sampling channel.
Above-mentioned three-phase four-wire system APF control panel, mainly by DSP development board, FPGA development board and separately peripheral circuit form.FPGA development board major function is to sample (comprising No. 3 inverter outputs, 3 road load currents, 1 road DC voltage, 3 road voltage on line side) for controlling AD, and threephase load current data is calculated and extracted each harmonic, the harmonic data of sampling and calculate is passed to DSP development board by bus form simultaneously.
Described testing power supply, the maximum effective value of voltage three-phase that it provides is that 57 volts, the maximum effective values of three road electric currents are 5 peaces, maximum overtone order is 50 times.
During test load current sample passage, primary circuit is by standard testing source output current signal, by the current transformer Access Control plate of a 5A/5mA;
During test inverter current sampling channel, primary circuit is by standard testing source output current signal, the current transformer Access Control plate of the 5A/200mA by a specific customization;
During Test Network side voltage sample passage, primary circuit is by standard testing source output voltage signal, by the 50V/220V voltage transformer (VT) Access Control plate of a specific customization; With standard testing source, in conjunction with the mode of specific mutual inductor, make to simulate each sampling channel on-site parameters value.
Described peripheral circuit comprises signal conditioning circuit, A/D convertor circuit, holding circuit, zero passage comparator circuit etc.
The invention has the beneficial effects as follows, the present invention, without just completing at the scene the debugging of control panel, has guaranteed the reliability of control panel, has greatly reduced experiment safety hidden danger and experimental cost, in relevant large-power occasions, has general versatility.
accompanying drawing explanation
Fig. 1 is three-phase four-wire system APF topological structure schematic diagram in the present invention;
Fig. 2 is three-phase four-wire system APF control panel hardware block diagram in the present invention;
Fig. 3 is three-phase four-wire system APF control panel debugging schematic diagram in the present invention;
Fig. 4 is standard testing power supply schematic diagram.
Embodiment
As shown in Figure 1, Fig. 1 is parallel connection type (pouring-in) three-phase four-wire system APF topological structure schematic diagram.Detection & Controling partly comprise each voltage, current signal detection, instruction current computing circuit, current tracking control circuit, driving circuit, main circuit.Testing circuit is sampled and by ordering calculation circuit, is carried out the calculating of dependent instruction correlation parameter, then and the instruction calculating is delivered to circuit tracing control circuit, and then through driving circuit, main circuit is controlled, form a closed-loop control system.
As shown in Figure 2, Fig. 2 is three-phase four-wire system APF control panel hardware structure diagram.Mainly by DSP development board, FPGA development board, signal conditioning circuit, A/D convertor circuit, holding circuit and zero passage comparator circuit, formed.Signal conditioning circuit connects respectively A/D convertor circuit and holding circuit; A/D convertor circuit connects FPGA development board; FPGA development board connects DSP development board; DSP development board one tunnel connects holding circuit, and a road connects faulty circuit; IGBT power module connects DSP development board and faulty circuit, and to they power supplies.
FPGA development board major function is to sample (comprising No. 3 inverter outputs, 3 road load currents, 1 road DC voltage, 3 road voltage on line side) for controlling AD, and threephase load current data is calculated and extracted each harmonic, the harmonic data of sampling and calculate is passed to DSP development board by bus form simultaneously.
The following describes the concrete grammar of control panel adjustment method:
Before upper electro-detection, check whether there is solder skip, whether reversal connection of electrochemical capacitor; Check main circuit (isolating switch, buffer resistance and contactor) and circuit board testing power supply as shown in Figure 4: comprise that whether analog power ± 15VA ,+5VA, AGND and digital power+15VD ,+5VD, DGND be correct.With the whether short circuit of multimeter test access auxiliary electrical source, open circuit.
Testing power supply voltage comprises analog power ± 15VA ,+5VA, AGND, after digital power+15VD ,+5VD, DGND are correct, does not insert DSP development board, FPGA development board, after switching on several minutes, disconnects, and checks whether chip has heating situation; If have device heating, the even situation of smoldering power-off immediately, check whether reversal connection of corresponding site, short circuit etc.; Determining does not have after abnormal conditions, continues energising several minutes, observe whether abnormal, simultaneously with multimeter inspection DSP development board, FPGA development board, power supply;
Insert DSP development board, FPGA development board, energising, whether observation pilot lamp is bright: the bright expression of pilot lamp is normal, otherwise undesired, needs to check on development board, whether connector connects closely, checks whether development board power interface has voltage; Whether interface (3.3V/5V) is normally connected, and if any power-off extremely immediately, checks corresponding site;
Open CCS software, by DSP emulator, be connected with DSP development board, at CCS software " View/Graph/Time or frequency ", the zero situation of wafing of observation;
Load current sampling in test, DC side sampling, the sampling of inverter output current are presented at the high frequency burr that amplitude is less (generally in 1 left and right), show that this channel sample is errorless.As zero, waft larger, when dsp program, should subdue zero and waft numerical value to improve the precision of sampling;
If any a certain passage, do not meet foregoing description,
1. as occurred, zero large this of sailing shows that in branch road, certain pin of amplifier chip may penetrate DC current, the load current of take sampling branch road describes as example, investigation step is: from mutual inductor end start to detect successively current sampling resistor end, amplifier input, output terminal voltage whether there is voltage, if there is voltage, illustrate and penetrate electric current or voltage, now need to do further inspection, observe this place and whether be directly connected with power supply, or there is the situation of picture mistake in pcb board.
2. as without any waveform possible cause be that this passage somewhere disconnects, first deenergization, checks circuit diagram, use multimeter, gets rid of one by one from corresponding mutual inductor end to AD incoming end; The load current of take equally sampling branch road describes as example, the sampling of Ru Gai road goes wrong, investigation step is: from mutual inductor end start to detect successively the input of obtaining current sampling resistor end, amplifier, that whether output terminal all connects is correct, whether there is the situation of somewhere broken string, if broken string, need to be from corresponding position fly line;
When zero of the sampling of above-mentioned observation load current, DC side sampling and the sampling of inverter output current waftd, due to the difference of device own and welding difference waveform not necessarily the same, during detection waveform zero waft that amplitude is less can (in 1 left and right);
After more than test is passed through, and then testing power supply enters voltage on line side and load-side sampling, whether its amplitude is wrong, voltage on line side is that A phase zero crossing is caught, all the other two-phases realize by A phase retardation, and whether amplitude is corrected and need be coincide with initial designs according to the input current amplitude checking respective branch enlargement factor of testing power supply; According to on-the-spot constant calculations, go out actual gain, then whether the signal of contrast standard test source output is consistent with the voltage magnitude of CCS watch window output, if inconsistent, need to find a suitable coefficient by repeatedly measuring, if consistent, do not need to change;
During test inverter sampling channel, while accessing due to standard testing source, with a small amount of DC component influence, test, therefore after adopting mutual inductor isolation, test, can meet the simulation of ascending spot sampling parameter value simultaneously, adopt the mutual inductor of the 5A/100mA of specific customization herein; Secondary side is that test signal is connected with inverter sample circuit, and its simplified diagram as shown in Figure 3.Next by CCS, observe graphical window, whether observe current amplitude coincide, wherein no-load voltage ratio calculates gain by 5A/100mA mutual inductor and inverter sample circuit, then whether the signal of contrast standard source output is consistent with the voltage magnitude of CCS watch window output, if inconsistent, need by repeatedly measuring and find a suitable coefficient, if unanimously, do not need to change.
During Test Network side voltage sample passage, because net side phase voltage in scene is 220v, for can simulated field parameter, test source output 50v connects Access Control plate after the voltage transformer (VT) of customization 50V/220V herein, its simplified diagram as shown in Figure 3, finally utilize the amplitude of CCS software observed samples whether correct, as incorrect, need detect successively respective channel, step and upper similar.
During test load current sample passage, due to spot sampling parameter 5mA, for can simulated field parameter, the current transformer of the 5A/5mA connecing after the 5A of standard testing source output is herein Access Control plate again, its simplified diagram as shown in Figure 3, finally utilize the amplitude of CCS software observed samples whether correct, as incorrect, need detect successively respective channel, step and upper similar.
Claims (1)
1. a three-phase four-wire system APF control panel adjustment method, it is characterized in that, described method relies on standard testing source, its maximum effective value in voltage providing three roads is that voltage source, the maximum effective value of three road electric currents of 57 volts is 5 peaces, maximum overtone order is the current source of 50 times, and load current sampling channel, inverter current sampling channel and voltage on line side sampling channel are tested;
During test load current sample passage, primary circuit is by standard source output current signal, by the current transformer Access Control plate of a 5A/5mA;
During test inverter current sampling channel, primary circuit is by standard source output current signal, the current transformer Access Control plate of the 5A/200mA by a specific customization;
During Test Network side voltage sample passage, primary circuit is by standard source output voltage signal, by the 50V/220V voltage transformer (VT) Access Control plate of a specific customization.
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| CN201410137344.7A CN103926915A (en) | 2014-04-08 | 2014-04-08 | Three-phase four-wire system APF control-panel debugging method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107505933A (en) * | 2017-09-05 | 2017-12-22 | 上海地铁电子科技有限公司 | Subordinate inverter controller test system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5737198A (en) * | 1996-11-26 | 1998-04-07 | General Electric Company | Hybrid active power filter with programmed impedance characteristics |
| JP2003102127A (en) * | 2001-09-26 | 2003-04-04 | Shindengen Electric Mfg Co Ltd | Method for controlling active filter apparatus |
| CN101262131A (en) * | 2007-03-08 | 2008-09-10 | 北京博旺天成科技发展有限公司 | A mixed active power filter with online adjustable controller parameter |
| CN102801174A (en) * | 2012-08-31 | 2012-11-28 | 长沙威胜能源产业技术有限公司 | Main control module for low-voltage dynamic reactive harmonic comprehensive compensation device |
| CN103558840A (en) * | 2013-11-05 | 2014-02-05 | 国家电网公司 | Method for establishing entity controller simulation experiment standard interface and circuit of RTDS |
-
2014
- 2014-04-08 CN CN201410137344.7A patent/CN103926915A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5737198A (en) * | 1996-11-26 | 1998-04-07 | General Electric Company | Hybrid active power filter with programmed impedance characteristics |
| JP2003102127A (en) * | 2001-09-26 | 2003-04-04 | Shindengen Electric Mfg Co Ltd | Method for controlling active filter apparatus |
| CN101262131A (en) * | 2007-03-08 | 2008-09-10 | 北京博旺天成科技发展有限公司 | A mixed active power filter with online adjustable controller parameter |
| CN102801174A (en) * | 2012-08-31 | 2012-11-28 | 长沙威胜能源产业技术有限公司 | Main control module for low-voltage dynamic reactive harmonic comprehensive compensation device |
| CN103558840A (en) * | 2013-11-05 | 2014-02-05 | 国家电网公司 | Method for establishing entity controller simulation experiment standard interface and circuit of RTDS |
Non-Patent Citations (2)
| Title |
|---|
| 刘威葳: "三相四线制并联型有源滤波器物理模拟装置的研制", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 卢浩等: "基于能量守恒PI控制方法的有源电力滤波器研究", 《电力系统保护与控制》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107505933A (en) * | 2017-09-05 | 2017-12-22 | 上海地铁电子科技有限公司 | Subordinate inverter controller test system |
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Application publication date: 20140716 |