CN103928384A - Forming method of semiconductor structure, and semiconductor structure - Google Patents
Forming method of semiconductor structure, and semiconductor structure Download PDFInfo
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- CN103928384A CN103928384A CN201310009789.2A CN201310009789A CN103928384A CN 103928384 A CN103928384 A CN 103928384A CN 201310009789 A CN201310009789 A CN 201310009789A CN 103928384 A CN103928384 A CN 103928384A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Abstract
The invention provides a forming method of a semiconductor structure, and a semiconductor structure. The forming method of the semiconductor structure comprises: forming a groove in a substrate, the groove dividing the substrate into a first active area and a second active area; forming a first well region in the first active area, forming a second well region in the second active area, and forming a depletion region at the connection position of the first well region and the second well region; performing first ion implantation in the first well region at the bottom of the groove, and performing second ion implantation in the second well region at the bottom of the groove, the type of the first ion implantation being the same as the type of the first well region, the type of the second ion implantation being the same as the type of the second well region; and after the ion implantation, filling a dielectric layer in the groove to form an isolation structure. According to the invention, the method reduces the dimension of the isolation structure and accordingly reduces the occupation area of the isolation structure on a chip; a electrostatic protection circuit can also be quite easily triggered so as to protect a semiconductor device from being damaged; and the latch effect generation probability can also be reduced.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of formation method and semiconductor structure of semiconductor structure.
Background technology
Along with the development of semiconductor technology, the size of the semiconductor device on chip is constantly being dwindled.The isolation structure of accordingly, semiconductor device being isolated need to constantly dwindle.The patent No. is that the american documentation literature of US6171910B1 discloses a kind of method of dwindling dimensions of semiconductor devices.
Referring to figs. 1 to Fig. 3, the manufacture method of the fleet plough groove isolation structure between existing semiconductor structure is as follows:
With reference to figure 1, Semiconductor substrate 100 is provided, in described Semiconductor substrate, form groove 102.
With reference to figure 2, in described groove 102, form dielectric layers with substrate 100 surfaces, remove the dielectric layer higher than groove 102 surfaces, form fleet plough groove isolation structure (STI) 104.Form after fleet plough groove isolation structure 104, in the substrate of the both sides of described fleet plough groove isolation structure 104, carry out respectively Implantation, form N well region 105 and P well region 106.
With reference to figure 3, form after N well region 105 and P well region 106, at N well region 105, form PMOS transistor 107, wherein, in PMOS transistor, be formed with source electrode 108 and the drain electrode 109 of P type.At P well region 106, form nmos pass transistor 110, wherein, in nmos pass transistor, be formed with source electrode 111 and the drain electrode 112 of N-type.
Fleet plough groove isolation structure of the prior art cannot continue to dwindle, and the area that takies chip is larger.
Summary of the invention
The problem that the present invention solves is that fleet plough groove isolation structure of the prior art cannot continue to dwindle, and the area that takies chip is larger.
For addressing the above problem, the invention provides a kind of formation method of semiconductor structure, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms groove, described groove is divided into the first active area and the second active area by Semiconductor substrate;
In described the first active area, form the first well region, in described the second active area, form the second well region, the formation depletion region, junction of described the first well region and the second well region;
In the first well region of described bottom portion of groove, carry out the first Implantation, in the second well region of described bottom portion of groove, carry out the second Implantation, the type of the first Implantation is identical with the type of the first well region, and the type of the second Implantation is identical with the type of the second well region;
After Implantation, in described groove, filled media layer forms isolation structure.
Optionally, describedly in the first well region of described bottom portion of groove, carry out the first Implantation and comprise:
On the surface of described substrate and groove formation, form patterned the first mask layer, the region of definition the first Implantation;
Described patterned the first mask layer of take is mask, carries out the first Implantation;
After the first Implantation, remove patterned the first mask layer.
Optionally, describedly in the second well region of described bottom portion of groove, carry out the second Implantation and comprise:
On the surface of described substrate and groove formation, form patterned the second mask layer, the region of definition the second Implantation;
Described patterned the second mask layer of take is mask, carries out the second Implantation;
After the second Implantation, remove patterned the second mask layer.
Ion implantation concentration when optionally, the concentration of described the first Implantation is less than described isolation structure and punctures.
Optionally, the concentration of described the first Implantation is less than 1 * 10
14atom/cm
2.
Ion implantation concentration when optionally, the concentration of described the second Implantation is less than described isolation structure and punctures.
Optionally, the concentration of described the second Implantation is less than 1 * 10
14atom/cm
2.
Optionally, also comprise step form the step of groove in described Semiconductor substrate before: on described substrate, form oxygen pad layer, on described oxygen pad layer, form barrier layer.
Optionally, the material of described oxygen pad layer is silica, and the material on described barrier layer is silicon nitride.
Optionally, in described the first active area, form the first well region, form the second well region step in described the second active area before, also comprise step: in described groove surfaces, form silicon oxide layer.
Optionally, the formation method of described silicon oxide layer is thermal oxidation.
Optionally, the material of described dielectric layer is silica.
Optionally, the described method that forms groove in described Semiconductor substrate comprises:
In described Semiconductor substrate, form patterned the 3rd mask layer, the position of definition groove;
Described patterned the 3rd mask layer of take carries out etching to Semiconductor substrate as mask.
The present invention also provides a kind of semiconductor structure, comprising:
The reeded Semiconductor substrate of tool, a side Semiconductor substrate of described groove is the first active area, the opposite side Semiconductor substrate of described groove is the second active area;
Be positioned at the first well region of the first active area, be positioned at the second well region of the second active area, described the first well region and described the second well region are in formation depletion region, the junction of described bottom portion of groove;
The ion concentration of the first well region of described bottom portion of groove is greater than the concentration of first other position of well region, and the ion concentration of the second well region of described bottom portion of groove is greater than the concentration of second other position of well region;
Fill the dielectric layer of described groove.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the first well region of described bottom portion of groove, carry out the first Implantation, in the second well region of described bottom portion of groove, carry out the second Implantation, the type of the first Implantation is identical with the type of the first well region, the type of the second Implantation is identical with the type of the second well region, so that the ion concentration of bottom portion of groove the first well region and the second well region all increases to some extent, thereby the width of the depletion region that the first well region and the second well region form at bottom portion of groove is reduced.After Implantation, in described groove, filled media layer forms isolation structure.Then, in the both sides of described isolation structure, form drain electrode and source electrode, wherein, drain as the transistorized drain electrode adjacent with this isolation structure forming in the first well region, described source electrode is transistorized source electrode adjacent with this isolation structure in the second well region.When dwindling the size of this isolation structure, drain electrode and the distance between source electrode of these isolation structure both sides also can correspondingly be dwindled, but, in the situation that dwindling this isolation structure size, even source electrode or drain electrode are applied to voltage, can there is not the break-through (Punchthrough) between source electrode, drain electrode and well region of the same type, yet, the drain electrode of the first well region not can and the second well region between there is break-through, the source electrode of the second well region not can and the first well region between there is break-through.Therefore, when described bottom portion of groove is carried out to above-mentioned Implantation, can dwindle the size of this isolation structure, and then reduce the area occupied of this isolation structure on chip.
Further; at described bottom portion of groove, carry out above-mentioned Implantation; so that the concentration of the first well region and the second well region all increases to some extent; can reduce the trigger voltage (TriggerVoltage) of electrostatic storage deflection (ESD) protection circuit; when having static discharge phenomenon to occur; the present invention can more easily trigger electrostatic discharge protection circuit, to protect semiconductor device be not damaged or damage.
Further, at described bottom portion of groove, carry out above-mentioned Implantation, reduced respectively the dead resistance of the first well region and the second well region, therefore, if producing latch-up, the semiconductor device of follow-up formation needs larger parasite current (Holding Current), therefore, the difficulty of the semiconductor device generation latch-up of follow-up formation is increased, thereby reduce the probability that latch-up produces.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the cross-sectional view of the manufacture method of the fleet plough groove isolation structure between the semiconductor structure of prior art;
Fig. 4 is the schematic flow sheet of formation method of the semiconductor structure of the embodiment of the present invention;
Fig. 5 to Figure 10 is the cross-sectional view of forming process of the semiconductor structure of the embodiment of the present invention.
Embodiment
Inventor finds and analyzes, and fleet plough groove isolation structure of the prior art cannot continue to dwindle, take larger former of the area of chip because:
With reference to figure 3, in prior art, the hole of P well region 106 can be diffused into N well region 105, and the electrons of N well region 105 is diffused into P well region 106, therefore the electrons that, is diffused into the hole of N well region 105 and is diffused into P well region 106 is compounded to form depletion region in fleet plough groove isolation structure 104 bottoms.Need to be to PMOS transistor when device is worked, source electrode and the drain electrode of nmos pass transistor apply voltage, the width of depletion region can increase executing under alive effect, if now dwindle the size of fleet plough groove isolation structure 104, be equivalent to dwindle the drain electrode 112 of nmos pass transistor and the distance between PMOS transistor source 108, the depletion region that width increases is easy to enter drain electrode 112 and the PMOS transistor source 108 of nmos pass transistor, cause source electrode 108, break-through (Punchthrough) between drain electrode 112 and the well region of doping of the same type, semiconductor device cannot be worked.Be specially, the electronics in the depletion region that width increases enters into the drain electrode 112 of nmos pass transistor, makes, between the drain electrode 112 of nmos pass transistor and N well region 105, break-through occurs.Hole in the depletion region that width increases enters into the source electrode 108 of PMOS transistor, makes, between the transistorized source electrode 108 of PMOS and P well region 106, break-through occurs.Therefore, the size of fleet plough groove isolation structure cannot continue to dwindle, and the area taking in chip is larger.
For this reason, inventor, through research, has proposed a kind of formation method of semiconductor structure, and Fig. 4 is the schematic flow sheet of formation method of the semiconductor structure of the embodiment of the present invention.Fig. 5 to Fig. 8 is the cross-sectional view of forming process of the semiconductor structure of the embodiment of the present invention.Below Fig. 5 to Fig. 8 and Fig. 4 are combined the formation method of semiconductor structure of the present invention is elaborated.
First with reference to figure 5, the step S11 in execution graph 4, provides Semiconductor substrate 200, forms groove 201 in described Semiconductor substrate, and described groove 201 is divided into the first active area I and the second active area ∏ by Semiconductor substrate.
Substrate 200 materials can be silicon substrate, germanium silicon substrate, III-V group element compound substrate, silicon carbide substrates or its laminated construction, or silicon on insulated substrate, or diamond substrate, or well known to a person skilled in the art other semiconductive material substrate.
In the present embodiment, on semiconductor 200, be also formed with oxygen pad layer 202, on oxygen pad layer 202, form barrier layer 203.Acting as of barrier layer 203 protected semiconductor substrate surface.The material on described barrier layer 203 is silicon nitride, and formation method is chemical vapour deposition (CVD).The effect of oxygen pad layer 202 is in order to prevent between barrier layer 203 and Semiconductor substrate 200 due to the different stress ruptures that produce of thermal coefficient of expansion.The material of oxygen pad layer 202 is silica, and formation method is chemical vapour deposition (CVD).
Form behind barrier layer 203, on the surface on described barrier layer 203, form the mask layer (not shown) of patterning, the mask layer of described patterning of take is mask, successively barrier layer 203, oxygen pad layer 202 and substrate 200 is carried out to etching, at the interior formation groove 201 of substrate 200.Described groove 201 is divided into the first active area I and the second active area ∏ by Semiconductor substrate.
Form after groove 201, on described groove 201 surfaces, form silicon oxide layer 213, the formation method of described silicon oxide layer 213 is thermal oxidation.Groove 201 surfaces form acting as of silicon oxide layer 213: first, through etching technics, form in the process of groove 201, the silicon on groove 201 surfaces has damage, by thermal oxidation technology, surface can there be is the silicon of damage become silica, so that the isolation effect of the fleet plough groove isolation structure of follow-up formation is better.Moreover, the angle of the bottom portion of groove edge forming through etching technics is more sharp-pointed, easily accumulation is arrived most advanced and sophisticated, electric discharge tapers off to a point, thereby at follow-up fleet plough groove isolation structure place, produce puncture voltage, therefore, on the surface of described groove, form silicon oxide layer, can, so that the edge of bottom portion of groove becomes round and smooth, reduce the generation of point discharge phenomenon.
Certainly, in other embodiments, can on the surface of groove 201, not form silicon oxide layer 213 yet.
Then,, with reference to figure 6, the step S12 in execution graph 4 forms the first well region 204 in described the first active area I, in described the second active area ∏, forms the second well region 205, the formation depletion region, junction of described the first well region 204 and the second well region 205.
When the transistor in the first active area I is nmos pass transistor, at the first active area I doping trivalent dopant, form P well region, wherein, trivalent dopant is boron ion; When the transistor in the first active area I is PMOS transistor, at the first active area I doping pentavalent dopant, form N well region, wherein, pentavalent dopant is phosphonium ion, arsenic ion or antimony ion.In the first active area I, form the method for the first well region 204 for those skilled in the art know technology, do not repeat them here.Transistor in the first active area I is nmos pass transistor, when the first active area I doping trivalent dopant forms P well region, at the second active area ∏ doping pentavalent dopant, forms N well region; Transistor in the first active area I is PMOS transistor, when the first active area I doping pentavalent dopant forms N well region, at the second active area ∏ doping trivalent dopant, forms P well region.In the second active area ∏, form the method for the second well region 205 for those skilled in the art know technology, do not repeat them here.In the present embodiment, the transistor in the first active area I is nmos pass transistor, is to form P well region at the first active area I doping trivalent dopant, at the second active area ∏ doping pentavalent dopant, forms N well region.Form after N well region the formation depletion region, junction of described N well region and the P well region forming at the first active area I.
In other embodiments, also can form N well region at the first active area I doping pentavalent dopant, the trivalent dopant that adulterates in the second active area ∏ forms P well region also can implement the present invention.
Then, with reference to figure 7 and Fig. 8, step S13 in execution graph 4, in the first well region 204 of described groove 201 bottoms, carry out the first Implantation, in the second well region 205 of described groove 201 bottoms, carry out the second Implantation, the type of the first Implantation is identical with the type of the first well region 204, and the type of the second Implantation is identical with the type of the second well region 205.
Be specially: with reference to figure 7, on the surface of described substrate 200 and groove 201 formation, form patterned the first mask layer 207, the region of definition the first Implantation, then, described patterned the first mask layer of take is mask, carries out the first Implantation.The type of the first Implantation is identical with the type of the first well region 204.
Wherein, the first mask layer 207 can be photoresist, silica, silicon oxynitride, tantalum nitride or titanium nitride.The better photoresist of selecting of the present embodiment.
In the present embodiment, the first well region 204 is P well region.P well region to bottom portion of groove carries out the first Implantation, forms P+ region 208, and the ion of injection is phosphonium ion, arsenic ion or antimony ion.The dosage that described phosphonium ion injects is less than 1 * 10
14atom/cm
2, the energy that phosphonium ion injects is less than 1000Kev.The sputtering machine table that the time that radio-frequency voltage when described phosphonium ion injects and phosphonium ion inject is used during according to ion implantation technology is determined, the time that radio-frequency voltage when therefore, phosphonium ion injects and phosphonium ion inject is according to the difference of concrete ion implantation technology and difference.
Form behind P+ region 208, remove the first mask layer 207, the method for removing the first mask layer 207 is ashing.
Then, with reference to figure 8, on the surface of described substrate 200 and groove 201 formation, form patterned the second mask layer 209, the region of definition the second Implantation, then, described patterned the second mask layer 209 of take is mask, carries out the second Implantation.The type of the second Implantation is identical with the type of the second well region 205.
Wherein, the second mask layer 209 can be photoresist, silica, silicon oxynitride, tantalum nitride or titanium nitride.The better photoresist of selecting of the present embodiment.
In the present embodiment, the second well region 205 is N well region.N well region to bottom portion of groove carries out the second Implantation, forms N+ region 210, and the ion of injection is boron ion.The dosage of described boron Implantation is less than 1 * 10
14atom/cm
2, the energy of boron Implantation is less than 1000Kev.The sputtering machine table that the time of radio-frequency voltage during described boron Implantation and boron Implantation is used during according to ion implantation technology is determined, therefore, the time of radio-frequency voltage during boron Implantation and boron Implantation is according to the difference of concrete ion implantation technology and difference.
Form behind N+ region 210, remove the second mask layer 209, the method for removing the second mask layer 209 is ashing.
In the present embodiment, groove 201 bottoms are carried out after the first Implantation and the second Implantation, at P well region, form P+ region 208, at N well region, form N+ region 210.The formation in 208HeN+ region, P+ region 210 has increased the depletion region intermediate ion of groove 201 bottoms and the concentration in hole, makes the narrowed width of depletion region.The width of the groove therefore forming in substrate can correspondingly dwindle, distance between the drain electrode of the follow-up nmos pass transistor forming in P well region and the PMOS transistor source that forms in N well region is corresponding dwindling also, and can there is not the break-through (Punchthrough) between source electrode or drain electrode and the well region of doping of the same type,, can there is not the drain electrode of nmos pass transistor of follow-up formation and the break-through between N well region, the source electrode in the PMOS transistor of follow-up formation and the break-through between P well region.
It should be noted that, in P+ region 208, the implantation dosage of phosphonium ion is less than 1 * 10
14atom/cm
2, wherein 1 * 10
14atom/cm
2for follow-up, at P well region, form drain electrode in nmos pass transistor or the concentration of source electrode.In N+ region 210, the implantation dosage of boron ion is less than 1 * 10
14atom/cm
2, wherein 1 * 10
14atom/cm
2follow-uply at P well region, to form drain electrode in nmos pass transistor or the concentration of source electrode.1 * 10
14atom/cm
2ion implantation concentration while also puncturing for isolation structure.In P+ region, in the implantation dosage of phosphonium ion and N+ region, why the implantation dosage of boron ion is less than 1 * 10
14atom/cm
2.Because if the dosage of Implantation is too large, the isolation structure of follow-up formation is easily breakdown, does not have buffer action, and semiconductor device cannot be worked.
In other embodiments, also can first to the second well region 205 of groove 201 bottoms, carry out Implantation, and then the first well region 204 of groove 201 bottoms is carried out to Implantation.
Then,, with reference to figure 9 and Figure 10, the step S14 in execution graph 4, after Implantation, forms isolation structure 212 at the interior filled media layer 211 of described groove 201.
Wherein, the material of dielectric layer 211 is silica.In the present embodiment, adopt the method for deposition to form silica with the surface on barrier layer 203 in described groove 201 (please refer to Fig. 5), then adopt the method for chemico-mechanical polishing to remove the silicon oxide layer on 203 surfaces, barrier layer, form isolation structure 212, the isolation structure 212 of the present embodiment is that shallow trench isolation is from (STI) structure.Wherein, barrier layer 203 is the stop-layer of chemico-mechanical polishing, and protection substrate is injury-free.
In other embodiments, also can form silica in the interior method of heat growth that adopts of groove 201.The isolation structure 212 forming is local field oxidation isolation (LOCOS) structure.
The technique of the semiconductor device of follow-up formation is known field for those skilled in the art.
It should be noted that, in the present embodiment, below described fleet plough groove isolation structure, form 208HeN+ region, P+ region 210, can also make electrostatic storage deflection (ESD) protection circuit more easily trigger, and then protection semiconductor device is normally worked.
Be specially, static discharge (electrostatic discharge, ESD) refers to the electric current that flow in a large number semiconductor device in short moment.The source of this large electric current has a variety of.For example, human body and machine electric discharge, be called human body discharging model (Human Body Model, HBM) and machine discharging model (machinemodel, MM).Semiconductor device is easily subject to the impact of static discharge and goes to pot or damage.Especially when dimensions of semiconductor devices is decreased to the scope of deep-sub-micrometer, static discharge more easily damages semiconductor device.
In the present embodiment; below fleet plough groove isolation structure, form 208HeN+ region, P+ region 210; so that the concentration of P well region and N well region all increases to some extent; thereby reduce the trigger voltage (Trigger Voltage) of electrostatic storage deflection (ESD) protection circuit; when having static discharge phenomenon to occur; the present invention can more easily trigger electrostatic discharge protection circuit, to protect semiconductor device be not damaged or damage.
Need to go on to say, the present invention has also reduced the occurrence probability of the latch-up (Latch-up) of cmos device.Wherein, the latch-up of cmos device (Latch-up) is two junction transistor (the Bipolarjunction transisitor of pnp parasitic under the PMOS of the pn knot generation in cmos device, BJT) the two junction transistors of npn parasitic and under NMOS are by unconscious unlatching, and produce low-resistance electric current road through CMOS structure.Transistor is locked, thereby has stoped the control to NMOS and PMOS in cmos device.Being specially, for the two junction transistors of pnp, is that the electric current of β 1 is when flow through if there is multiplication factor, for the two junction transistors of npn, if having multiplication factor is the electric current of β 2 while flowing through, when β 1 * β 2 > 1, just there is the latch-up of cmos device.
The formation in the 208HeN+ region, P+ region 210 in the present invention, reduced respectively the dead resistance of P well region and N well region, thereby reduced the dead resistance of the two junction transistors of pnp and the two junction transistors of npn, if make cmos device produce latch-up, need larger parasite current (Holding Current) to flow through cmos device, therefore, the difficulty of cmos device generation latch-up is increased, reduce the probability that latch-up produces.
With reference to Figure 10, the present invention also provides a kind of semiconductor structure, comprising:
The Semiconductor substrate 200 with groove 201, a side Semiconductor substrate of described groove 201 (with reference to figure 5) is the first active area I, the opposite side Semiconductor substrate of described groove is the second active area ∏;
Be positioned at the first well region 204 of the first active area I, be positioned at the second well region 205 of the second active area ∏, described the first well region 204 and described the second well region 205 are in formation depletion region, the junction of described bottom portion of groove;
The ion concentration of the first well region 204 of described groove 201 bottoms is greater than the concentration of first well region 204 other positions, and the ion concentration of the second well region 205 of described groove 201 bottoms is greater than the concentration of second well region 205 other positions;
Fill the dielectric layer 212 of described groove.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (14)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms groove, described groove is divided into the first active area and the second active area by Semiconductor substrate;
In described the first active area, form the first well region, in described the second active area, form the second well region, the formation depletion region, junction of described the first well region and the second well region;
In the first well region of described bottom portion of groove, carry out the first Implantation, in the second well region of described bottom portion of groove, carry out the second Implantation, the type of the first Implantation is identical with the type of the first well region, and the type of the second Implantation is identical with the type of the second well region;
After Implantation, in described groove, filled media layer forms isolation structure.
2. formation method as claimed in claim 1, is characterized in that, describedly in the first well region of described bottom portion of groove, carries out the first Implantation and comprises:
On the surface of described substrate and groove formation, form patterned the first mask layer, the region of definition the first Implantation;
Described patterned the first mask layer of take is mask, carries out the first Implantation;
After the first Implantation, remove patterned the first mask layer.
3. formation method as claimed in claim 1, is characterized in that, describedly in the second well region of described bottom portion of groove, carries out the second Implantation and comprises:
On the surface of described substrate and groove formation, form patterned the second mask layer, the region of definition the second Implantation;
Described patterned the second mask layer of take is mask, carries out the second Implantation;
After the second Implantation, remove patterned the second mask layer.
4. formation method as claimed in claim 2, is characterized in that, the ion implantation concentration when concentration of described the first Implantation is less than described isolation structure and punctures.
5. formation method as claimed in claim 4, is characterized in that, the concentration of described the first Implantation is less than 1 * 10
14atom/cm
2.
6. formation method as claimed in claim 3, is characterized in that, the ion implantation concentration when concentration of described the second Implantation is less than described isolation structure and punctures.
7. formation method as claimed in claim 6, is characterized in that, the concentration of described the second Implantation is less than 1 * 10
14atom/cm
2.
8. formation method as claimed in claim 1, is characterized in that, also comprises step before forming the step of groove: on described substrate, form oxygen pad layer, on described oxygen pad layer, form barrier layer in described Semiconductor substrate.
9. formation method as claimed in claim 8, is characterized in that, the material of described oxygen pad layer is silica, and the material on described barrier layer is silicon nitride.
10. formation method as claimed in claim 1, is characterized in that, in described the first active area, forms the first well region, before forming the second well region step, also comprises step in described the second active area: in described groove surfaces, form silicon oxide layer.
11. formation methods as claimed in claim 10, is characterized in that, the formation method of described silicon oxide layer is thermal oxidation.
12. formation methods as claimed in claim 1, is characterized in that, the material of described dielectric layer is silica.
13. formation methods as claimed in claim 1, is characterized in that, the described method that forms groove in described Semiconductor substrate comprises:
In described Semiconductor substrate, form patterned the 3rd mask layer, the position of definition groove;
Described patterned the 3rd mask layer of take carries out etching to Semiconductor substrate as mask.
14. 1 kinds of semiconductor structures, is characterized in that, comprising:
The reeded Semiconductor substrate of tool, a side Semiconductor substrate of described groove is the first active area, the opposite side Semiconductor substrate of described groove is the second active area;
Be positioned at the first well region of the first active area, be positioned at the second well region of the second active area, described the first well region and described the second well region are in formation depletion region, the junction of described bottom portion of groove;
The ion concentration of the first well region of described bottom portion of groove is greater than the concentration of first other position of well region, and the ion concentration of the second well region of described bottom portion of groove is greater than the concentration of second other position of well region;
Fill the dielectric layer of described groove.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310009789.2A CN103928384A (en) | 2013-01-10 | 2013-01-10 | Forming method of semiconductor structure, and semiconductor structure |
| TW102113284A TW201428928A (en) | 2013-01-10 | 2013-04-15 | Forming method of semiconductor structure and semiconductor structure |
| KR1020130054964A KR101478272B1 (en) | 2013-01-10 | 2013-05-15 | A semiconductor structure and a method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310009789.2A CN103928384A (en) | 2013-01-10 | 2013-01-10 | Forming method of semiconductor structure, and semiconductor structure |
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| Publication Number | Publication Date |
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| CN103928384A true CN103928384A (en) | 2014-07-16 |
Family
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| CN201310009789.2A Pending CN103928384A (en) | 2013-01-10 | 2013-01-10 | Forming method of semiconductor structure, and semiconductor structure |
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|---|---|
| KR (1) | KR101478272B1 (en) |
| CN (1) | CN103928384A (en) |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1282098A (en) * | 1999-07-21 | 2001-01-31 | 摩托罗拉公司 | Method for forming semiconductor device |
| US6228726B1 (en) * | 2000-03-06 | 2001-05-08 | Taiwan Semiconductor Manufacturing Company | Method to suppress CMOS device latchup and improve interwell isolation |
| CN1485895A (en) * | 2002-07-24 | 2004-03-31 | ���ǵ�����ʽ���� | Method for fabricating low well of semiconductor device using low energy ion implantation |
| US20050142728A1 (en) * | 2003-12-30 | 2005-06-30 | Kim Dae K. | Methods of forming wells in semiconductor devices |
| KR20060009422A (en) * | 2004-07-21 | 2006-01-31 | 매그나칩 반도체 유한회사 | Method for manufacturing of semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002043534A (en) * | 2000-07-28 | 2002-02-08 | Nec Corp | Semiconductor device and manufacturing method thereof |
| US7041581B2 (en) * | 2001-11-16 | 2006-05-09 | International Business Machines Corporation | Method and structure for improving latch-up immunity using non-dopant implants |
-
2013
- 2013-01-10 CN CN201310009789.2A patent/CN103928384A/en active Pending
- 2013-04-15 TW TW102113284A patent/TW201428928A/en unknown
- 2013-05-15 KR KR1020130054964A patent/KR101478272B1/en active IP Right Grant
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1282098A (en) * | 1999-07-21 | 2001-01-31 | 摩托罗拉公司 | Method for forming semiconductor device |
| US6228726B1 (en) * | 2000-03-06 | 2001-05-08 | Taiwan Semiconductor Manufacturing Company | Method to suppress CMOS device latchup and improve interwell isolation |
| CN1485895A (en) * | 2002-07-24 | 2004-03-31 | ���ǵ�����ʽ���� | Method for fabricating low well of semiconductor device using low energy ion implantation |
| US20050142728A1 (en) * | 2003-12-30 | 2005-06-30 | Kim Dae K. | Methods of forming wells in semiconductor devices |
| KR20060009422A (en) * | 2004-07-21 | 2006-01-31 | 매그나칩 반도체 유한회사 | Method for manufacturing of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201428928A (en) | 2014-07-16 |
| KR101478272B1 (en) | 2014-12-31 |
| KR20140090923A (en) | 2014-07-18 |
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