CN103928520A - Back gate modulation fully-depleted MOS device and preparation method thereof - Google Patents
Back gate modulation fully-depleted MOS device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims description 58
- 239000000463 material Substances 0.000 claims description 32
- 150000001875 compounds Chemical class 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 7
- 229910002601 GaN Inorganic materials 0.000 claims description 6
- HTCXJNNIWILFQQ-UHFFFAOYSA-M emmi Chemical compound ClC1=C(Cl)C2(Cl)C3C(=O)N([Hg]CC)C(=O)C3C1(Cl)C2(Cl)Cl HTCXJNNIWILFQQ-UHFFFAOYSA-M 0.000 claims description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 6
- 238000006731 degradation reaction Methods 0.000 abstract description 5
- 230000005855 radiation Effects 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 23
- 230000037230 mobility Effects 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 229910017083 AlN Inorganic materials 0.000 description 5
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 5
- 238000005510 radiation hardening Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000003471 anti-radiation Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a back gate modulation fully-depleted MOS device and a preparation method thereof. Through a back gate electrode formed in a heavily-doped region, while dynamic modulation is conducted on the threshold voltage, the MOS device has performance within a wider range, the back gate threshold voltage is further improved through an ultra-thin insulating layer with a high dielectric constant, so that mobility degradation caused by adulteration is avoided, the leak current is reduced, radiation resistance performance is enhanced, and the self-heating effect of the device is reduced due to the excellent thermal conductivity.
Description
Technical field
The present invention relates to semiconductor device and technical field of integrated circuits, be specifically related to a kind of back of the body grid modulation and entirely exhaust MOS device and preparation method thereof.
Background technology
Along with further dwindling of transistor size, when Bulk CMOS technical development is after 22nm and following technology node thereof, its characteristic size has been difficult to continue micro, makes Bulk CMOS cannot obtain performance, cost and the power consumption advantages of scaled down.To further dwindle critical size, mainly contain at present two kinds of approach: the one, the FinFET transistor of employing solid type structure, another is silicon technology (being UTBB FD-SOI transistor technology) on the ultrathin insulating layer adopting based on SOI.Although FinFET transistor has advantages of that power consumption is little, area is little, but this technology exists transistor parasitic resistance capacitance larger, manufacturing process is compared the shortcomings such as the more complicated cost of planar ransistor is higher, so run into great challenge from 22nm FinFET technique transistor to the evolution of 14nm technology node.
Comparatively speaking, UTBB FD-SOI(Fully Depleted SOI, full-exhaustion SOI) technology is more expected to become the strong replacer of Bulk CMOS technology.UTBB FD-SOI transistor has been realized medium isolation completely between device, has avoided the latch-up of Bulk cmos circuit.Ultra-thin silicon layer defines source-and-drain junction deeply and source-and-drain junction depletion region naturally, thereby can improve short-channel effect, the Sub-Threshold Characteristic of device, reduces the quiescent dissipation of circuit etc.Without breech lock, high-speed, low supply voltage, anti-irradiation and the advantage such as high temperature resistant, make UTBB FD-SOI technology have application prospect widely.And UTBB FD-SOI transistor adopts ultra-thin silicon raceway groove and by back of the body grid-control threshold voltage processed, has reduced the dependence to channel doping, makes threshold voltage keep stable, can also avoid the mobil-ity degradation causing because of doping simultaneously.
But, the existence of back of the body grid can make the tagma on BOX layer form a back of the body gate groove, if back of the body gate threshold voltage is too low, can in lower back of the body gate bias situation, occur carrying on the back the unlatching of gate groove, form the OFF leakage current of device, increased device quiescent dissipation, affect the performance of device.In anti-irradiation circuit, irradiation can produce trapped charge in the Si/SiO2 interface in BOX layer and tagma, and these trapped charges can be opened by induction back gate groove in advance, and cause carrying on the back gate threshold voltage and increase, and then the increase that causes carrying on the back gate leak current.So for improving the anti-irradiation of device and reducing the characteristics such as back of the body gate leak current and power consumption, the threshold voltage that improves back of the body grid is most important.
In addition, adopt the technology that strengthens channel region carrier mobility also can obtain higher performance and lower power consumption, consider that III-V group element compound, IV compound material compare traditional silicon materials and aspect carrier mobility, have certain advantage, compound-material with these high carrier mobilities replaces traditional silicon raceway groove can significantly improve the operating rate of device, reduces power consumption.
Chinese patent (publication number: CN103367450A) disclose SOI device of a kind of radiation hardening and preparation method thereof.SOI device of the present invention comprises Semiconductor substrate, oxygen buried layer, tagma, grid region, source region and drain region, grid side wall, LDD district and isolating oxide layer; wherein; between the lower surface in tagma and the upper surface of oxygen buried layer; and be provided with U-shaped protective layer between two sidewalls of tagma on Width and isolating oxide layer, along the Width shape of raceway groove, become U-shaped.The present invention introduces U-shaped protective layer in tagma, even if radiation makes to be absorbed in a large amount of electric charges in thick oxygen buried layer and isolating oxide layer, heavily doped U-shaped protective layer is also difficult to occur transoid.For full-exhaustion SOI device, owing to burying oxygen top, there is heavily doped region, the surface potential of tagma-oxygen buried layer interface, the back side is not easy to be subject to the impact of the positive charge that radiation is absorbed in burying oxygen, therefore introduce heavily doped U-shaped can reduce radiation on full-exhaustion SOI device before the impact of gate threshold voltage.
Chinese patent (publication number: CN101221957A) disclose a kind of dual-grid full-exhaustion SOI CMOS device, this device comprises silicon substrate, oxygen buried layer and is formed on N-shaped slot field-effect transistor, p-type slot field-effect transistor and the device medium isolation in top silicon surface.The present invention discloses a kind of method of preparing dual-grid full-exhaustion SOI cmos device.Utilize the present invention, improved source drain breakdown voltage and channel region carrier mobility, reduced the fluctuation of complex process degree and device performance.
Summary of the invention
The present invention proposes a kind of back of the body grid modulation and entirely exhausts MOS device and preparation method thereof, based on a kind of novel structural material XOi, this XOi(X on insulator) refer to the X material on ultrathin insulating layer i, be III-V compounds of group and the IV compound material with high carrier mobility from this different X material of traditional SOI material, the material of ultrathin insulating layer i is for the insulating material that has higher thermal conductivity and a high-k (high k) than SiO2 is as AlN etc., and adopt epitaxy technique to prepare this XOi material, and then make to using this XOi material to be further improved as the mobility of the raceway groove of device, to improve the speed of device, and the operating voltage of device is further reduced, in addition, the good thermal conductivity of ultrathin insulating layer i, can also reduce the self-heating effect of device, the insulating material XOi of high k characteristic is conducive to improve threshold voltage, strengthens anti-radiation performance etc.Compared to traditional Bulk CMOS, UTBB FD-XOi device can reduce short-channel effect, improves Sub-Threshold Characteristic, improves device mutual conductance and anti-soft failure ability etc.
The present invention has recorded a kind of back of the body grid modulation and has entirely exhausted MOS device, this MOS device comprises that one is provided with the substrate of back gate region and area of grid, and be positioned on the substrate of described area of grid and be provided with grid structure, be positioned on the substrate of described back gate region and be provided with back-gate electrode, one embeds the fleet plough groove isolation structure being arranged in described substrate isolates described area of grid and described back gate region, wherein, described MOS device also comprises: an insulating barrier and an epitaxial loayer;
Described insulating barrier covers the upper surface of the substrate of described area of grid, described epitaxial loayer covers the upper surface of described insulating barrier, described grid structure is positioned at the upper surface of described epitaxial loayer, and the epitaxial loayer that is positioned at described grid structure below forms the raceway groove of MOS device, forms the active area of MOS device in remaining epitaxial loayer;
Wherein, be positioned on the substrate of described back-gate electrode below and be also provided with heavily doped region.
Above-mentioned back of the body grid modulation exhausts MOS device entirely, wherein, described area of grid comprises NMOS area of grid and PMOS area of grid, described back gate region comprises NMOS back gate region and PMOS back gate region, and the common formation of described NMOS area of grid and described NMOS back gate region one nmos device region, the common formation of described PMOS area of grid and described PMOS back gate region one PMOS device area.
Above-mentioned back of the body grid modulation exhausts MOS device entirely, and wherein, described MOS device is CW structure or FW structure;
When described MOS device is CW structure, the substrate that is arranged in described nmos device region is provided with P well region, and the substrate that is arranged in described PMOS device area is provided with N well region;
When described MOS device is FW structure, the substrate that is arranged in described nmos device region is provided with N well region, and the substrate that is arranged in described PMOS device area is provided with P well region.
The modulation of above-mentioned back of the body grid exhausts MOS device entirely, and wherein, to be arranged in the well region doping type that substrate arranges identical with it for the doping type of described heavily doped region.
Above-mentioned back of the body grid modulation exhausts MOS device entirely, wherein, the material that described insulating barrier is high-k, its thickness is 50 Ethylmercurichlorendimide～200 Ethylmercurichlorendimides.
Above-mentioned back of the body grid modulation exhausts MOS device entirely, and wherein, the material of described epitaxial loayer is III-V compounds of group or the IV compounds of group with high carrier mobility.
The present invention has also recorded a kind of preparation method that grid modulation exhausts MOS device entirely that carries on the back, and wherein, described method comprises:
One substrate with area of grid and back gate region is provided;
Adopt epitaxial growth technology after upper surface epitaxial growth one insulation film of described substrate, utilizing epitaxial growth technology is to have the III-V compounds of group of high carrier mobility or the epitaxial loayer of IV compounds of group in upper surface epitaxial growth one material of this insulation film;
Continue at described area of grid and prepare grid structure, in described back gate region, prepare back-gate electrode.
Above-mentioned back of the body grid modulation exhausts MOS device preparation method entirely, wherein, on the substrate of described back-gate electrode below, is prepared with heavily doped region.
Above-mentioned back of the body grid modulation exhausts MOS device preparation method entirely, wherein, described area of grid comprises NMOS area of grid and PMOS area of grid, described back gate region comprises NMOS back gate region and PMOS back gate region, and the common formation of described NMOS area of grid and described NMOS back gate region one nmos device region, the common formation of described PMOS area of grid and described PMOS back gate region one PMOS device area.
Above-mentioned back of the body grid modulation exhausts MOS device preparation method entirely, and wherein, described MOS device is CW structure or FW structure;
When described MOS device is CW structure, the substrate that is arranged in described nmos device region is provided with P well region, and the substrate that is arranged in described PMOS device area is provided with N well region;
When described MOS device is FW structure, the substrate that is arranged in described nmos device region is provided with N well region, and the substrate that is arranged in described PMOS device area is provided with P well region.
The modulation of above-mentioned back of the body grid exhausts MOS device preparation method entirely, and wherein, to be arranged in the well region doping type that substrate arranges identical with it for the doping type of described heavily doped region.
Above-mentioned back of the body grid modulation exhausts MOS device preparation method entirely, wherein, the material that described insulation film is high-k, its thickness is 50 Ethylmercurichlorendimide～200 Ethylmercurichlorendimides.
Above-mentioned back of the body grid modulation exhausts MOS device preparation method entirely, and wherein, the material of described epitaxial loayer is mono-crystal gallium nitride.
The present invention has following technical advantage:
1, the present invention passes through the ultra-thin ultra-thin channel layer of insulating barrier and top, and the modulation of application back of the body grid, can, to back of the body gate threshold voltage dynamic modulation, have the more performance of wide region.
2, ultrathin insulating layer and semiconductor monocrystal structure can be born the epitaxial growth that high temperature carries out fabricating low-defect-density, and are a procedure, and lower cost can approach even lower than traditional extension cost.
3, MOS device architecture of the present invention is simple, short channel effect is little, mobility is high, leakage current is little, without advantages such as latch-ups, at aspects such as high frequency, high temperature resistant, high pressure, low-power consumption and anti-irradiation, have great advantage.
Accompanying drawing explanation
The accompanying drawing that forms a part of the present invention is used to provide a further understanding of the present invention, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the side sectional view of epitaxial growth technology of the present invention;
Fig. 2 is that the present invention carries on the back the side sectional view that grid are modulated full depletion mos transistor CW structure.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail.Implement process of the present invention, condition, experimental technique etc., except the content of mentioning specially below, be universal knowledege and the common practise of this area, the present invention is not particularly limited content.
Embodiment mono-
Fig. 1 is the side sectional view of epitaxial growth technology of the present invention, as shown in Figure 1, the present embodiment discloses back of the body grid and has modulated the preparation method who entirely exhausts MOS device, one substrate 1 with area of grid and back gate region is provided, by epitaxial growth technology, in the material of this substrate 1 of substrate 1(, be first initial monocrystalline or polysilicon) upper surface epitaxial growth one deck material be high-k the insulation film 2 with high heat conductance, this insulation film 2 is ultrathin insulating layer preferably, the material of this insulation film 2 is aluminium nitride in the present embodiment, and its thickness is that 50 Ethylmercurichlorendimide～200 Ethylmercurichlorendimides are (as 50 Ethylmercurichlorendimides, 100 Ethylmercurichlorendimides, 150 Ethylmercurichlorendimides or 200 Ethylmercurichlorendimides etc.), due to the silica membrane than traditional, the insulation film 2 that in the present embodiment, material is aluminium nitride has higher thermal conductivity and dielectric constant, can effectively improve back of the body gate threshold voltage, and then can avoid the mobil-ity degradation that causes because of doping, can also further reduce leakage current, radiation hardening energy, then, continuation by epitaxial growth technology at insulation film 2 epitaxial growth one epitaxial loayers 3, the material of epitaxial loayer 3 adopts III-V compounds of group and the IV compounds of group with high carrier mobility, such as GaN, SiC etc., the present embodiment adopts monocrystalline GaN, consider that III-V compounds of group, IV compounds of group compare traditional silicon materials and aspect carrier mobility, have certain advantage, compound-material with these high carrier mobilities replaces traditional silicon raceway groove can significantly improve the operating rate of device, reduces power consumption.
Fig. 2 is that the present invention carries on the back the side sectional view that grid are modulated full depletion mos transistor CW structure; As shown in Figure 2, after above-mentioned epitaxy technique, in the epitaxial loayer of continuation in area of grid (31 and 32), prepare raceway groove 15 and active area (source region 6 and drain region 7), this raceway groove top forms grid structure (gate dielectric layer 16 and front gate electrode 5), and this external back gate region is prepared back-gate electrode (Gndsn ground connection back-gate electrode 8 and Vddsp power supply back-gate electrode 19).
Described area of grid can be divided into NMOS area of grid 31 and PMOS area of grid 32, between NMOS area of grid 31 and PMOS area of grid 32, be provided with fleet plough groove isolation structure 20, back gate region can be divided into NMOS back gate region 41 and PMOS back gate region 42, and NMOS area of grid 31 and NMOS back gate region 41 common formation one nmos device regions 51, PMOS area of grid 32 and PMOS back gate region 42 common formation one PMOS device areas 52.
The MOS device of the present embodiment is divided into CW(conventional well) structure or FW(flip well) structure, when MOS device is CW structure, the substrate 13 that is arranged in nmos device region 51 is provided with P well region, and the substrate 13 that is arranged in PMOS device area 52 is provided with N well region; When MOS device is FW structure, the substrate 13 that is arranged in nmos device region 51 is provided with N well region, the substrate 13 that is arranged in PMOS device area 52 is provided with P well region, and the doping type of heavily doped region is with it, to be arranged in the well region doping type that substrate arranges identical, this enforcement adopts CW structure, 51Zhong heavily doped region, nmos device region 12 is the heavy doping of P type, and the heavily doped region 18 in PMOS device area 52 is N-type heavy doping, and FW structure will not be narrated at this.
Embodiment bis-
Fig. 2 is that the present invention carries on the back the sectional view that grid are modulated full depletion mos transistor CW structure; As shown in Figure 2, the invention discloses the structure that the modulation of back of the body grid exhausts MOS device CW entirely, this MOS device comprises an area of grid (31 and 32) and back gate region (41 and 42), and be arranged on the substrate 13 of area of grid and be provided with grid structure (figure does not mark), grid structure comprises gate dielectric layer 16 and front gate electrode 5; Be positioned on the substrate 13 of back gate region and be provided with back-gate electrode, back-gate electrode comprises ground connection back-gate electrode 8(Gndsn) and power supply back-gate electrode 19(Vddsp), and an embedding is arranged on fleet plough groove isolation structure 17 isolated gate region and the back gate region in substrate.
Particularly, MOS device also comprises an insulating barrier 14 and epitaxial loayer (not shown), utilize epitaxial growth technology in the upper surface epitaxial growth one deck material of substrate that is positioned at area of grid for high dielectric constant material and there is the insulating barrier 14 of high heat conductance, and this insulating barrier 14 is ultrathin insulating layer preferably, the material of this insulating barrier 14 is aluminium nitride in the present embodiment, thickness is that 50 Ethylmercurichlorendimide～200 Ethylmercurichlorendimides are (as 50 Ethylmercurichlorendimides, 80 Ethylmercurichlorendimides, 120 Ethylmercurichlorendimides, 180 Ethylmercurichlorendimides or 200 Ethylmercurichlorendimides etc.), due to the silica membrane than traditional, material is that the insulating barrier 14 of aluminium nitride has higher thermal conductivity and dielectric constant, and then improved back of the body gate threshold voltage, thereby avoid the mobil-ity degradation causing because of doping, reduced leakage current, radiation hardening energy, epitaxial loayer covers the upper surface of insulating barrier 14, and above-mentioned epitaxial loayer adopts III-V compounds of group and the IV compounds of group with high carrier mobility, such as GaN, SiC etc., the preferred monocrystalline GaN of the present embodiment material, consider that III-V compounds of group, IV compounds of group compare traditional silicon materials and aspect carrier mobility, have certain advantage, compound-material with these high carrier mobilities replaces traditional silicon raceway groove can significantly improve the operating rate of device, reduces power consumption.
Grid structure (gate dielectric layer 16 and front gate electrode 5) is positioned at the upper surface of above-mentioned epitaxial loayer, and the epitaxial loayer that is positioned at grid structure below forms the raceway groove 15 of MOS device, upper surface at raceway groove 15 is provided with gate dielectric layer 16 and front gate electrode 5 formation grid structures successively, the epitaxial loayer of remainder forms the active area (6 drain regions 7, source region) of MOS device, and the substrate that is arranged in back-gate electrode below is also provided with heavily doped region (12 and 18).
Area of grid can be divided into NMOS area of grid 31 and PMOS area of grid 32, between NMOS area of grid 31 and PMOS area of grid 32, be provided with fleet plough groove isolation structure 20, back gate region can be divided into NMOS back gate region 41 and PMOS back gate region 42, and NMOS area of grid 31 and NMOS back gate region 41 common formation one nmos device regions 51, PMOS area of grid 32 and PMOS back gate region 42 common formation one PMOS device areas 52, MOS device of the present invention is divided into CW(conventional well) structure or FW(flip well) structure, when MOS device is CW structure, the substrate 13 that is arranged in nmos device region is provided with P well region, the substrate 13 that is arranged in PMOS device area is provided with N well region, when MOS device is FW structure, the substrate 13 that is arranged in nmos device region is provided with N well region, the substrate 13 that is arranged in PMOS device area is provided with P well region, and the doping type of heavily doped region is with it, to be arranged in the well region doping type that substrate arranges identical, this enforcement adopts CW structure, heavily doped region 12 in nmos device region is the heavy doping of P type, and the heavily doped region 18 in PMOS device area is N-type heavy doping, and FW structure will not be narrated at this.
The back-gate electrode that the present invention forms by heavily doped region, to threshold voltage, can carry out dynamic modulation, there is the more performance of wide region, and the ultra-thin insulating barrier by high-k has further improved back of the body gate threshold voltage, thereby avoid the mobil-ity degradation causing because of doping, reduced leakage current, radiation hardening energy.
In addition, MOS device of the present invention can reduce short-channel effect, improves Sub-Threshold Characteristic, improve device mutual conductance and anti-soft failure ability etc., compare with prior art FinFET device, the complexity of device preparation technology of the present invention, lower than FinFET, therefore has obvious cost advantage and practicality.
These are only preferred embodiment of the present invention; not thereby limit embodiments of the present invention and protection range; to those skilled in the art; should recognize that being equal to that all utilizations specification of the present invention and diagramatic content make replace and the resulting scheme of apparent variation, all should be included in protection scope of the present invention.
Claims (13)
1. back of the body grid modulation exhausts MOS device entirely, this MOS device comprises that one is provided with the substrate of back gate region and area of grid, and be positioned on the substrate of described area of grid and be provided with grid structure, be positioned on the substrate of described back gate region and be provided with back-gate electrode, one embeds the fleet plough groove isolation structure being arranged in described substrate isolates described area of grid and described back gate region, it is characterized in that, described MOS device also comprises: an insulating barrier and an epitaxial loayer;
Described insulating barrier covers the upper surface of the substrate of described area of grid, described epitaxial loayer covers the upper surface of described insulating barrier, described grid structure is positioned at the upper surface of described epitaxial loayer, and the epitaxial loayer that is positioned at described grid structure below forms the raceway groove of MOS device, forms the active area of MOS device in remaining epitaxial loayer;
Wherein, be positioned on the substrate of described back-gate electrode below and be also provided with heavily doped region.
2. carry on the back as claimed in claim 1 grid modulation and entirely exhaust MOS device, it is characterized in that, described area of grid comprises NMOS area of grid and PMOS area of grid, described back gate region comprises NMOS back gate region and PMOS back gate region, and the common formation of described NMOS area of grid and described NMOS back gate region one nmos device region, the common formation of described PMOS area of grid and described PMOS back gate region one PMOS device area.
3. carry on the back as claimed in claim 2 grid modulation and entirely exhaust MOS device, it is characterized in that, described MOS device is CW structure or FW structure;
When described MOS device is CW structure, the substrate that is arranged in described nmos device region is provided with P well region, and the substrate that is arranged in described PMOS device area is provided with N well region;
When described MOS device is FW structure, the substrate that is arranged in described nmos device region is provided with N well region, and the substrate that is arranged in described PMOS device area is provided with P well region.
4. carry on the back as claimed in claim 3 grid modulation and entirely exhaust MOS device, it is characterized in that, to be arranged in the well region doping type that substrate arranges identical with it for the doping type of described heavily doped region.
5. carry on the back as claimed in claim 1 grid modulation and entirely exhaust MOS device, it is characterized in that, the material that described insulating barrier is high-k, its thickness is 50 Ethylmercurichlorendimide～200 Ethylmercurichlorendimides.
6. carry on the back as claimed in claim 1 grid modulation and entirely exhaust MOS device, it is characterized in that, the material of described epitaxial loayer is III-V compounds of group or the IV compounds of group with high carrier mobility.
7. carry on the back the preparation method that grid modulation exhausts MOS device entirely, it is characterized in that, described method comprises:
One substrate with area of grid and back gate region is provided;
Adopt epitaxial growth technology after upper surface epitaxial growth one insulation film of described substrate, utilizing epitaxial growth technology is to have the III-V compounds of group of high carrier mobility or the epitaxial loayer of IV compounds of group in upper surface epitaxial growth one material of this insulation film;
Continue at described area of grid and prepare grid structure, in described back gate region, prepare back-gate electrode.
8. carry on the back as claimed in claim 7 grid modulation and entirely exhaust MOS device preparation method, it is characterized in that, on the substrate of described back-gate electrode below, be prepared with heavily doped region.
9. carry on the back as claimed in claim 8 grid modulation and entirely exhaust MOS device preparation method, it is characterized in that, described area of grid comprises NMOS area of grid and PMOS area of grid, described back gate region comprises NMOS back gate region and PMOS back gate region, and the common formation of described NMOS area of grid and described NMOS back gate region one nmos device region, the common formation of described PMOS area of grid and described PMOS back gate region one PMOS device area.
10. carry on the back as claimed in claim 9 grid modulation and entirely exhaust MOS device preparation method, it is characterized in that, described MOS device is CW structure or FW structure;
When described MOS device is CW structure, the substrate that is arranged in described nmos device region is provided with P well region, and the substrate that is arranged in described PMOS device area is provided with N well region;
When described MOS device is FW structure, the substrate that is arranged in described nmos device region is provided with N well region, and the substrate that is arranged in described PMOS device area is provided with P well region.
11. carry on the back grid modulation as claimed in claim 10 exhausts MOS device preparation method entirely, it is characterized in that, to be arranged in the well region doping type that substrate arranges identical with it for the doping type of described heavily doped region.
12. carry on the back grid modulation as claimed in claim 7 exhausts MOS device preparation method entirely, it is characterized in that, and the material that described insulation film is high-k, its thickness is 50 Ethylmercurichlorendimide～200 Ethylmercurichlorendimides.
13. carry on the back grid modulation as claimed in claim 7 exhausts MOS device preparation method entirely, it is characterized in that, the material of described epitaxial loayer is mono-crystal gallium nitride.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107222197A (en) * | 2016-03-21 | 2017-09-29 | 二劳额市首有限公司 | Level shifter, digital analog converter, buffer amplifier, source electrode driver and electronic installation |
| CN108565212A (en) * | 2017-11-29 | 2018-09-21 | 珠海创飞芯科技有限公司 | A kind of production method and MOS transistor of MOS transistor |
| CN108631768A (en) * | 2017-03-15 | 2018-10-09 | 格芯公司 | Circuit tuning scheme for FDSOI |
| CN110310678A (en) * | 2019-06-04 | 2019-10-08 | 上海新储集成电路有限公司 | A kind of intelligent chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5610083A (en) * | 1996-05-20 | 1997-03-11 | Chartered Semiconductor Manufacturing Pte Ltd | Method of making back gate contact for silicon on insulator technology |
| CN1909231A (en) * | 2005-08-01 | 2007-02-07 | 株式会社瑞萨科技 | Semiconductor device and semiconductor integrated circuit using the same |
| CN103000671A (en) * | 2011-09-16 | 2013-03-27 | 中国科学院微电子研究所 | MOSFET (metal oxide semiconductor field effect transistor) and manufacturing method thereof |
| CN103337519A (en) * | 2013-06-26 | 2013-10-02 | 清华大学 | Field effect transistor and forming method thereof |
-
2014
- 2014-03-21 CN CN201410109947.6A patent/CN103928520A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5610083A (en) * | 1996-05-20 | 1997-03-11 | Chartered Semiconductor Manufacturing Pte Ltd | Method of making back gate contact for silicon on insulator technology |
| CN1909231A (en) * | 2005-08-01 | 2007-02-07 | 株式会社瑞萨科技 | Semiconductor device and semiconductor integrated circuit using the same |
| CN103000671A (en) * | 2011-09-16 | 2013-03-27 | 中国科学院微电子研究所 | MOSFET (metal oxide semiconductor field effect transistor) and manufacturing method thereof |
| CN103337519A (en) * | 2013-06-26 | 2013-10-02 | 清华大学 | Field effect transistor and forming method thereof |
Non-Patent Citations (1)
| Title |
|---|
| P.SIFFERT 等: "《硅技术的发展和未来》", 28 February 2009, 冶金工业出版社 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107222197A (en) * | 2016-03-21 | 2017-09-29 | 二劳额市首有限公司 | Level shifter, digital analog converter, buffer amplifier, source electrode driver and electronic installation |
| CN108631768A (en) * | 2017-03-15 | 2018-10-09 | 格芯公司 | Circuit tuning scheme for FDSOI |
| CN108631768B (en) * | 2017-03-15 | 2022-05-24 | 格芯(美国)集成电路科技有限公司 | Circuit tuning scheme for FDSOI |
| CN108565212A (en) * | 2017-11-29 | 2018-09-21 | 珠海创飞芯科技有限公司 | A kind of production method and MOS transistor of MOS transistor |
| CN110310678A (en) * | 2019-06-04 | 2019-10-08 | 上海新储集成电路有限公司 | A kind of intelligent chip |
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