CN103985748B - Quasiconductor is arranged and manufacture method - Google Patents
Quasiconductor is arranged and manufacture method Download PDFInfo
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- CN103985748B CN103985748B CN201310050053.XA CN201310050053A CN103985748B CN 103985748 B CN103985748 B CN 103985748B CN 201310050053 A CN201310050053 A CN 201310050053A CN 103985748 B CN103985748 B CN 103985748B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
This application discloses a kind of quasiconductor to arrange and manufacture method.One example arranges and may include that substrate；The backgate formed on substrate；The fin formed in the side of backgate；And the backgate dielectric layer being sandwiched between backgate and fin.
Description
Technical field
It relates to semiconductor applications, include fin (fin) structure more particularly, to one
Quasiconductor arrange and manufacture method.
Background technology
It is increasingly miniaturized brought challenge, such as short-channel effect in order to tackle semiconductor device
Deng, it has been proposed that multiple high performance device, such as UTBB (ultra-thin embedment oxide and basis
Body) device and FinFET (fin formula field effect transistor) etc..
UTBB devices use ET-SOI (very thin-semiconductor-on-insulator) substrate.Due to SOI
Substrate is imbedded the existence of oxide (BOX), short-channel effect can be suppressed.It addition, can
Back-gate electrode is set with SOI substrate dorsal part, controls the threshold voltage of device, such that it is able to have
Effect reduces the power consumption of device and (such as, by promoting threshold voltage when device ends, thus drops
Low-leakage current).But, the cost of ET-SOI is high, and there is self-heating problem.And,
Along with being increasingly miniaturized of device, ET-SOI is increasingly difficult to manufacture.
FinFET is a kind of solid type device, is included in the fin (fin) being vertically formed on substrate,
The conducting channel of device can be formed in fin.It is not increased owing to the height of fin can be promoted
Area occupied (footprint), such that it is able to increase the current driving ability of per unit area occupied.
But, FinFET can not efficiently control its threshold voltage.And, continuous along with device
Miniaturization, fin is more and more thinner, thus easily caves in the fabrication process.
Summary of the invention
The purpose of the disclosure is to provide a kind of quasiconductor to arrange and manufacturer at least in part
Method.
According to an aspect of this disclosure, it is provided that a kind of quasiconductor is arranged, including: substrate；
The backgate formed on substrate；The fin formed in the side of backgate；And be sandwiched in backgate and fin it
Between backgate dielectric layer.
According to another aspect of the present disclosure, it is provided that a kind of method manufacturing quasiconductor setting, bag
Include: form backgate groove in the substrate；The sidewall of backgate groove is formed backgate dielectric layer；Support or oppose
Grid groove is filled conductive material, forms backgate；Substrate is patterned, to be formed and backgate one
The fin that the backgate dielectric layer of side is adjacent.
According to the exemplary embodiment of the disclosure, it is disposed adjacent backgate with fin.With this structure it is
Basis, can make multiple device, such as fin formula field effect transistor (FinFET).At this
In the device of sample, on the one hand, backgate can be passed through, efficiently control the threshold voltage of device.
On the other hand, backgate can serve as the supporting construction of fin, contributes to improving reliability of structure.
Accompanying drawing explanation
By description to disclosure embodiment referring to the drawings, the disclosure above-mentioned and its
He will be apparent from objects, features and advantages, in the accompanying drawings:
Fig. 1 shows the perspective view that the quasiconductor according to one embodiment of the disclosure is arranged；
Fig. 2 shows the perspective view that the quasiconductor according to another embodiment of the disclosure is arranged；
Fig. 3 shows the quasiconductor shown in Fig. 2 and arranges the perspective view after cutting along A-A ' line；
Fig. 4-23 shows the stream manufacturing quasiconductor setting according to another embodiment of the disclosure
The schematic diagram in multiple stages in journey.
Detailed description of the invention
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these
Describe the most exemplary, and be not intended to limit the scope of the present disclosure.Additionally, in following description
In, eliminate the description to known features and technology, to avoid unnecessarily obscuring the disclosure
Concept.
Various structural representations according to disclosure embodiment shown in the drawings.These figures are also
Non-is drawn to scale, wherein in order to understand the purpose of expression, is exaggerated some details, and
And some details may be eliminated.Various regions shown in figure, the shape of layer and they
Between relative size, position relationship be only exemplary, reality is likely to be due to manufacturing tolerance
Or technical limitations and deviation, and those skilled in the art according to actually required can be additionally
Design has difformity, size, the regions/layers of relative position.
In the context of the disclosure, when one layer/element is referred to as positioned at another layer/element " on "
Time, this layer/element can be located immediately on this another layer/element, or can deposit between them
At intermediate layer/element.If it addition, one towards in one layer/element be positioned at another layer/element
On " ", then when turn towards time, this layer/element may be located at this another layer/element D score.
According to embodiment of the disclosure, it is provided that a kind of quasiconductor is arranged.This quasiconductor is arranged can
To be included in the fin and backgate being disposed adjacent on substrate.Between fin and backgate by backgate medium every
Open, such that it is able to by applying biasing to backgate, fin is controlled by.According to an example,
Fin can be formed by a part for substrate by being patterned substrate.Alternatively, fin
Can be by being patterned being formed to the epitaxial layer of Grown.
According to embodiment of the disclosure, backgate can make electrical contact with substrate.As such, it is possible to pass through
Substrate, to apply biasing to backgate.Apply efficiency to improve biasing, substrate can be formed
There is well region, thus backgate makes electrical contact with well region.Can come by arriving the electrical contacts of well region
Biasing is applied to backgate.It addition, in order to reduce the contact resistance between backgate and well region further,
Position corresponding with backgate in well region could be formed with contact area.Mixing of this contact area
Miscellaneous concentration can be higher than the doping content of remainder in well region.
According to embodiment of the disclosure, multiple quasiconductor can be formed based on said structure
Device, such as FinFET.Although this structure including backgate, but it being the most permissible
Present fin-shaped, thus existing various FinFET manufacturing process and the equipment of manufacture are the most applicable.
Therefore, it can apply the technology of the disclosure, and without again developing other manufacturing process and system
Manufacturing apparatus.
This FinFET such as can be included on substrate formed and fin (and backgate)
The grid stacking intersected.In order to electrically insulate grid stacking and substrate, FinFET can be included on substrate
Formed sealing coat, this sealing coat expose middle fin a part (this part be used as FinFET
Real fin), and grid stacking be formed on sealing coat.Block owing to the bottom of fin is isolated layer,
So grid stacking is difficult to control effectively the bottom of fin, consequently, it is possible to cause warp between source and drain
By the leakage current bottom fin.For suppressing this leakage current, FinFET can include the dew being positioned at fin
Go out the break-through stop part (PTS) of beneath portions.Such as, this PTS can be located substantially in fin
It is isolated in the part that layer blocks.
Grid are stacked in fin and define channel region (corresponding to stacking, with grid, the part intersected in fin),
And thus define source/drain region (corresponding to being positioned at the part of channel region opposite sides in fin).For
Avoid the interference between grid stacking and backgate, could be formed with between them dielectric layer and because of
This electric isolution.
According to some examples, in order to strengthen device performance, strain source/drain technology can be applied.Example
As, source/drain region can include and the semiconductor layer of fin different materials, such that it is able to execute to channel region
Add stress.Such as, for p-type device, compressive stress can be applied；And for n-type device,
Tension can be applied.
Can be such as system of getting off according to being disposed adjacent of some examples of the disclosure, above-mentioned fin and backgate
Make.For example, it is possible to form backgate groove in the substrate, by filling conduction material in this backgate groove
The material polysilicon etc. such as metal, doping forms backgate.It addition, before filling backgate groove,
Backgate dielectric layer can be formed on the sidewall of backgate groove.According to an advantageous example, this backgate
Dielectric layer can be made by side wall (spacer) formation process, thus can be with Simplified flowsheet.
It follows that substrate can be patterned, form the fin adjacent with backgate dielectric layer.Such as,
So substrate can be patterned so that backgate groove side sidewall (more specifically, the back of the body
The backgate dielectric layer formed on this sidewall of grid groove) on leave (fin-shaped) part of substrate.
For the ease of backgate groove and the composition of fin, according to an advantageous example, can on substrate shape
Become composition auxiliary layer.This composition auxiliary layer can be patterned to have open corresponding with backgate groove
Mouthful, and pattern-transferringlayer layer can be formed on the side sidewall that it is relative with opening.So,
Composition backgate groove (hereinafter referred to as " can be carried out with composition auxiliary layer and pattern-transferringlayer layer as mask
One composition ")；Furthermore it is possible to pattern-transferringlayer layer is mask, carry out composition fin (hereinafter referred to as "
Two compositions ").
So, fin is formed by twice composition: in the first composition, forms a side of fin；
And in the second composition, form another side of fin.In the first composition, fin still with substrate
Main body be connected and be therefore supported.It addition, in the second composition, fin is connected also with backgate
Therefore it is supported.As a result, it is possible to prevent from the manufacture process of fin is caved in, and therefore can be more
High productivity manufactures relatively thin fin.
Before the second composition, dielectric layer can be formed in backgate groove, to cover backgate.
On the one hand this dielectric layer can make backgate (such as stacking) electric isolution with grid, on the other hand can
To prevent the second composition from backgate being impacted.
It addition, for the ease of composition, according to an advantageous example, side wall formation process can be pressed,
To be formed pattern-transferringlayer layer on the sidewall of composition auxiliary layer.Owing to side wall formation process need not
Mask, such that it is able to reduce the number of masks used in technique.In order to only at composition auxiliary layer one
Side forms pattern-transferringlayer layer, first can be respectively formed preparation figure according to side wall technique in its both sides
Case transfer layer.Then, such as by tilting (angular) ion implanting, side is changed
The character of preparation pattern-transferringlayer layer, such that it is able to come relative to the preparation pattern-transferringlayer layer of opposite side
The preparation pattern-transferringlayer layer of this side of selective removal.As a result, preparation figure is left at opposite side
Case transfer layer, which constitutes the pattern-transferringlayer layer for forming fin.According to an advantageous example, also
Side wall can be formed on composition auxiliary layer and form auxiliary layer.Such as, this side wall forms auxiliary layer
The material (such as, nitride) identical with pattern-transferringlayer layer can be included.Carrying out angle-tilt ion
During injection, ion can also enter into side wall and be formed in auxiliary layer, and therefore changes its character.
So, in the preparation coming this side of selective removal relative to the preparation pattern-transferringlayer layer of opposite side
During pattern-transferringlayer layer, this side wall forms auxiliary layer and can also be removed.
According to an example, substrate can include Si, Ge, SiGe, GaAs, GaSb, AlAs,
InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, and composition auxiliary layer is permissible
Including non-crystalline silicon.In this case, in order to avoid unnecessarily carving during composition backgate groove
Erosion composition auxiliary layer, can form protective layer on the end face of composition auxiliary layer.It addition, in shape
Before becoming composition auxiliary layer, it is also possible to form stop-layer on substrate.For composition auxiliary layer
Composition (to form opening wherein) can stop at this stop-layer.Such as, protective layer is permissible
Including oxide (e.g., silicon oxide), pattern-transferringlayer layer can include nitride, and stop-layer is permissible
Including oxide (e.g., silicon oxide).
It addition, according to some examples of the disclosure, adjacent with backgate at fin fabricated as described above
After setting, FinFET can be made as got off.For example, it is possible to be formed with fin and backgate
Forming sealing coat on substrate, this sealing coat exposes a part for fin.It is then possible at sealing coat
The grid stacking that upper formation is intersected with fin (and backgate).
In order to form above-mentioned PTS, being formed after sealing coat and can be stacked it forming grid
Before, carry out ion implanting.Each dielectric layer (the example existed due to form factor and the top thereof of fin
As, pattern-transferringlayer layer etc.), PTS can be substantially formed in fin and be isolated the part that layer blocks
In.
The disclosure can present in a variety of manners, some of them example explained below.
Fig. 1 shows the perspective view that the quasiconductor according to one embodiment of the disclosure is arranged.As
Shown in Fig. 1, this quasiconductor arranges and includes substrate 100, such as body Semiconductor substrate such as Si, Ge
Deng, compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP,
GaN, SiC, InGaAs, InSb, InGaSb etc., semiconductor-on-insulator substrate (SOI)
Deng.For convenience of description, it is described as a example by body silicon substrate and silicon based material below.
This quasiconductor arranges the combination setting being additionally included on substrate fin and the backgate formed.Specifically
Ground, this combination arranges and can be included on substrate the fin 104 being disposed adjacent and backgate formed
120.The width of fin 104 such as be about 3-28nm, and and backgate 120 between be situated between by backgate
Matter layer 116 separates.Backgate dielectric layer 116 can include various suitable dielectric substance, example
Such as oxide (such as, silicon oxide), its equivalent thickness (dimension in horizontal direction in paper in figure
Degree) such as it is about 10-40nm.Backgate 120 can include various suitable conductive material, as
The polysilicon of doping, its width (dimension in horizontal direction in paper in figure) is such as about
5-30nm.Backgate 120 can make electrical contact with substrate 100, such that it is able to by substrate 100 to
Backgate 120 applies biasing.To this end, substrate 100 can include well region 100-1, to strengthen
Electrical contact with backgate 120.
In the example of fig. 1, fin 104 and substrate 100 one, by a part for substrate 100
Formed.Although it is to be herein pointed out in FIG well region 100-1 is shown as also into
In fin 104, but the disclosure is not limited to this.Such as, well region 100-1 may be located at fin 104
In the substrate portions of lower section, and do not enter in fin 104 (particularly, bottom fin 104
In the case of forming break-through stop part, as described below).
Fig. 1 also show the dielectric layer 124 being positioned on backgate 120 end face.Dielectric layer
124 such as can include nitride (such as, silicon nitride).It addition, also show in FIG
The dielectric layer arranged on the backgate 120 side with fin 104 opposite side.According to the disclosure
An example, this dielectric layer can be with backgate dielectric layer 116 shape in identical manufacturing step
Become and include that identical material (therefore, has when this dielectric layer referenced below for convenience
Time be also referred to as backgate dielectric layer).This dielectric layer and dielectric layer 124 can be by backgates
120 remaining parts formed with substrate face (upper surface in Fig. 1) (such as, grid stacking)
Electric isolution.
Fig. 2 shows the perspective view that the quasiconductor according to another embodiment of the disclosure is arranged, and
Fig. 3 shows the quasiconductor shown in Fig. 2 and arranges the perspective view after cutting along A-A ' line.Fig. 2
Arrange with the quasiconductor shown in 3 and to include substrate 200 equally and to be formed over substrate 200
The combination of fin and backgate is arranged.Similar with the embodiment of Fig. 1, this combination arranges and can include position
The fin 204 being disposed adjacent on substrate and backgate 220.Lead between fin 204 and backgate 220
Cross backgate dielectric layer 216 to separate.In order to strengthen the electricity between backgate 220 and base substrate 200
Contact, can include well region 200-1 in base substrate 200.About these features structure and
Material parameter, may refer to the explanation above in association with Fig. 1.
It addition, this quasiconductor arrange be additionally included on substrate 200 formed sealing coat 202 and
The combination with fin and backgate formed on sealing coat 202 arranges the grid stacking intersected.Such as,
Sealing coat 202 can include oxide.Grid stacking can include gate dielectric layer 238 and grid conductor
Layer 240.Such as, gate dielectric layer 238 can include high-K gate dielectric such as HfO2, thickness is
1-5nm；Grid conductor layer 240 can include metal gate conductor.It addition, gate dielectric layer 238 is also
One layer of thin oxide (high-K gate dielectric is formed on this oxide) can be included, such as thick
Degree is 0.3-1.2nm.Between gate dielectric layer 238 and grid conductor 240, it is also possible to form work content
Number regulating course (not shown).It addition, grid stacking both sides are formed with grid side wall 230.Such as,
Grid side wall 230 can include nitride, and thickness is about 5-20nm.Backgate 220 is by its end face
On dielectric layer 224 and backgate dielectric layer on side, side and grid stacking isolation.
Due to the existence of grid stacking, in fin, define that channel region (stacks phase corresponding to fin with grid
The part handed over) and source/drain region (corresponding to being positioned at the part of channel region opposite sides in fin).?
During quasiconductor shown in Fig. 2 is arranged, in source/drain region, also on the surface of fin, growth formation is partly led
Body layer 232.Semiconductor layer 232 can include the material being different from fin 204, so as to
Fin 204 (channel region the most therein) applies stress.Such as, include Si's at fin 204
In the case of, for n-type device, semiconductor layer 232 can include the Si:C (atomic percent of C
Ratio such as about 0.2-2%), to apply tension；For p-type device, semiconductor layer 232
SiGe (such as, the atomic percent of Ge is about 15-75%) can be included, answer to apply to press
Power.It addition, the existence of semiconductor layer 232 also broadening source/drain region, thus the most follow-up system
Make the contact site with source/drain region.
As it is shown on figure 3, grid stack the side phase with fin 204 (with backgate 220 opposite side)
Hand over.Specifically, gate dielectric layer 238 and this contacts side surfaces of fin 204, thus grid conductor layer 240
Can control to produce conducting channel on this side of fin 204 by gate dielectric layer 238.
In the example shown in Fig. 2 and 3, further it is shown that be positioned at some layer of knot at fin 204 top
Structure.These Rotating fields can be such as to remain in the manufacture process that this quasiconductor is arranged, right
The structure and the work that arrange in this quasiconductor there is no materially affect.According to some examples of the disclosure,
These residual layer structures can also be removed.
Fig. 4-23 shows the stream manufacturing quasiconductor setting according to another embodiment of the disclosure
The schematic diagram in multiple stages in journey.
As shown in Figure 4, it is provided that substrate 1000, such as body silicon substrate.In substrate 1000,
Such as by ion implanting, it is formed with well region 1000-1.Such as, for p-type device, permissible
Form N-shaped well region；And for n-type device, p-type well region can be formed.Such as, N-shaped trap
District can be formed by implant n-type impurity such as P or As in substrate 1000, p-type well region
Can be formed by implanted with p-type impurity such as B in substrate 1000.If it is required, at note
Can also anneal after entering.Those skilled in the art are it is conceivable that various ways forms n
Type trap, p-type trap, do not repeat them here.
Substrate 1000 can sequentially form stop-layer 1006, composition auxiliary layer 1008, protect
Sheath 1048 and side wall form auxiliary layer 1010.Such as, stop-layer 1006 can protect oxidation
Thing (such as silicon oxide), thickness is about 5-25nm；Composition auxiliary layer 1008 can include non-crystalline silicon,
Thickness is about 50-200nm；Protective layer 1048 can include oxide (such as silicon oxide), thickness
It is about 20-50nm；Side wall forms auxiliary layer 1010 can include nitride (such as silicon nitride),
Thickness is about 5-15nm.The material of these layers selects primarily to carry during subsequent processes
For Etch selectivity.It will be appreciated by those skilled in the art that these layers can include that other are suitable
Material, and some of which layer can omit in some cases.
Then, side wall formation auxiliary layer 1010 can form photoresist 1012.The most logical
Cross photoetching, photoresist 1012 is patterned, with the backgate phase formed wherein and will be formed
Corresponding opening.The width D 1 of opening such as can be about 15-100nm.
Then, as it is shown in figure 5, successively side wall can be formed with photoresist 1012 as mask
Auxiliary layer 1010, protective layer 1048 and composition auxiliary layer 1008 perform etching, such as reactive ion
Etching (RIE), thus form auxiliary layer 1010, protective layer 1048 and composition auxiliary at side wall
Layer 1008 is formed opening.Etching can stop at stop-layer 1006.Certainly, if composition
Auxiliary layer 1008 and under substrate 1000 between there is enough Etch selectivities, even may be used
To remove this stop-layer 1006.Afterwards, photoresist 1012 can be removed.
It is then possible on the side sidewall of composition auxiliary layer 1008 (relative with opening), shape
Become pattern-transferringlayer layer.An example according to the disclosure, this pattern-transferringlayer layer can be formed.
Specifically, as shown in Figure 6, (can go in structure shown in Fig. 5 according to side wall formation process
Except photoresist 1012) surface on deposit one layer of nitride, then nitride is carried out RIE,
To be formed the preparation pattern-transferringlayer layer of side wall form on the sidewall of assisted drawing layer 1008 both sides
1014.The thickness of the nitride layer deposited can be about 3-28nm and (substantially determines shape subsequently
The width of the fin become).This deposit such as can be passed through atomic layer deposition (ALD) and carry out.
Those skilled in the art will know that various ways, to form this side wall, does not repeats them here.Then,
As indicated by the arrows in fig. 6, angle-tilt ion injection can be carried out, to change assisted drawing layer 1008
Preparation pattern-transferringlayer layer on side (in figure left side) sidewall (and assisted drawing layer 1008
On side wall formed auxiliary layer 1010) character (such as, due to ion implanting wherein
Cause damage).Then, optional relative to unmodified opposite side (right side in figure) preparation pattern
Transfer layer comes modified for selective removal such as RIE (left side) preparation pattern-transferringlayer layer (and top
The side wall in portion forms auxiliary layer 1010), thus obtain being positioned at the figure on opposite side (right side in figure)
Case transfer layer 1014.
It follows that as it is shown in fig. 7, can be with composition auxiliary layer 1008 and pattern-transferringlayer layer 1014
For mask, substrate 1000 is patterned, to form backgate groove BG wherein.Here, can
Successively stop-layer 1006 and substrate 1000 are carried out RIE, form backgate groove BG.Due to
The existence of protective layer 1048, these RIE do not interfere with composition auxiliary layer 1008.Certainly,
If had between the material of the material of composition auxiliary layer 1008 and stop-layer 1006 and substrate 1000
There are enough Etch selectivities, it might even be possible to remove protective layer 1048.
According to an advantageous embodiment, backgate groove BG can enter in well region 1000-1.Such as,
As it is shown in fig. 7, the bottom surface of the backgate groove BG end face compared to well region 1000-1 or ultimately form
FET channel bottom the degree of depth of recessed D2.D2 can be in the scope of about 10-30nm.
Subsequently, as shown in Figure 8, backgate dielectric layer can be formed on the sidewall of backgate groove BG
1016.Backgate dielectric layer 1016 can include any suitable dielectric substance, such as oxide or
High K dielectric material such as HfO2.Here, backgate can be made according to side wall formation process
Dielectric layer 1016.For example, it is possible to by passing through thermal oxide on the surface of structure shown in Fig. 7,
Form one layer of equivalent thickness (EOT) and be about the oxide skin(coating) of 10-40nm, then to this oxygen
Compound layer carries out RIE, forms the backgate dielectric layer of side wall form.
Here, in order to reduce the contact resistance between the backgate and substrate that will be formed, such as Fig. 8
In arrow shown in, ion implanting can be carried out via backgate groove BG, with at substrate 1000
(particularly well region 1000-1) is formed contact area 1018.The doping type of ion implanting and trap
The doping type in district is identical, thus the doping content of contact area 1018 (such as, for
1E18-1E21cm-3) higher than the doping content at remainder in well region 1000-1.Due to D2
The existence of (seeing Fig. 7), is possible to prevent the adulterant of ion implanting to enter into and subsequently forms
In fin.
Then, as it is shown in figure 9, conductive material can be filled in backgate groove BG, to be formed
Backgate 1020.Backgate 1020 can include the semi-conducting material of doping (and therefore conduction) such as
Polysilicon, the polarity (p-type or N-shaped) of doping can be used to the threshold voltage of adjusting means,
And the concentration of doping can be about 1E18-1E21cm-3.Filling such as can be by depositing and right
Rear eat-back conductive material is carried out.Alternatively, backgate 1020 can include metal such as TiN, W
Deng or a combination thereof.According to an advantageous example, the end face of backgate 1020 can be with substrate 1000
End face substantially maintain an equal level or (omit) be higher than substrate 1000 end face.
After backgate formed as discussed above, next substrate 1000 can be patterned,
Form fin.
In the present embodiment, will be subsequently formed the grid stacking intersected with fin and manufacture FinFET.For
Avoid the interference between backgate 1020 and grid stacking, can as shown in Figure 10, at backgate groove
Further filling dielectric layer 1024 in BG, to cover backgate 1020.Such as, dielectric layer
1024 can include nitride, and can be then etched back by deposited oxide and formed.It addition,
According to an advantageous example, before filling dielectric layer 1024, can be situated between with selective removal backgate
Part (in this example, protective layer 1048 and the backgate that matter layer 1016 is exposed by backgate 1020
Dielectric layer 1016 all includes oxide, thus can also be selectively removed) so that electrolyte
Layer 1024 is completely covered backgate stacking (backgate 1020 and backgate dielectric layer 1016), to avoid
It is impacted in process subsequently.
It follows that as shown in figure 11, selective etch can be passed through, as molten by TMAH
Liquid carries out wet etching, removes composition auxiliary layer 1008, leaves pattern-transferringlayer layer 1014.So
After, can be with pattern-transferringlayer layer 1014 as mask, further selective etch such as RIE stop layer
1006 and substrate 1000.So, as shown in figure 12, just (in figure left in backgate 1020 side
Side) leave the substrate portions 1004 of fin-shaped, they are corresponding to the shape of pattern-transferringlayer layer 1014
Shape.
Although it is to be herein pointed out in fig. 12 the bottom of fin 1004 being shown as and carry on the back
The bottom of grid 1020 is the most fair, but the disclosure is not limited to this.According to the example of the disclosure,
So that backgate 1020 can efficiently control fin 1004, in the vertical direction fin 1004
Expanded range is preferably more than the expanded range of backgate 1020.
So, the combination just having obtained the fin according to this embodiment and backgate is arranged.Such as Figure 12
Shown in, this combination arranges and includes backgate 1020 and be positioned at backgate 1020 side (left side in figure)
Fin 1004, accompany backgate dielectric layer 1016 between backgate 1020 and fin 1004.Backgate 1020
End face be provided with dielectric layer 1024, and cover equally on opposite side (right side in figure) side
There is backgate dielectric layer 1016.
In the combination of Figure 12 is arranged, further it is shown that pattern-transferringlayer layer 1014 and stop-layer 1006
Residue.These residues there is no materially affect for subsequent process, therefore can not at this
Give and comprehending, with Simplified flowsheet.Of course, it is possible to on-demand, they are removed.
After the combination being obtained fin and backgate by above-mentioned flow process is arranged, can this combination arrange
Based on, manufacture multiple device.It is to be herein pointed out in the example depicted in fig. 12,
Together form three combinations to arrange.But the disclosure is not limited to this.For example, it is possible to according to need
Want, form more or less of combination and arrange.It addition, the layout that the combination formed is arranged is also
It is not necessarily parallel setting as depicted.
Following, explanation is manufactured the exemplary method flow process of FinFET.
For manufacturing FinFET, sealing coat can be formed on substrate 1000.Such as, such as Figure 13
Shown in, on substrate, such as can form dielectric layer 1002 (for example, it is possible to wrap by deposit
Include oxide), then the dielectric layer of deposit is etched back, forms sealing coat.Generally,
The dielectric layer of deposit can be completely covered combination and arrange, and can be to deposit before eat-back
Electrolyte planarize, as chemically mechanical polishing (CMP).According to a preferred exemplary,
By sputtering, the dielectric layer of deposit can be carried out planarization process.Such as, sputter permissible
Use plasma, such as Ar or N plasma.
In the case of forming well region 1000-1 in substrate 1000, the end face of well region can not be low
End face (seeing Figure 14) in sealing coat 1002.Such as, the end face of sealing coat 1002 is permissible
Expose slightly well region, i.e. the end face that the end face of sealing coat 1002 is slightly below well region 1000-1 is (attached
Figure is shown without the difference in height between them).
For improving device performance, particularly reduce source and drain leakage, according to an example of the disclosure,
As shown in the arrow in Figure 14, break-through stop part (PTS) can be formed by ion implanting
1046.Such as, for n-type device, can be with implanted with p-type impurity, such as B, BF2Or
In；For p-type device, can be with implant n-type impurity, such as As or P.Ion implanting can be hung down
Straight in substrate surface.Control the parameter of ion implanting so that PTS is formed at fin 1004 and is positioned at
In part under sealing coat 1006 surface, and there is desired doping content, e.g., from about
5E17-2E19cm-3, and doping content should be higher than that the doping content of well region 1000-1 in substrate.
It should be noted that, the form factor (elongated shape) arranged due to the combination of fin and backgate and top thereof
The each dielectric layer existed, is conducive to forming precipitous dopant profiles in the depth direction.Permissible
Carry out anneal such as spike annealing, laser annealing and/or short annealing, to activate the adulterant injected.
This PTS contributes to reducing source and drain leakage.
It follows that can be formed on sealing coat 1002 with to combine setting (the most therein
Fin) crossing grid stacking.Such as, this can be carried out as follows.Specifically, as shown in figure 15,
Such as by deposit, form gate dielectric layer 1026.Such as, gate dielectric layer 1026 can include
Oxide, thickness is about 0.8-1.5nm.In the example depicted in fig. 15, illustrate only ∏ shape
Gate dielectric layer 1026.But, gate dielectric layer 1026 can also be included in sealing coat 1002
The part extended on end face.Then, such as by deposit, form grid conductor layer 1028.Such as,
Grid conductor layer 1028 can include polysilicon.Grid conductor layer 1028 can be filled combination and be arranged it
Between gap, it is possible to carry out planarization and process such as CMP.
Such as Figure 16 (Figure 16 (b) shows the sectional view of BB ' line along Figure 16 (a)) institute
Show, grid conductor layer 1028 is patterned.In the example of Figure 16, grid conductor layer 1028
It is patterned to the bar shaped intersected with fin.According to another embodiment, it is also possible to the grid conductor after composition
Layer 1028 is mask, is patterned gate dielectric layer 1026 further.
After forming the grid conductor of composition, such as, can carry out haloing with grid conductor as mask
(halo) inject and extension area (extension) is injected.
It follows that such as Figure 17, (Figure 17 (b) shows C1C1 ' line along Figure 17 (a)
Sectional view, Figure 17 (c) shows the sectional view of C2C2 ' line along Figure 17 (a)) shown in,
Grid side wall 1030 can be formed on the sidewall of grid conductor layer 1028.For example, it is possible to by forming sediment
Long-pending formation thickness is about the nitride (such as silicon nitride) of 5-20nm, then carries out nitride
RIE, forms grid side wall 1030.Here, the amount of RIE can be controlled when forming grid side wall,
Make grid side wall 1030 essentially without being formed on the sidewall that combination is arranged.People in the art
Member knows that various ways, to form this side wall, does not repeats them here.
Being formed after side wall, source/drain (S/D) can be carried out with grid conductor and side wall as mask
Inject.Subsequently, the ion injected can be activated by annealing, to form source/drain region, obtains
FinFET。
For improving device performance, according to an example of the disclosure, it is possible to use strain source/drain technology.
Specifically, as Figure 18 (Figure 18 (b) shows the sectional view of C1C1 ' line along Figure 18 (a),
Figure 18 (c) shows the sectional view of C2C2 ' line along Figure 18 (a)) shown in, can remove
The gate dielectric layer 1026 exposed by grid stacking is (if to grid in the patterning process that above grid stack
Dielectric layer 1026 has been also carried out composition, then can omit this step), thus expose fin 1004
A part (corresponding to source/drain region).Extension can be passed through, on the surface that the fin exposed divides
Upper formation semiconductor layer 1032.An embodiment according to the disclosure, can be in grown semiconductor layer
While 1032, carry out adulterating in situ to it.Such as, for n-type device, n can be carried out
Type doping in situ；And for p-type device, p-type doping in situ can be carried out.It addition, in order to
Improving performance further, semiconductor layer 1032 can include the material being different from fin 1004, with
Just stress can be applied to fin 1004 (wherein forming the channel region of device).Such as, at fin
In the case of 1004 include Si, for n-type device, semiconductor layer 1032 can include Si:C
(atomic percent of C is such as about 0.2-2%), to apply tension；For p-type device,
Semiconductor layer 1014 can include SiGe (such as, the atomic percent of Ge is about 15-75%),
To apply compressive stress.On the other hand, the semiconductor layer 1032 certain journey of broadening in the horizontal of growth
Degree, thus contribute to subsequently forming the contact site of source/drain region.
In the case of grid conductor layer 1028 includes polysilicon, the growth of semiconductor layer 1032 can
Can may occur on the end face of sacrificial gate conductor layer 1028.This does not shows that in the accompanying drawings.
In the above-described embodiments, after the combination forming fin and backgate is arranged, directly define
Grid stack.The disclosure is not limited to this.Such as, replacement gate process is equally applicable to the disclosure.
According to another embodiment of the disclosure, the gate dielectric layer 1026 formed in fig .15 and grid
Conductor layer 1028 be sacrificial gate dielectric layer and sacrificial gate conductor layer (so, by combine Figure 15,
The grid that 16 operations described obtain are stacked as sacrificial gate stacking).It follows that can equally by with
The operation that upper combination Figure 17 describes forms grid side wall 1030.It addition, more than equally pressing
The operation described in conjunction with Figure 18, applies strain source/drain technology.
It follows that sacrificial gate stacking can be processed, to be formed according to replacement gate process
The real grid stacking of device.Such as, this can be carried out as follows.
Specifically, such as Figure 19, (Figure 19 (a) is corresponding to the sectional view of Figure 18 (b), Figure 19
B () is corresponding to the sectional view of Figure 18 (c)) shown in, such as by deposit, form electrolyte
Layer 1034.This dielectric layer 1034 such as can include oxide.Subsequently, to this electrolyte
Layer 1034 carries out planarization and processes such as CMP.This CMP can stop at grid side wall 1030,
Thus expose sacrificial gate conductor layer 1028.Subsequently, such as by TMAH solution, selectivity
Remove sacrificial gate conductor 1028, thus inside grid side wall 1030, define grid groove 1036.Root
According to another example, it is also possible to remove sacrificial gate dielectric layer 1026 further.
Then, such as Figure 20, (Figure 20 (a) is corresponding to the sectional view of Figure 19 (a), Figure 20 (b)
Corresponding to the sectional view of Figure 19 (b), Figure 20 (c) is corresponding to the sectional view of Figure 16 (b)),
Shown in Figure 21 (showing the top view of structure shown in Figure 20), by forming grid in grid groove
Dielectric layer 1038 and grid conductor layer 1040, form final grid stacking.Gate dielectric layer 1038 can
To include high-K gate dielectric such as HfO2, thickness is about 1-5nm.It addition, gate dielectric layer 1038
One layer of thin oxide (high-K gate dielectric is formed on this oxide) can also be included, such as
Thickness is 0.3-1.2nm.Grid conductor layer 1040 can include metal gate conductor.Preferably, exist
Work function regulating course can also be formed between gate dielectric layer 1038 and grid conductor layer 1040 (not show
Go out).
So, the FinFET according to this embodiment has just been obtained.Such as Figure 20, shown in 21, should
FinFET is included on substrate 1000 that formed and backgate 1020 and fin 1004 combination setting
Grid stacking (including gate dielectric layer 1038 and grid conductor layer 1040) intersected.Such as Figure 20 (c)
Be best illustrated in, grid conductor layer 1040 can via gate dielectric layer 1038, control fin 1004 (with
Backgate 1020 opposite side) produce conducting channel on side.It addition, backgate 1020 is permissible
Control fin 1004 via backgate dielectric layer 1016, thus be altered as desired the threshold value of FinFET.The back of the body
Grid 1020 are by dielectric layer 1024 and backgate dielectric layer 1016 and grid stacking electric isolution.
After FinFET formed as discussed above, it is also possible to make various electrical contact.Such as,
As shown in figure 22, interlayer dielectric (ILD) can be deposited on the surface of structure shown in Figure 21
Layer 1042.This ILD layer 1042 such as can include oxide.Can be to ILD layer 1042
Carry out planarization and process such as CMP so that it is surface general planar.Then, such as can pass through
Photoetching, formed contact hole, and in the contact hole fill conductive material such as metal (such as, W or
Cu etc.), form contact site, such as with contact site 1044-1 and the source/drain region of grid stacking
Contact site 1044-2 and the contact site 1044-2 with backgate.
Figure 23 (a), (b) respectively illustrate B1B1 ' line, the cross section of B2B2 ' line along Figure 22
Figure.As shown in figure 23, contact site 1044-1 penetrates ILD layer 1042, arrives grid conductor 1040,
And therefore make electrical contact with grid conductor 1040；Contact site 1044-2 penetrates ILD layer 1042 and electricity
Dielectric layer 1034, reaches source/drain region (in this example for semiconductor layer 1032), and therefore with
Source/drain region makes electrical contact with；Contact site 1044-3 penetrate ILD layer 1042, dielectric layer 1034 with
And sealing coat 1002, arrival substrate 1000 (particularly, well region 1000-1 therein), and because of
This makes electrical contact with backgate 1020.Made electrical contact with by these, the required signal of telecommunication can be applied.
Although it is to be herein pointed out in fig 23 the source/drain region of three fins being shown as even
It is connected to identical contact site, but the disclosure is not limited to this.Concrete electric connection mode can root
Depending on design.
In the above description, the ins and outs such as the composition of each layer, etching are not made
Detailed description.It should be appreciated to those skilled in the art that can by various technological means,
Form the layer of required form, region etc..It addition, in order to form same structure, this area skill
Art personnel can be devised by method the most identical with process as described above.It addition,
Although respectively describing each embodiment above, but it is not intended that in each embodiment
Measure can not be advantageously combined use.
Embodiment the most of this disclosure is described.But, these embodiments are only
Descriptive purpose, and be not intended to limit the scope of the present disclosure.The scope of the present disclosure is by appended
Appended claims and their equivalents limit.Without departing from the scope of the present disclosure, those skilled in the art can
To make multiple replacement and amendment, these substitute and amendment all should fall within the scope of the disclosure.
Claims (19)
1. a quasiconductor is arranged, including:
Substrate；
The backgate being formed on substrate, highlighting from substrate；
Formed in the side of backgate, highlight from substrate and the fin of extension adjacent with backgate；
The backgate dielectric layer being sandwiched between backgate and fin；
The sealing coat formed on substrate, described sealing coat exposes a part for fin；With
The grid stacking formed on sealing coat, described grid stacking intersects with described fin and backgate, its
Described in grid stacking with backgate between isolated by dielectric layer.
Quasiconductor the most according to claim 1 is arranged, wherein, and the end face of backgate and fin
End face maintain an equal level or higher than the end face of fin.
Quasiconductor the most according to claim 1 is arranged, and wherein, backgate includes conduction material
Expect, and width is 5-30nm.
Quasiconductor the most according to claim 1 arrange, wherein, fin include Si, Ge,
SiGe、GaAs、GaSb、AlAs、InAs、InP、GaN、SiC、InGaAs、InSb、
InGaSb, and width is 3-28nm.
Quasiconductor the most according to claim 1 is arranged, and wherein, backgate dielectric layer includes
Oxide, and equivalent thickness is 10-40nm.
Quasiconductor the most according to claim 1 is arranged, and wherein, substrate includes well region,
Wherein backgate makes electrical contact with well region.
Quasiconductor the most according to claim 6 arrange, also include: described fin by every
The break-through stop part that the beneath portions that absciss layer exposes is formed, the doping content of described break-through stop part
Doping content higher than well region.
Quasiconductor the most according to claim 1 is arranged, and is additionally included in fin and is positioned at grid stacking
The semiconductor layer of growth on the surface of the part of opposite sides.
Quasiconductor the most according to claim 8 is arranged, wherein, if described quasiconductor
It is provided for p-type device, then semiconductor layer band compressive stress；If described quasiconductor is provided for
N-type device, then semiconductor layer band tension.
10. manufacture the method that quasiconductor is arranged, including:
Form backgate groove in the substrate；
The sidewall of backgate groove is formed backgate dielectric layer；
In backgate groove, fill conductive material, form backgate；
Dielectric layer is formed, to cover backgate in backgate groove；
Substrate is patterned, the fin adjacent to form the backgate dielectric layer with backgate side；
Forming sealing coat on substrate, described sealing coat exposes a part for fin；
The grid stacking formed on sealing coat, described grid stacking intersects with described fin and backgate.
11. methods according to claim 10, wherein,
Form backgate groove to include:
Forming composition auxiliary layer on substrate, this composition auxiliary layer is patterned to be had and the back of the body
The opening that grid groove is corresponding；
The sidewall of the composition auxiliary layer side relative with opening is formed pattern-transferringlayer layer；
With this composition auxiliary layer and pattern-transferringlayer layer as mask, substrate is performed etching, with
Form backgate groove, and
Formation fin includes:
Selective removal composition auxiliary layer；And
With pattern-transferringlayer layer as mask, substrate is performed etching, to form fin.
12. methods according to claim 11, wherein, the conduction filled in backgate groove
The end face of material maintains an equal level with the end face of substrate or is higher than the end face of substrate.
13. methods according to claim 11, wherein, form pattern-transferringlayer layer and include:
Press side wall formation process, at the described side of composition auxiliary layer and relative opposite side
Preparation pattern-transferringlayer layer is formed on sidewall；
Carry out angle-tilt ion injection so that ion enters into the preparation pattern being positioned at described opposite side
In transfer layer；And
Selective etch, removes the preparation pattern-transferringlayer layer of described opposite side.
14. methods according to claim 13, also include:
Forming side wall on composition auxiliary layer and form auxiliary layer, wherein, ion is also into this side wall
Formed in auxiliary layer.
15. methods according to claim 14, wherein, substrate include Si, Ge, SiGe,
GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb,
Composition auxiliary layer includes non-crystalline silicon, and
The method also includes: form protective layer on the end face of composition auxiliary layer, with at backgate groove
Etching during protect composition auxiliary layer.
16. methods according to claim 15, also include: formed on substrate and stop
Layer, composition auxiliary layer is formed on this stop-layer.
17. methods according to claim 16, wherein, side wall forms auxiliary layer and includes
Nitride, protective layer includes that oxide, pattern-transferringlayer layer include that nitride, stop-layer include oxygen
Compound.
18. methods according to claim 10, wherein, by side wall formation process,
Backgate dielectric layer is formed on the sidewall of backgate groove.
19. methods according to claim 10, wherein, being formed after sealing coat and
Before forming grid stacking, the method also includes:
Carry out ion implanting, with at the exposed portion of fin break-through formed below stop part.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5610083A (en) * | 1996-05-20 | 1997-03-11 | Chartered Semiconductor Manufacturing Pte Ltd | Method of making back gate contact for silicon on insulator technology |
| CN1643697A (en) * | 2002-03-19 | 2005-07-20 | 国际商业机器公司 | Strained fin fets structure and method |
| CN1707802A (en) * | 2004-06-11 | 2005-12-14 | 国际商业机器公司 | Back gate FinFET SRAM |
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| US7056773B2 (en) * | 2004-04-28 | 2006-06-06 | International Business Machines Corporation | Backgated FinFET having different oxide thicknesses |
| US7102181B1 (en) * | 2005-04-22 | 2006-09-05 | International Business Machines Corporation | Structure and method for dual-gate FET with SOI substrate |
| US7960791B2 (en) * | 2005-06-24 | 2011-06-14 | International Business Machines Corporation | Dense pitch bulk FinFET process by selective EPI and etch |
| CN100527442C (en) * | 2007-06-05 | 2009-08-12 | 北京大学 | Double-fin type channel double-grid multifunction field effect transistor and producing method thereof |
| US7719057B2 (en) * | 2007-07-30 | 2010-05-18 | Intel Corporation | Multiple oxide thickness for a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5610083A (en) * | 1996-05-20 | 1997-03-11 | Chartered Semiconductor Manufacturing Pte Ltd | Method of making back gate contact for silicon on insulator technology |
| CN1643697A (en) * | 2002-03-19 | 2005-07-20 | 国际商业机器公司 | Strained fin fets structure and method |
| CN1707802A (en) * | 2004-06-11 | 2005-12-14 | 国际商业机器公司 | Back gate FinFET SRAM |
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