CN104051532B - The source/drain structures of semiconductor device - Google Patents
The source/drain structures of semiconductor device Download PDFInfo
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- CN104051532B CN104051532B CN201310425120.1A CN201310425120A CN104051532B CN 104051532 B CN104051532 B CN 104051532B CN 201310425120 A CN201310425120 A CN 201310425120A CN 104051532 B CN104051532 B CN 104051532B
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- 239000004065 semiconductor Substances 0.000 title abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 239000000463 material Substances 0.000 claims abstract description 51
- 230000005669 field effect Effects 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 72
- 230000008569 process Effects 0.000 claims description 22
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 10
- 239000000203 mixture Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 9
- IGELFKKMDLGCJO-UHFFFAOYSA-N xenon difluoride Chemical compound F[Xe]F IGELFKKMDLGCJO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims description 4
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 51
- 238000005530 etching Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 239000010408 film Substances 0.000 description 9
- 239000007789 gas Substances 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 239000012071 phase Substances 0.000 description 8
- 239000000376 reactant Substances 0.000 description 8
- 238000005476 soldering Methods 0.000 description 8
- 238000010521 absorption reaction Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000009826 distribution Methods 0.000 description 7
- 239000012159 carrier gas Substances 0.000 description 6
- 239000007787 solid Substances 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000002253 acid Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000007795 chemical reaction product Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000000284 extract Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052756 noble gas Inorganic materials 0.000 description 2
- 150000002835 noble gases Chemical class 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910052692 Dysprosium Inorganic materials 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910052693 Europium Inorganic materials 0.000 description 1
- 229910052688 Gadolinium Inorganic materials 0.000 description 1
- 229910052689 Holmium Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052765 Lutetium Inorganic materials 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 229910052777 Praseodymium Inorganic materials 0.000 description 1
- 229910052772 Samarium Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910052771 Terbium Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910052775 Thulium Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 150000001335 aliphatic alkanes Chemical class 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000000411 inducer Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- -1 tetraethoxy-silicane Alkane Chemical class 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention relates to a kind of source class of semiconductor device, drain electrode structure.The example arrangement of field-effect transistor includes：Substrate, the chamber including first type surface and below first type surface；Gate stack, on the first type surface of substrate；Distance piece is adjacent with the side of gate stack；Shallow trench is isolated（STI）Region, is arranged on the side of gate stack, and wherein, sti region is located in substrate；And source/drain（S/D）Structure, is distributed between gate stack and sti region.S/D structure includes：Strain gauge material in chamber, the lattice paprmeter of strain gauge material is different from the lattice paprmeter of substrate；And it is arranged on S/D extension between substrate and strain gauge material, S/D extension includes extending and be substantially perpendicular to the part of first type surface below distance piece.
Description
Cross-Reference to Related Applications
This application claims requiring entitled " the Source/Drain Structure of submitting on March 13rd, 2013
The priority of the U.S. Provisional Patent Application of Semiconductor Device " the 61/780th, 271, entire contents combine
In this as reference.
Technical field
The present invention relates to IC manufacturing, more specifically, it is related to the semiconductor device with source/drain structures.
Background technology
Semiconductor industry is in progress during pursuing bigger device density, better performance and lower cost
To nano level technical matters node, create such as fin formula field effect transistor from the challenge manufacturing with design aspect
（FinFET）Three dimensional design development.Typical FinFET is made with slim vertical " fin " extending from substrate（Or
Fin structure）, for example by etch away substrate silicon layer a part of forming this fin.This vertical fin is formed
The raceway groove of FinFET.Grid is arranged on above fin（For example, wrap up）.Raceway groove both sides all have grid and allow grid from both sides control
Raceway groove.Additionally, utilizing selective growth SiGe（SiGe）And the source/drain in FinFET（S/D）The partly strain of middle formation
Material can be used to improve the mobility of carrier.
However, in complementary metal oxide semiconductors (CMOS)（CMOS）Manufacture in, exist and implement choosing of these features and technique
War.For example, the non-uniform doping distribution of S/D extension can cause the fluctuation of the such as FinFET characteristic of punch-through effect and leakage,
Thus reducing the performance of device.With the reduction of the spacing between grid length and device, these problems are more prominent.
Content of the invention
According to an aspect of the invention, it is provided a kind of field-effect transistor, including：Substrate, including first type surface and position
Chamber below first type surface；Gate stack, on the first type surface of substrate；Distance piece, at least side with gate stack
Adjacent；Shallow trench is isolated（STI）Region, is arranged on the side of gate stack, and sti region is located in substrate；And source/drain
Pole（S/D）Structure, is distributed between gate stack and sti region.S/D structure includes：Strain gauge material, in chamber, strain
The lattice paprmeter of material is different from the lattice paprmeter of substrate；With S/D extension, it is arranged between substrate and strain gauge material, S/D prolongs
Stretch part to include extending and be substantially perpendicular to the part of first type surface below distance piece.
Preferably, chamber includes the part extending below distance piece.
Preferably, chamber includes the part extending below gate stack.
Preferably, the height between the first type surface of substrate and the bottom surface in chamber is between about 30nm to about 60nm.
Preferably, the second thickness of S/D extension is less than or equal to the first thickness of distance piece.
Preferably, the ratio of second thickness and first thickness is between 0.1 to 1.
Preferably, S/D extension includes SiP, SiCP or SiGeB.
Preferably, strain gauge material includes SiP, SiCP or SiGeB.
Preferably, the first doping content of S/D extension is less than the second doping content of strain gauge material.
Preferably, the ratio of the first doping content and the second doping content is between 0.01 to 0.1.
Preferably, strain gauge material extends above the first type surface of substrate.
Preferably, strain gauge material does not extend above the first type surface of substrate.
According to a further aspect in the invention, there is provided a kind of manufacture field-effect transistor method, including：There is provided and include leading
The substrate on surface；Form shallow trench isolation in substrate（STI）Region；The first type surface of substrate is formed adjacent with sti region
Gate stack；Form the distance piece adjacent with least side of gate stack；Make substrate recessed with formation and distance piece
Adjacent source/drain（S/D）Groove；At the first temperature, S/D groove is exposed to including XeF2、NH3And H2Steam mix
Compound；By silicon to higher second temperature to be formed at the S/D chamber extending below distance piece；Selective growth S/D prolongs
Stretching part makes it be partially fill in S/D chamber；And selective growth is filled in the strain gauge material in S/D chamber.
Preferably, implement at the first temperature by S/D groove under conditions of between about 20 DEG C and about 100 DEG C in temperature
It is exposed to including XeF2、NH3And H2Vapour mixture step.
Preferably, implement silicon to higher under conditions of between about 120 DEG C and about 200 DEG C in temperature
The step of two temperature.
Preferably, implement using anisortopicpiston etch process to make substrate recessed adjacent with distance piece to be formed
Source/drain（S/D）The step of groove.
Preferably, implementing selective growth S/D extension using LPCVD technique makes the step that it is partially filled with S/D chamber.
Preferably, S/D extension is SiCP, and in temperature between about 400 DEG C and about 800 DEG C and pressure is between about
Under conditions of between 1Torr and about 100Torr, by SiH4、CH4、PH3And H2To implement LPCVD technique as reacting gas.
Preferably, S/D extension is SiGeB, and temperature between about 400 DEG C and about 800 DEG C and pressure between
Under conditions of between about 1Torr and about 200Torr, by SiH2Cl2、SiH4、GeH4、HCl、B2H6And H2Real as reacting gas
Apply LPCVD technique.
Preferably, implement the step that selective growth is filled in the strain gauge material in S/D chamber using LPCVD.
Brief description
When reading in conjunction with the accompanying drawings, the present invention may be better understood according to the following detailed description.It should be emphasized that
, according to the standard practices in industry, various parts are not necessarily to scale and are intended solely for illustrative purposes.Actual
On, for the sake of clear discussion, the size of various parts can be arbitrarily increased or reduced.
Fig. 1 is the stream illustrating to manufacture the method for source/drain structures of semiconductor device according to various aspects of the invention
Cheng Tu；And
Fig. 2 to Figure 12 is the semiconductor device of the inclusion source/drain structures according to each embodiment of the present invention in difference
The sectional view of fabrication stage.
Specific embodiment
It should be appreciated that for the different characteristic realizing the present invention, the following disclosure provides many different embodiments or reality
Example.The instantiation the following describing part with arrangement is to simplify the present invention.Certainly these are only example but are not intended as limiting
The present invention processed.For example, in below describing, first component is formed at the above or over of second component and may include wherein first component
The embodiment being formed with second component directly contact, may also comprise wherein additional part and may be formed at first component and second
So that the embodiment that is not directly contacted with of first component and second component between part.In addition, the present invention may weigh in various embodiments
Multiple reference number and/or letter.This repeat to be intended merely to simple and clear and clearly purpose, but itself be not intended that and discussed
Relation between each embodiment and/or structure.
With reference to Fig. 1, show the source/drain manufacturing semiconductor device according to various aspects of the invention（S/D）Structure
Method 100 flow chart.Method 100 starts from step 102, wherein, provides the substrate including first type surface.Method 100 continues
To step 104, wherein, form shallow trench isolation in substrate（STI）Area.Method 100 continues to 106, wherein, in substrate
First type surface on form the gate stack adjacent with STI region.Method 100 continues to 108, wherein, is formed and grid pile
The adjacent distance piece in the side of overlapping piece.
Method 100 continues to 110, wherein, makes substrate recessed to form the S/D groove adjacent with distance piece.Method
100 continue to 112, wherein, at the first temperature, so that the surface of S/D groove is exposed to including XeF2、NH3And H2Steam
Mixture.Method 100 continues to 114, and wherein, heating substrate is prolonged to higher second temperature with being formed at below distance piece
The S/D chamber stretched.Method 100 continues to 116, and wherein, selective growth S/D extension makes it be partially fill in S/D chamber.
Method 100 proceeds step 118, and wherein, selective growth is filled in the strain gauge material in S/D chamber.Discussion below explanation
The embodiment of the semiconductor device that can be manufactured according to the method 100 of Fig. 1.
Fig. 2 to Figure 12 is the inclusion source/drain according to each embodiment of the present invention（S/D）The semiconductor device of structure 250
Part 200 is in the sectional view of different fabrication stages.As used in the present invention, term semiconductor device 200 represents fin field effect
Transistor（FinFET）200.FinFET 200 refers to any multi-gated transistor based on fin.In certain embodiments, term
Semiconductor device 200 represents planar MOSFETs effect transistor（MOSFET）.Other transistor arrangements and
Similar structures are all in the desired extent of the present invention.Semiconductor device 200 can include microprocessor, memory cell and/
Or other integrated circuits（IC）In.
It should be noted that in certain embodiments, the operation mentioned in execution Fig. 1 can not produce complete quasiconductor
Device 200.Complementary metal oxide semiconductors (CMOS) can be used（CMOS）Technology is processed and to be manufactured complete semiconductor device 200.Cause
This it will be appreciated that additional technique can be provided before, during and/or after the method 100 of Fig. 1, and in the present invention only
It is to schematically illustrate some techniques other.And, simplify Fig. 2 to Figure 12 to be better understood from idea of the invention.For example, to the greatest extent
Pipe accompanying drawing show semiconductor device 200 but it is to be understood that IC may include multiple inclusion resistors, inducer, capacitor,
Other devices of fuse etc..
With reference to the step 102 in Fig. 2 and Fig. 1, provide the substrate 202 including first type surface 202s.In at least one embodiment
In, substrate 202 includes crystalline silicon substrate（For example, wafer）.According to design requirement, substrate 202 can include various doped regions（Example
As, p-substrate or n-type substrate）.In certain embodiments, doped region can be doped with p-type or n-type dopant.For example, adulterate
Area can be doped with such as boron or BF2The n-type dopant of p-type dopant, such as phosphorus or arsenic and/or combinations thereof.Doping
Area can be configurable for N-shaped FinFET, or is optionally configured to for p-type FinFET.
In certain embodiments, substrate 202 can be by some other suitable elemental semiconductor（Such as diamond or germanium）、
Suitable compound semiconductor（Such as GaAs, carborundum, indium arsenide or indium phosphide）Or suitable alloy semiconductor（Such as silicon
Carbonization germanium, gallium arsenide phosphide or InGaP）Make.Additionally, substrate 202 can include epitaxial layer（epi-layer）, it can produce
Strain is so that performance enhancement and/or may include silicon-on-insulator（SOI）Structure.
In one embodiment, soldering pad layer 204a and mask layer are formed on the first type surface 202s of Semiconductor substrate 202
204b.Soldering pad layer 204a can be the thin film including the silicon oxide being formed using thermal oxidation technology.Soldering pad layer 204a can be used as half
Adhesive layer between conductor substrate 202 and mask layer 204b.Soldering pad layer 204a also acts as etching during etching mask layer 204b
Stop-layer.In one embodiment, for example, using low-pressure chemical vapor deposition（LPCVD）Or plasma enhanced chemical vapour phase
Deposition（PECVD）Mask layer 204b is formed by silicon nitride.Mask layer 204b is used as hard mask in follow-up photoetching process.Covering
Form photosensitive layer 206 in mold layer 204b, so that it is patterned, thus forming opening 208 in photosensitive layer 206.
As described in step 104 in Fig. 3 to Fig. 5 and Fig. 1, in order to form shallow trench isolation in substrate 202（STI）218th area,
Produce the structure in Fig. 3 by forming fin 212 in substrate 202.Come etching mask layer 204b and soldering pad layer through opening 208
204a is to expose following Semiconductor substrate 202.Then the Semiconductor substrate etching exposure is to form less than Semiconductor substrate 202
First type surface 202s groove 210.In the described embodiment, for the sake of simplicity, the part semiconductor between groove 210
Substrate 202 forms a semiconductor fin 212.In certain embodiments, FinFET 200 can include more than one fin, for example,
Three fins or five fins.In the described embodiment, semiconductor fin 212 includes top 212u and bottom 212l（Divided with dotted line
Every）.In certain embodiments, top 212u and bottom 212l includes the identical material of such as silicon.Then remove photosensitive layer
206.Next, implementing cleaning to remove the native oxide of Semiconductor substrate 202.Can be using the hydrogen fluorine of dilution（DHF）Acid
To be carried out.
Then can in groove 210 selectively formed cushion oxide layer（Not shown）.In one embodiment, liner oxidation
Layer can be thickness between aboutTo aboutBetween thermal oxide layer.In certain embodiments, it is possible to use steam in situ
Vapour generates（ISSG）Deng formation cushion oxide layer.The cushion oxide layer being formed makes the turning sphering of groove 210, thus reducing electricity
, and therefore improve the performance of the integrated circuit of generation.
Fig. 4 shows deposition of dielectric materials 214, is then chemically-mechanicapolish polished（CMP）The structure being formed after technique.
Groove 210 is filled with dielectric material 214.Dielectric material 214 can include silicon oxide, therefore also referred to as aoxidizes in the present invention
Thing 214.In certain embodiments, it is possible to use other dielectric materials, such as silicon nitride, silicon oxynitride, fluorine doped silicate glass
（FSG）Or low k dielectric.In certain embodiments, can be by silane（SiH4）And oxygen（O2）As reacting precursor, use
High-density plasma（HDP）CVD technique forms oxide 214.In other embodiments, it is possible to use sub-atmospheric pressure CVD
（SACVD）Technique or high-aspect-ratio technique（HARP）Form oxide 214, wherein, process gas can include tetraethoxy-silicane
Alkane（TEOS）And ozone（O3）.In other embodiments, it is possible to use spin-on-dielectric（SOD）Technique（Such as hydrogen silsesquioxane
Alkane（HSQ）Or methyl silsesquioxane（MSQ））Form oxide 214.
In certain embodiments, after the cmp process, remove mask layer 204b and soldering pad layer 204a.In an embodiment
In, mask layer 204b is formed by silicon nitride, can utilize hot H using wet processing3PO4Remove mask layer 204b, and if weld pad
Layer 204a is formed by silicon oxide, then can remove weld layer 204a with the HF acid of dilution.In certain embodiments, oxygen can be made
Mask layer 204b and soldering pad layer 204a is removed, wherein recessed step figure 5 illustrates after compound 214 is recessed.
In certain embodiments, to replace the top 212u of fin 212 to improve device performance with other semi-conducting materials.Will
Oxide 214 is used as hard mask, makes the top 212u of fin 212 recessed by etching step.Then, epitaxial growth such as Ge is not
With material to fill recess.In the described embodiment, fin 212 includes different materials, and the top 212u of fin 212 is all
As the material of Ge, the bottom 212l of fin 212 is the material of such as Si.
After removing mask layer 204b and soldering pad layer 204a, make by etching step that oxide 214 is recessed to expose fin
212 top 212u, thus generate groove 216 and remaining oxide 214（Shown in Fig. 5）.Below by the oxygen in groove 210
The remainder of compound 214 is referred to as STI region 218.In one embodiment, it is possible to use wet etching process walks to implement to etch
Suddenly, for example, by substrate 202 is immersed in Fluohydric acid.（HF）In.In another embodiment, it is possible to use dry etching process comes real
Apply etching step, for example, it is possible to by CHF3Or BF3To implement dry etching process as etching gas.
In the described embodiment, the top 212u of fin 212 extends downward STI region 218 from substrate main surface 202s
Surface 218s, has the first height H1.First height H1 can be between 15nm to about 50nm, although it is likely to more greatly or more
Little.In the described embodiment, top 212u includes source/drain（S/D）Part and the groove being located between S/D part
Point.Raceway groove part is used for forming the channel region of semiconductor device 200.
With reference to the step 106 in Fig. 6 and Fig. 1, after forming STI region 218 in substrate 202, by the master in substrate 202
Form the gate stack 220 adjacent with STI region 218 on the 202s of surface and generate the structure in Fig. 6.Thus, STI region 218a position
In the side of gate stack 220, and STI region 218b is located at the opposite side of gate stack 220.In certain embodiments, grid
The gate electrode layer 224 that pole stack 220 includes gate dielectric 222 and is located at gate dielectric 222 top.
As shown in fig. 6, forming gate dielectric 222 to cover the raceway groove part of top 212u.In certain embodiments, grid
Pole dielectric layer 222 may include silicon oxide, silicon nitride, silicon oxynitride or high k dielectric.High k dielectric comprises metal-oxide.With
Make the metal-oxide of high k dielectric example include Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm,
The oxide of Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and their mixture.In the present embodiment, gate dielectric 222 is
Thickness is between aboutTo aboutBetween high k dielectric layer.Can be using suitable technique（Such as ald
（ALD）, chemical vapor deposition（CVD）, physical vapor deposition（PVD）, thermal oxide, UV ozone oxidation or combinations thereof）Carry out shape
Become gate dielectric 222.Gate dielectric 222 also includes boundary layer（Not shown）To reduce gate dielectric 222 and top
The groove of 212u divide between damage.Boundary layer can include silicon oxide.
Then, gate electrode layer 224 is formed on gate dielectric 222.In certain embodiments, gate electrode layer 224 is permissible
Including single or multiple lift structure.In certain embodiments, gate electrode layer 224 can include polysilicon and non-crystalline silicon.Real at some
Apply in example, gate electrode layer 224 can include metal（Such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi,
CoSi）, other conductive materials of matching of work function and backing material or combinations thereof.In the present embodiment, gate electrode layer
224 thickness is between about 60nm to about 100nm.Can be suitable using such as ALD, CVD, PVD, plating or combinations thereof
Technique is forming gate electrode layer 224.
So far, processing step provides the substrate 202 on the first type surface 202s of substrate 202 with gate stack 220.
Generally, it is possible to use lightly doped drain（LDD）Inject and to change the S/D dopant profiles of S/D structure.By introducing LDD region domain
（That is, S/D extension）, reduce the peak electric field in space-charge region and make to puncture and be minimized with thermoelectronic effect.So
And, the non-uniform doping agent distribution of the S/D extension on the top surface and side wall of fin 212 causes such as punch-through effect and leakage
FinFET characteristic fluctuation, thus reducing the performance of device.
Therefore, the S/D that can be formed including having Uniform Doped agent distribution below with reference to the process that Fig. 7 to Figure 12 is discussed prolongs
The S/D structure stretching part is to replace the LDD region domain with non-uniform doping agent distribution（That is, S/D extension）.Can avoid by S/D
The non-uniform doping agent of extension is distributed the relevant problem of the fluctuation with FinFET characteristic causing.Therefore, the method for applicant
The Performance Characteristics of device, such as punch-through effect and leakage can be realized.
As shown in the step 108 of Fig. 7 and Fig. 1, in order to manufacture the S/ of the Uniform Doped agent distribution with semiconductor device 200
D extension（All S/D extensions 230 as is illustrated by figs. 11 and 12）, adjacent with the side of gate stack 220 by being formed
Distance piece 226（Step 108 in Fig. 1）To generate the structure in Fig. 7.In certain embodiments, distance piece 226 may include oxidation
Silicon, silicon nitride, silicon oxynitride or other suitable material.Distance piece 226 can include single or multiple lift structure.Reality in description
Apply in example, the covering of dielectric layer can be formed by CVD, PVD, ALD or other suitable technology above gate stack 220
Layer.Then, dielectric layer is implemented with anisotropic etching to form a pair of distance piece 226 in the both sides of gate stack 220.Distance piece
226 include first thickness t between about 5nm to about 15nm for the thickness range1.In certain embodiments, only in gate stack
The side of part 220 forms distance piece 226, thus generating dissymmetrical structure.
With reference to the step 110 in Fig. 8 and Fig. 1, formed the distance piece 226 adjacent with the side of gate stack 220 it
Afterwards, generate the structure in Fig. 8 by making substrate 202 recess for forming the S/D groove 228 adjacent with distance piece 226.By grid
Stack 220 and a pair of distance piece 226 are used as hard mask, implement anisortopicpiston and etch so that not being subject in the 212u of top
Protection or the S/D exposing are partially recessed, thus in first type surface 202s S/D formed below groove 228.In certain embodiments,
Can will be selected from Cl2、HBr、NF3、CF4And SF6Chemical substance be used as etching gas implementing etch process.The skill of this area
Art personnel will appreciate that by forming symmetrical junction as shown in Figure 8 in the both sides of gate stack 220 formation gate spacer
Structure.In other embodiments, unsymmetric structure can be formed by only forming gate spacer in the side of gate stack 220.
All these embodiments are all in the desired extent of the present invention.
The CMOS technology step being subsequently applied to the semiconductor device 200 of Fig. 8 includes being formed at distance piece 226 lower section extension
S/D extension 230（Referring to Figure 12）To provide the electrical contact with the channel region of semiconductor device 200.As Fig. 9 to Figure 11 and Tu
Step 112 in 1 to shown in 116, after forming the S/D groove 228 adjacent with distance piece 226, by vapour phase etch process
Substrate 202 is made to recess for forming the S/D chamber 236 extending below distance piece 226 further（Referring to Figure 10）, hereinafter can be to this
Make and more explaining in detail.
Vapour phase etch process starts from the structure of Fig. 8 is incorporated into the reative cell of sealing, and wherein vapour phase etch process uses
Vapor phase reactant.Etch process is isotropism and self limiting, because the quantity of material removing depends on stoping vapour-phase reaction
The threshold value of the non volatile etch by-product of any further chemical reaction between the exposed surface of thing and S/D groove is thick
Degree.In certain embodiments, the vapour phase etch process adopting in the present invention is included at the first temperature by the table of S/D groove 228
Face is exposed to including XeF2、NH3And H2Steam mixture 232a（Step 112 in Fig. 1）.
Although response mechanism does not affect scope of the claims, it should be appreciated that vapour phase etch process is multi-step
Technique.As Fig. 9 schematically shows, for first step, can in the reaction chamber, the surface of S/D groove 228,
The surface of the surface of gate electrode layer 224 and the dielectric medium including distance piece 226 and STI region 218 forms and includes
XeF2、NH3And H2Vapour mixture 232a blanket adsorption reaction thing film 232b.In certain embodiments, in pressure between about
Between 10mTorr to about 25mTorr and the first temperature is implemented to utilize steam under conditions of about 20 DEG C to about 100 DEG C
The first step of thing 232a.
For second step, the reactant film 232b of absorption can be with the exposed surface of the recessed substrate 202 being in contact with it（That is,
The top surface of S/D groove 228）React, thus the reactant film 232b in absorption（As shown in Figure 9）Thickened solid formed below
Product 234.Additionally, the reactant film 232b of absorption can seldom or not with the grid being disposed below and be in contact with it
The surface of electrode layer 224, distance piece 226 and sti region 218 reacts.
Next, being formed at, by substrate 202 is heated to higher second temperature, the S/ that distance piece 226 lower section extends
D chamber 236（Step 114 in Fig. 1）Thus generating the structure of Figure 10.In certain embodiments, substrate 202 can be heated to more
The high second temperature between about 120 DEG C to about 200 DEG C, can extract solid reaction product 234 from reative cell out simultaneously
Sublimate with the reactant film 232b of absorption.In certain embodiments, can by substrate 202 be heated to higher between about
Second temperature between 120 DEG C to about 200 DEG C, makes carrier gas just flow on the substrate 202 to remove solid from reative cell simultaneously
The sublimate of the reactant film 232b of product 234 and absorption.Carrier gas can be any noble gases.In some embodiments
In, carrier gas includes N2, He or Ar.
In certain embodiments, substrate 202 can be transferred in the chamber of heating, this chamber is heated to higher
The second temperature between about 120 DEG C to about 200 DEG C, simultaneously can from through heating chamber extract out solid reaction produce
The sublimate of the reactant film 232b of thing 234 and absorption.In certain embodiments, substrate 202 can be transferred to through heating
Chamber in, this chamber is heated to the higher second temperature between about 120 DEG C to about 200 DEG C, so that carrier gas is existed simultaneously
Substrate 202 top flowing is with the reactant film 232b of removal solid reaction product 234 and absorption from the chamber through heating
Sublimate.Carrier gas can be any noble gases.In certain embodiments, carrier gas includes N2, He or Ar.
Reaction proceeds, until eliminating solid reaction product 234 and adsorption reaction thing film 232b.Vapour mixture
The substrate 202 that 232a etching exposes, so that the little part in gate electrode layer 224, distance piece 226 and sti region 218 is gone
Remove or do not remove.Therefore, at the end of vapour phase etch process, vapour phase etch process can remove the expose portion of substrate 202 with shape
Become below distance piece 226（And below first type surface 202s）The S/D chamber 236 extending.In other words, chamber 236 is included at interval
The part that part 226 lower section extends.In certain embodiments, S/D chamber 236 includes the part extending below gate stack 220
（Not shown）.In certain embodiments, between the first type surface 202s and the lower surface 236b in chamber 236 of substrate 202 second is high
Degree H2Between about 30nm to about 60nm.In certain embodiments, the second height H2More than the first height H1.
With reference to the step 116 in Figure 11 and Fig. 1, after being formed at the S/D chamber 236 extending below distance piece 226, pass through
Selective growth S/D extension 230 and make it be partially filled with S/D chamber 236, thus generating the structure in Figure 11, wherein, S/D
Extension 230 includes extending and be substantially perpendicular to the part of first type surface 202s below distance piece 226.In some embodiments
In, second thickness t of S/D extension 2302First thickness t less than or equal to distance piece 2261.In certain embodiments, second
Thickness t2With first thickness t1Ratio between 0.1 to 1.
In the embodiment that some are directed to N-shaped FinFET, N_S/D extension 230 includes SiP or SiCP.Reality in description
Apply in example, pre-cleaning processes can be implemented to clean S/D chamber 236 with HF or other suitable solution.Then, by LPCVD
Technique carrys out the N_S/D extension 230 of selective growth such as SiCP to be partially filled with S/D chamber 236.In the described embodiment,
Between temperature is between about 400 DEG C to 800 DEG C and pressure between about 1Torr to 15Torr between under conditions of, by SiH4、
CH3SiH3、PH3And H2To implement LPCVD technique as reacting gas.Adjust pH3Partial pressure can control the phosphorus of N_S/D extension 230
Doping content.In certain embodiments, N_S/D extension 230 includes scope between about 5 × 1019To 8 × 1020atoms/cm3It
Between the first active phosphorus doping density.
Compared with the LDD region domain of injection, the N_S/D extension 230 with more high activity concentration of dopant can provide relatively
Low resistance.Additionally, the N_S/D extension 230 with Uniform Doped agent distribution can reduce the fluctuation of the characteristic of FinFET.Cause
This, the method for applicant can realize the Performance Characteristics of device, such as punch-through effect and leakage.
In the embodiment that some are directed to p-type FinFET, P_S/D extension 230 includes SiGeB.Embodiment in description
In, pre-cleaning processes can be implemented to clean S/D chamber 236 with HF or other suitable solution.Then, by LPCVD technique
The P_S/D extension 230 of selective growth such as SiGeB is to be partially filled with S/D chamber 236.In one embodiment, it is situated between in temperature
Between about 400 DEG C to about 800 DEG C and pressure between about 1Torr to about 200Torr between under conditions of, by SiH2Cl2、
SiH4、GeH4、HCl、B2H6And H2To implement LPCVD technique as reacting gas.Adjust B2H6Partial pressure can control P_S/D extension
230 boron doping concentration.In certain embodiments, P_S/D extension 230 includes scope between about 5 × 1019To 2 ×
1020atoms/cm3Between the first active boron doping concentration.
Compared with the LDD region domain of injection, P_S/D extension 230 can provide higher stress to channel region.Additionally,
Have Uniform Doped agent distribution P_S/D extension 230 can reduce FinFET characteristic fluctuation.Therefore, the side of applicant
Method can realize the Performance Characteristics of device, such as punch-through effect and leakage.
With reference to the step 118 in Figure 12 and Fig. 1, after forming S/D extension 230 in S/D chamber 236, by selectivity
Grow the strain gauge material 240 being filled in S/D chamber 236 to generate the structure in Figure 12, wherein, the lattice of strain gauge material 240 is normal
Number is different from the lattice paprmeter of substrate 202.In the described embodiment, strain gauge material 240 is on the first type surface 202s of substrate 202
Fang Yanshen, although it may coplanar with first type surface 202s or be less than first type surface 202s.In other words, strain gauge material 240 is not in lining
Extend above the first type surface 202s at bottom 202.
In the embodiment that some are directed to N-shaped FinFET, N_ strain gauge material 240 includes SiP or SiCP.Enforcement in description
In example, S/D chamber 236 can be partially filled with by the N_ strain gauge material 240 that LPCVD process selectivity grows such as SiCP.?
In the embodiment of description, in temperature, between about 400 DEG C to 800 DEG C and pressure is between about 1Torr to 100Torr
Under the conditions of, by SiH4、CH4、PH3And H2To implement LPCVD technique as reacting gas.Adjust PH3Partial pressure can control N_ strain material
The phosphorus doping density of material 240.In certain embodiments, N_ strain gauge material 240 includes scope between about 1 × 1018To 3 ×
1021atoms/cm3Between the second phosphorus doping density.
In the embodiment that some are directed to p-type FinFET, P_ strain gauge material 240 includes SiGeB.Embodiment in description
In, the P_ strain gauge material 240 that can selectively grow such as SiGeB by LPCVD technique is partially filled with S/D chamber 236.?
In one embodiment, in temperature, between about 400 DEG C to about 800 DEG C and pressure is between about 1Torr to about 200Torr
Under conditions of, by SiH2Cl2、SiH4、GeH4、HCl、B2H6And H2To implement LPCVD technique as reacting gas.Adjust B2H6Point
The boron doping concentration of the controllable P_ strain gauge material 240 of pressure.In certain embodiments, P_ strain gauge material 240 includes scope between about 1
×1018To 1 × 1021atoms/cm3Between the second boron doping concentration.
In certain embodiments, S/D extension 230 and 240 groups of strain gauge material are collectively referred to as S/D structure 250.Real at some
Apply in example, S/D structure 250 is distributed between gate stack 220 and sti region 218.In certain embodiments, S/D extension
230 are arranged between substrate 202 and strain gauge material 240.In certain embodiments, the first doping content of S/D extension 230 is little
The second doping content in strain gauge material 240.In certain embodiments, the first doping content and the ratio of the second doping content are situated between
Between 0.01 to 0.1.
After step shown in Fig. 1 completes, by further describing of example shown in Fig. 2 to Figure 12, generally can be real
Apply the manufacture to complete semiconductor device 200 of subsequent technique including interconnection process.
According to an embodiment, a kind of field-effect transistor includes：Substrate, including first type surface with below first type surface
Chamber；Gate stack on the first type surface of substrate；The distance piece adjacent with the side of gate stack；It is arranged on grid pile
The shallow trench isolation of overlapping piece side（STI）Area, wherein sti region are located in substrate；Be distributed in gate stack and sti region it
Between source/drain（S/D）Structure, wherein S/D structure include the strain gauge material in chamber, and the lattice of strain gauge material is normal
Number is different from the lattice paprmeter of substrate；And it is arranged on S/D extension between substrate and strain gauge material, wherein, S/D extension
Including the part extending and being substantially perpendicular to first type surface below distance piece.
According to another embodiment, a kind of method of manufacture field-effect transistor includes：The substrate including first type surface is provided；
Form shallow trench isolation in substrate（STI）Area；The gate stack adjacent with sti region is formed on the first type surface of substrate；
Form the distance piece adjacent with the side of gate stack；Make substrate recessed to form the source/drain adjacent with distance piece（S/
D）Groove；At the first temperature, S/D groove is exposed to including XeF2、NH3And H2Vapour mixture；By silicon to more
High second temperature is to be formed at the S/D chamber extending below distance piece；Selective growth S/D extension is to be partially filled with S/D chamber；
And selective growth strain gauge material is to fill S/D chamber.
Although describe the present invention by way of example and according to preferred embodiment, it should be understood that the invention is not restricted to
Disclosed embodiment.On the contrary, the invention is intended to covering various modifications and similar arrangement（Those of ordinary skill in the art are come
Say it is obvious）.Therefore, scope of the following claims should be shown with broadest interpretation one and cover all these and repair
Change and similar arrangement.
Claims (19)
1. a kind of field-effect transistor, including：
Substrate, the chamber including first type surface and below described first type surface；
Gate stack, on the first type surface of described substrate；
Distance piece is adjacent with least side of described gate stack；
Shallow trench isolates (STI) region, is arranged on the side of described gate stack, and described shallow plough groove isolation area is located at described
In substrate；And
Source/drain (S/D) structure, is distributed between described gate stack and described shallow plough groove isolation area, and described source electrode/
Drain electrode structure includes：
Strain gauge material, in described chamber, the lattice paprmeter of described strain gauge material is different from the lattice paprmeter of described substrate；With
Source/drain extension, is arranged between described substrate and described strain gauge material, and described source/drain extension includes
Extend below described distance piece but do not extend and the part perpendicular to described first type surface below described gate stack.
2. field-effect transistor according to claim 1, wherein, described chamber includes the portion extending below described distance piece
Point.
3. field-effect transistor according to claim 1, wherein, between the bottom surface in the first type surface of described substrate and described chamber
Height between 30nm to 60nm.
4. field-effect transistor according to claim 1, wherein, the second thickness of described source/drain extension is less than
Or it is equal to the first thickness of described distance piece.
5. field-effect transistor according to claim 4, wherein, described second thickness is situated between with the ratio of described first thickness
Between 0.1 to 1.
6. field-effect transistor according to claim 1, wherein, described source/drain extension includes Si：P、SiC：P
Or SiGe：B.
7. field-effect transistor according to claim 1, wherein, described strain gauge material includes Si：P、SiC：P or SiGe：
B.
8. field-effect transistor according to claim 1, wherein, the first doping content of described source/drain extension
The second doping content less than described strain gauge material.
9. field-effect transistor according to claim 8, wherein, described first doping content and described second doping content
Ratio between 0.01 to 0.1.
10. field-effect transistor according to claim 1, wherein, described strain gauge material is on the first type surface of described substrate
Fang Yanshen.
11. field-effect transistors according to claim 1, wherein, described strain gauge material is not in the first type surface of described substrate
Top extends.
A kind of 12. methods manufacturing field-effect transistor, including：
The substrate including first type surface is provided；
Form shallow trench isolation (STI) region in described substrate；
The gate stack adjacent with described shallow plough groove isolation area is formed on the first type surface of described substrate；
Form the distance piece adjacent with least side of described gate stack；
Make described substrate recessed to form source/drain (S/D) groove adjacent with described distance piece；
At the first temperature, described source/drain groove is exposed to including XeF2、NH3And H2Vapour mixture；
By described silicon to higher second temperature to be formed at the source/drain chamber extending below described distance piece；
Selective growth source/drain extension makes it be partially fill in described source/drain chamber；And
Selective growth is filled in the strain gauge material in described source/drain chamber.
13. methods according to claim 12, wherein, are implemented under conditions of between 20 DEG C and 100 DEG C in temperature
At a temperature of described first, described source/drain groove is exposed to including XeF2、NH3And H2Vapour mixture step.
14. methods according to claim 12, wherein, implementing under conditions of between 120 DEG C and 200 DEG C in temperature will
Described silicon to higher second temperature step.
15. methods according to claim 12, wherein, implement to make described using anisortopicpiston etch process
The recessed step to form source/drain (S/D) groove adjacent with described distance piece of substrate.
16. methods according to claim 12, wherein, implement to select using low-pressure chemical vapor deposition (LPCVD) technique
The selecting property described source/drain extension of growth makes the step that it is partially filled with described source/drain chamber.
17. methods according to claim 16, wherein, described source/drain extension is SiC：P, and be situated between in temperature
Between 400 DEG C and 800 DEG C and pressure between 1Torr and 100Torr between under conditions of, by SiH4、CH4、PH3And H2It is used as
Reacting gas is implementing described low-pressure chemical vapor deposition technique.
18. methods according to claim 16, wherein, described source/drain extension is SiGe：B, and be situated between in temperature
Between 400 DEG C and 800 DEG C and pressure between 1Torr and 200Torr between under conditions of, by SiH2Cl2、SiH4、GeH4、
HCl、B2H6And H2To implement described low-pressure chemical vapor deposition technique as reacting gas.
19. methods according to claim 12, wherein, implement selective growth filling using low-pressure chemical vapor deposition
The step of the strain gauge material in described source/drain chamber.
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| CN104392927B (en) * | 2014-11-19 | 2017-07-11 | 上海华力微电子有限公司 | The method for improving shallow groove isolation edge SiC stress performances |
| US9601574B2 (en) * | 2014-12-29 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | V-shaped epitaxially formed semiconductor layer |
| CN107785261A (en) * | 2016-08-26 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacture method |
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| US7041224B2 (en) * | 1999-10-26 | 2006-05-09 | Reflectivity, Inc. | Method for vapor phase etching of silicon |
| CN102347234A (en) * | 2010-07-29 | 2012-02-08 | 中国科学院微电子研究所 | Structure of semiconductor device and manufacturing method thereof |
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| US7041224B2 (en) * | 1999-10-26 | 2006-05-09 | Reflectivity, Inc. | Method for vapor phase etching of silicon |
| CN102347234A (en) * | 2010-07-29 | 2012-02-08 | 中国科学院微电子研究所 | Structure of semiconductor device and manufacturing method thereof |
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