CN104123249A - Novel dynamic memory SDDR architecture array based on serial access - Google Patents
Novel dynamic memory SDDR architecture array based on serial access Download PDFInfo
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- CN104123249A CN104123249A CN201410349073.1A CN201410349073A CN104123249A CN 104123249 A CN104123249 A CN 104123249A CN 201410349073 A CN201410349073 A CN 201410349073A CN 104123249 A CN104123249 A CN 104123249A
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Abstract
The invention relates to computer storage media, in particular to a novel dynamic memory SDDR architecture array based on serial access. The novel dynamic memory SDDR architecture array based on serial access solves the problem that according to existing computer storage media, further acceleration and capacity expansion are difficult to achieve. The novel dynamic memory SDDR architecture array based on serial access comprises n paths of SDDR memorizers, an SDDR memory array controller and a computer host interface, wherein each path of SDDR memorizer comprises an SDDR controller, m SDDR memorizer nodes, M+1 UN1s and a BoW, each SDDR memorizer node comprises an SDDR memorizer control interface, a DDR controller and a DDR memorizer. The novel dynamic memory SDDR architecture array based on serial access is suitable for computer storage.
Description
Technical field
The present invention relates to computer-readable storage medium, specifically a kind of novel dynamic storage SDDR architecture array of serial access.
Background technology
Under prior art condition, computer-readable storage medium is commonly the computer-readable storage medium based on parallel bus access.Practice shows, this kind of computer-readable storage medium be along with self constantly upgrades, and himself pin is more and more, causes thus it to be difficult to further speed-raising and dilatation, thereby causes it cannot meet more and more higher Computer Storage requirement.Based on this, be necessary to invent a kind of brand-new computer-readable storage medium, be difficult to the problem of further speed-raising and dilatation to solve active computer storage medium.
Summary of the invention
The present invention is difficult to the problem of further speed-raising and dilatation in order to solve active computer storage medium, a kind of novel dynamic storage SDDR architecture array of serial access is provided.
The present invention adopts following technical scheme to realize: a kind of novel dynamic storage SDDR architecture array of serial access, comprises n road SDDR storer, SDDR storage array controllers, computer host interface; Wherein, every road SDDR storer includes 1 SDDR controller, a m SDDR memory node, a m+1 UNI(Unified Node Interface, unified node interface), 1 BoW(Bus only Write, a write bus); Each SDDR memory node includes 1 SDDR storer control interface, 1 DDR controller, 1 DDR storer; M DDR storer and m the DDR controller of every road SDDR storer connect one to one; M DDR controller and m the SDDR storer control interface of every road SDDR storer connect one to one; M SDDR storer control interface of every road SDDR storer connects one to one with m UNI wherein; The SDDR controller of every road SDDR storer is connected with remaining 1 UNI; M+1 UNI of every road SDDR storer is all connected with BoW; The SDDR controller of every road SDDR storer is all connected with SDDR storage array controllers; SDDR storage array controllers is connected with computer host interface; N, m are positive integer.
Specific works process is as follows:
One, SDDR storer is carried out to initialization: computer host interface is sent to initialization command the SDDR controller of n road SDDR storer simultaneously by SDDR storage array controllers.Initialization command is packaged into message bag by SDDR controller, and by BoW, message bag is sent to SDDR storer control interface.Initialization command is resolved and extracted to SDDR storer control interface to message bag, then initialization command is sent to DDR controller.DDR controller carries out initialization according to initialization command to DDR storer;
Two, to SDDR storer data writing: the parallel data stream of 1 n bit is sent to SDDR storage array controllers by computer host interface.SDDR storage array controllers converts the parallel data stream of 1 n bit to the serial data stream of n 1 bit, and the serial data stream of n 1 bit is sent to respectively simultaneously to the SDDR controller of n road SDDR storer.The serial data stream of 11 bit is packaged into message bag by SDDR controller, and by BoW, message bag is sent to the SDDR storer control interface of selected SDDR memory node.SDDR storer control interface resolves and extracts the serial data stream of 11 bit to message bag, then convert the serial data stream of 11 bit to parallel data stream, and parallel data stream is sent to DDR controller.Parallel data stream is write DDR storer by DDR controller;
Three, from SDDR storer sense data: the DDR controller of selected SDDR memory node is read parallel data stream from DDR storer, and parallel data stream is sent to SDDR storer control interface.SDDR storer control interface converts parallel data stream to the serial data stream of 11 bit, and the serial data stream of 11 bit is packaged into message bag, then by BoW, message bag is sent to SDDR controller.The serial data stream of n 1 bit resolved and extracts by the SDDR controller of n road SDDR storer to message bag, then by the serial data stream synchronized transmission of n 1 bit to SDDR storage array controllers.SDDR storage array controllers converts the serial data stream of n 1 bit the parallel data stream of 1 n bit to, and the parallel data stream of 1 n bit is sent to computer host interface.
Based on said process, compared with active computer storage medium, the novel dynamic storage SDDR architecture array of a kind of serial access of the present invention is no longer accessed based on parallel bus, but access based on serial BoW, even if therefore DDR storer self pin is more and more, SDDR still can further raise speed and dilatation, thereby has met more and more higher Computer Storage requirement completely.
The present invention is rational in infrastructure, it is ingenious to design, and efficiently solves the problem that active computer storage medium is difficult to further speed-raising and dilatation, is applicable to Computer Storage.
Brief description of the drawings
Fig. 1 is structural representation of the present invention.
Fig. 2 is the structural representation of SDDR memory node of the present invention.
Embodiment
A novel dynamic storage SDDR architecture array for serial access, comprises n road SDDR storer, SDDR storage array controllers, computer host interface;
Wherein, every road SDDR storer includes 1 SDDR controller, a m SDDR memory node, a m+1 UNI, 1 BoW;
Each SDDR memory node includes 1 SDDR storer control interface, 1 DDR controller, 1 DDR storer;
M DDR storer and m the DDR controller of every road SDDR storer connect one to one;
M DDR controller and m the SDDR storer control interface of every road SDDR storer connect one to one;
M SDDR storer control interface of every road SDDR storer connects one to one with m UNI wherein;
The SDDR controller of every road SDDR storer is connected with remaining 1 UNI;
M+1 UNI of every road SDDR storer is all connected with BoW;
The SDDR controller of every road SDDR storer is all connected with SDDR storage array controllers;
SDDR storage array controllers is connected with computer host interface;
N, m are positive integer.
When concrete enforcement, described DDR storer is DDR storer or DDR2 storer or DDR3 storer or DDR4 storer; Described DDR controller is DDR controller or DDR2 controller or DDR3 controller or DDR4 controller.
Claims (2)
1. a novel dynamic storage SDDR architecture array for serial access, is characterized in that: comprise n road SDDR storer, SDDR storage array controllers, computer host interface;
Wherein, every road SDDR storer includes 1 SDDR controller, a m SDDR memory node, a m+1 UNI, 1 BoW;
Each SDDR memory node includes 1 SDDR storer control interface, 1 DDR controller, 1 DDR storer;
M DDR storer and m the DDR controller of every road SDDR storer connect one to one;
M DDR controller and m the SDDR storer control interface of every road SDDR storer connect one to one;
M SDDR storer control interface of every road SDDR storer connects one to one with m UNI wherein;
The SDDR controller of every road SDDR storer is connected with remaining 1 UNI;
M+1 UNI of every road SDDR storer is all connected with BoW;
The SDDR controller of every road SDDR storer is all connected with SDDR storage array controllers;
SDDR storage array controllers is connected with computer host interface;
N, m are positive integer.
2. the novel dynamic storage SDDR architecture array of a kind of serial access according to claim 1, is characterized in that: described DDR storer is DDR storer or DDR2 storer or DDR3 storer or DDR4 storer; Described DDR controller is DDR controller or DDR2 controller or DDR3 controller or DDR4 controller.
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| CN201410349073.1A CN104123249B (en) | 2014-07-22 | 2014-07-22 | A kind of new dynamic memory SDDR architecture arrays of serial access |
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| CN201410349073.1A CN104123249B (en) | 2014-07-22 | 2014-07-22 | A kind of new dynamic memory SDDR architecture arrays of serial access |
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| CN104123249A true CN104123249A (en) | 2014-10-29 |
| CN104123249B CN104123249B (en) | 2018-03-09 |
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| CN102272745A (en) * | 2009-01-08 | 2011-12-07 | 美光科技公司 | Memory system controller |
| CN102521200A (en) * | 2011-12-13 | 2012-06-27 | 四川赛狄信息技术有限公司 | System for configuring multi-processor in single Flash in embedded manner |
| CN103049397A (en) * | 2012-12-20 | 2013-04-17 | 中国科学院上海微系统与信息技术研究所 | Method and system for internal cache management of solid state disk based on novel memory |
| CN103136162A (en) * | 2013-03-07 | 2013-06-05 | 太原理工大学 | ASIC (application specific integrated circuit) on-chip cloud architecture and design method based on same |
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Patent Citations (7)
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| US20080209112A1 (en) * | 1999-08-04 | 2008-08-28 | Super Talent Electronics, Inc. | High Endurance Non-Volatile Memory Devices |
| US20080162861A1 (en) * | 2004-03-08 | 2008-07-03 | Micron Technology, Inc. | Memory hub architecture having programmable lane widths |
| CN102272745A (en) * | 2009-01-08 | 2011-12-07 | 美光科技公司 | Memory system controller |
| CN102012791A (en) * | 2010-10-15 | 2011-04-13 | 中国人民解放军国防科学技术大学 | Flash based PCIE (peripheral component interface express) board for data storage |
| CN102521200A (en) * | 2011-12-13 | 2012-06-27 | 四川赛狄信息技术有限公司 | System for configuring multi-processor in single Flash in embedded manner |
| CN103049397A (en) * | 2012-12-20 | 2013-04-17 | 中国科学院上海微系统与信息技术研究所 | Method and system for internal cache management of solid state disk based on novel memory |
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