CN104157696A - Thin film transistor and preparation method thereof, as well as array baseplate and liquid crystal display device - Google Patents
Thin film transistor and preparation method thereof, as well as array baseplate and liquid crystal display device Download PDFInfo
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- CN104157696A CN104157696A CN201410340379.0A CN201410340379A CN104157696A CN 104157696 A CN104157696 A CN 104157696A CN 201410340379 A CN201410340379 A CN 201410340379A CN 104157696 A CN104157696 A CN 104157696A
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- 239000010409 thin film Substances 0.000 title claims abstract description 56
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 18
- 230000000903 blocking effect Effects 0.000 claims abstract description 124
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 113
- 238000005516 engineering process Methods 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 100
- 239000000758 substrate Substances 0.000 claims description 44
- 239000010408 film Substances 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000010301 surface-oxidation reaction Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 238
- 238000009825 accumulation Methods 0.000 description 9
- 238000005286 illumination Methods 0.000 description 9
- 230000005684 electric field Effects 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005056 compaction Methods 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
Abstract
The invention provides a thin film transistor and a preparation method thereof, as well as an array baseplate and a liquid crystal display device, relates to the technical field of display, can enable a preparation technology of the thin film transistor to be simpler, and can avoid generating photoinduced leakage current and hole leakage current. The thin film transistor comprises a gate electrode, an amorphous silicon layer and an ohmic contact layer which are arranged on an underlay baseplate in sequence; the size of the gate electrode is smaller than that of the amorphous silicon layer; on the basis, the thin film transistor further comprises a light blocking layer which is arranged between the amorphous silicon layer and the underlay baseplate, corresponding to the rest part, not being blocked by the gate electrode, of the amorphous silicon layer, and beyond the amorphous silicon layer. The invention is used for designing and manufacturing the thin film transistor, the array baseplate comprising the thin film transistor, and the liquid crystal display device comprising the array baseplate.
Description
Technical field
The present invention relates to Display Technique field, relate in particular to a kind of thin-film transistor and preparation method, array base palte, liquid crystal indicator.
Background technology
(the Thin Film Transistor of thin-film transistor in liquid crystal indicator, abbreviation TFT) leakage current can produce serious influence to the characteristic of thin-film transistor, therefore the leakage current that, all the time how to reduce thin-film transistor is the problem that those skilled in the art study.
As shown in Figure 1, 2, 3, thin-film transistor 10 can comprise grid 101, gate insulation layer 102, amorphous silicon layer 103, ohmic contact layer 104 (n+ amorphous silicon layer) and source electrode 105 and the drain electrode 106 being arranged on underlay substrate 100.
The structure of the thin-film transistor 10 of ideal type as shown in Figure 1, wherein, the consistent size of grid 101 and amorphous silicon layer 103.Like this, on the one hand, when this thin-film transistor 10 is applied to array base palte, when this array base palte is applied to liquid crystal indicator, opaque grid 101 can prevent that bottom backlight from irradiating amorphous silicon layer 103 and producing photic leakage current, on the other hand, overlapping region at grid 101 with source electrode 105 and drain electrode 106, hole accumulation layer in amorphous silicon layer 103 and ohmic contact layer 104 form PN junction, can prevent hole in the accumulation layer of hole from flowing in the hole accumulation layer that electronics in source electrode 105 and drain electrode 106 or in source electrode 105 and drain electrode 106 flows into amorphous silicon layer 103 and produce hole leakage current.
Yet, in actual process, tend to occur situation as shown in Figures 2 and 3.Wherein, Figure 2 shows that grid 101 sizes are less than the situation of amorphous silicon layer 103 sizes, because grid 101 can not block amorphous silicon layer 103 completely, can cause arriving amorphous silicon layer 103 from the illumination of bottom backlight, thereby produce photic leakage current.Be illustrated in figure 3 the situation that grid 101 sizes are greater than amorphous silicon layer 103 sizes, because grid 101 still has overlapping with source electrode 105 and drain electrode 106 in the part that exceeds amorphous silicon layer 103, and in this overlapping region, between grid 101 and source electrode 105 and drain electrode 10, be only provided with gate insulation layer 102 and source electrode 105 and drain and 106 directly contact with amorphous silicon layer 103, make between hole accumulation layer in amorphous silicon layer 103 and source electrode 105 and drain electrode 106 owing to not having the electronics that causes hole to flow in source electrode 105 and drain electrode 106 or in source electrode 105 and drain electrode 106 of PN junction to flow in the hole accumulation layer of amorphous silicon layer 103, produce hole leakage current.
Summary of the invention
Embodiments of the invention provide a kind of thin-film transistor and preparation method, array base palte, liquid crystal indicator, can make the preparation technology of thin-film transistor more simple, and can avoid the generation of photic leakage current and hole leakage current.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, provide a kind of thin-film transistor, comprise the grid, amorphous silicon layer and the ohmic contact layer that are successively set on underlay substrate, the size of described grid is less than the size of described amorphous silicon layer; On this basis, described thin-film transistor also comprises: be arranged on the light blocking layer between described amorphous silicon layer and described underlay substrate, the remainder of described light blocking layer and the amorphous silicon layer not blocked by described grid is corresponding and exceed described amorphous silicon layer.
Preferably, described light blocking layer is arranged between described underlay substrate and described grid, and described light blocking layer is also corresponding with described grid.
Further, the material of described light blocking layer is opaque resin.
Preferably, described light blocking layer and described grid with layer and be integrated; Wherein, described light blocking layer obtains for after described grid material is oxidized away from the surperficial material of described underlay substrate, and the material of the remainder of described light blocking layer is identical with described grid material.
On the other hand, also provide a kind of array base palte, comprise the thin-film transistor described in above-mentioned any one.
On the one hand, also provide a kind of liquid crystal indicator again, comprise above-mentioned array base palte.
Another aspect, also provides a kind of preparation method of thin-film transistor, is included on underlay substrate and forms successively grid, amorphous silicon layer and ohmic contact layer, and the size of described grid is less than the size of described amorphous silicon layer; On this basis, described method also comprises: between described amorphous silicon layer and described underlay substrate, form light blocking layer, the remainder of described light blocking layer and the amorphous silicon layer not blocked by described grid is corresponding and exceed described amorphous silicon layer.
Preferably, described light blocking layer is formed between described underlay substrate and described grid, and described light blocking layer is also corresponding with described grid.
Further, the material of described light blocking layer is opaque resin; On this basis, form described grid, described light blocking layer specifically comprises:
On underlay substrate, form successively light blocking layer film, grid metallic film, and form photoresist on described grid metallic film; Adopt normal masks plate to being formed with the base board to explosure of described photoresist, after developing, the formation complete reserve part of photoresist and photoresist are removed part completely; Wherein, the size of the complete reserve part of described photoresist is greater than the size of described grid, and the complete reserve part of described photoresist covers described grid completely, and described photoresist is removed corresponding other regions of part completely; Adopt wet-etching technology pair to remove described grid metallic film corresponding to part completely with described photoresist and carry out etching, form described grid; The complete reserve part of described photoresist of take is mask, adopts dry etch process to carry out etching to described light blocking layer film, forms described light blocking layer; Adopt stripping technology to remove the photoresist of the complete reserve part of described photoresist.
Preferably, described light blocking layer and described grid with layer and be integrated; On this basis, form described grid, described light blocking layer specifically comprises:
On underlay substrate, form grid metallic film, and form photoresist on described grid metallic film; Adopt half rank or gray-tone mask plate to being formed with the base board to explosure of described photoresist, after developing, form the complete reserve part of photoresist, photoresist half reserve part and photoresist and remove part completely; Wherein, the region of the corresponding described grid of the complete reserve part of described photoresist, the region of the corresponding described light blocking layer of described photoresist half reserve part, described photoresist is removed corresponding other regions of part completely; Adopt etching technics to remove the described grid metallic film that described photoresist is removed part completely; Using plasma bombards described photoresist half reserve part, removes the photoresist of described photoresist half reserve part; And adjust plasma parameter, make the surface oxidation of the described grid metallic film corresponding with described photoresist half reserve part form described light blocking layer, the described grid metallic film corresponding with the complete reserve part of described photoresist forms grid, removes the photoresist of the complete reserve part of described photoresist simultaneously.
Embodiments of the invention provide a kind of thin-film transistor and preparation method, array base palte, liquid crystal indicator, this thin-film transistor comprises grid, amorphous silicon layer and the ohmic contact layer being successively set on underlay substrate, and the size of described grid is less than the size of described amorphous silicon layer; On this basis, described thin-film transistor also comprises: be arranged on the light blocking layer between described amorphous silicon layer and described underlay substrate, the remainder of described light blocking layer and the amorphous silicon layer not blocked by described grid is corresponding and exceed described amorphous silicon layer.
Process complexity with respect to the thin-film transistor of the consistent grid of preparation size and amorphous silicon layer, thin-film transistor in the array base palte that the embodiment of the present invention provides, because the size of described grid is less than the size of described amorphous silicon layer, makes preparation technology more simple; On this basis, on the one hand, because the size of described grid is less than the size of described amorphous silicon layer, make the overlapping region in described grid and described source electrode and drain electrode, hole accumulation layer in amorphous silicon layer and ohmic contact layer form PN junction, thereby have avoided the generation of hole leakage current; On the other hand, by described light blocking layer and described grid, share effect, can stop that illumination is mapped to described amorphous silicon layer, thereby avoid the generation of photic leakage current.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation that Fig. 1 is a kind of ideal type thin-film transistor of providing in prior art;
Fig. 2 is less than the structural representation of the thin-film transistor of amorphous silicon layer size for the grid size providing in prior art;
Fig. 3 is greater than the structural representation of the thin-film transistor of amorphous silicon layer size for the grid size providing in prior art;
The structural representation one of a kind of thin-film transistor that Fig. 4 provides for the embodiment of the present invention;
The structural representation two of a kind of thin-film transistor that Fig. 5 provides for the embodiment of the present invention;
The structural representation one of a kind of array base palte that Fig. 6 provides for the embodiment of the present invention;
The structural representation two of a kind of array base palte that Fig. 7 provides for the embodiment of the present invention;
A kind of process schematic diagram one that forms grid and light blocking layer that Fig. 8 a-8e provides for the embodiment of the present invention;
A kind of process schematic diagram two that forms grid and light blocking layer that Fig. 9 a-9d provides for the embodiment of the present invention.
Reference numeral:
10-thin-film transistor; 100-underlay substrate; 101-grid; 101a-grid metallic film; 102-gate insulation layer; 103-amorphous silicon layer; 104-ohmic contact layer; 105-source electrode; 106-drain electrode; 107-light blocking layer; 107a-light blocking layer film; 20-pixel electrode; 30-public electrode; 40-photoresist; The complete reserve part of 401-photoresist; 402-photoresist is removed part completely; 403-photoresist half reserve part.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of thin-film transistor 10, as shown in Figure 4 and Figure 5, this thin-film transistor 10 comprises: be successively set on grid 101, amorphous silicon layer 103 and ohmic contact layer 104 on underlay substrate 100, the size of described grid 101 is less than the size of described amorphous silicon layer 103; On this basis, described thin-film transistor 10 also comprises: be arranged on the light blocking layer 107 between described amorphous silicon layer 103 and described underlay substrate 100, the remainder of described light blocking layer 107 and the amorphous silicon layer not blocked by described grid 101 is corresponding and exceed described amorphous silicon layer 103.
Certainly, described thin-film transistor 10 also comprises: be arranged on gate insulation layer 102 between described grid 101 and described amorphous silicon layer 103, be arranged on described ohmic contact layer 104 away from the source electrode 105 of underlay substrate 100 1 sides and drain electrode 106.
It should be noted that, the first, the size of described grid 101 is less than the size of described amorphous silicon layer 103, is: the size of the projection of described grid 101 on underlay substrate 100 is less than the size of the projection of described amorphous silicon layer 103 on underlay substrate 100.
Certainly, those skilled in the art will be appreciated that, described amorphous silicon layer 103 is exactly semiconductor active layer, and described grid 101 and described amorphous silicon layer 103 are completely corresponding, and by described amorphous silicon layer 103, the projection on underlay substrate 100 covers completely in the namely projection of described grid 101 on underlay substrate 100.
Second, the remainder of described light blocking layer 103 and the amorphous silicon layer 103 not blocked by described grid 101 is corresponding and exceed described amorphous silicon layer 103, be: described light blocking layer 103, except comprising the part corresponding with the remainder of the amorphous silicon layer 101 not blocked by described grid 101, also comprises the part that surpasses described amorphous silicon layer 103.
The 3rd, because the size of described grid 101 is less than the size of described amorphous silicon layer 103, in this case when described thin-film transistor 10 is applied to array base palte, and when this array base palte is applied to liquid crystal indicator, certainly will cause being mapped to amorphous silicon layer 103 and producing photic leakage current from the illumination of bottom backlight, and one of object of the present invention is the problem that solves photic leakage current, therefore, the light blocking layer 107 that those skilled in the art mention from the embodiment of the present invention with and setting position, just will be appreciated that one of object that described light blocking layer 107 is set is the remainder that is mapped to the amorphous silicon layer 103 not blocked by grid 101 from the illumination of bottom backlight for stopping, thereby avoid producing photic leakage current, therefore, the material of described light blocking layer 107 should be can light absorbing opaque material.
On this basis, because described light blocking layer 107 is except comprising the part corresponding with the remainder of the amorphous silicon layer 101 not blocked by described grid 101, also comprise the part that surpasses described amorphous silicon layer 103, in the case, if described light blocking layer 107 conductions the words that contact with described grid 101, be equivalent to extend the size of grid 101 and made grid 101 sizes after extension be greater than described amorphous silicon layer 103, if based on an alternating floor gate insulation layer 102 between light blocking layer this described 107 and described source electrode 105 and drain electrode 106, can cause the generation of hole leakage current, therefore, if described light blocking layer 103 conductor materials in the embodiment of the present invention, and in the situation that it contacts with grid 101, also need between described light blocking layer 103 and described source electrode 105 and drain electrode 106, be formed for intercepting the insulating barrier of electric field.
The embodiment of the present invention provides a kind of thin-film transistor 10, comprising: be successively set on grid 101, amorphous silicon layer 103 and ohmic contact layer 104 on underlay substrate 100, the size of described grid 101 is less than the size of described amorphous silicon layer 103; On this basis, described thin-film transistor 10 also comprises: be arranged on the light blocking layer 107 between described amorphous silicon layer 103 and described underlay substrate 100, the remainder of described light blocking layer 107 and the amorphous silicon layer not blocked by described grid 101 is corresponding and exceed described amorphous silicon layer 103.
Like this, the process complexity with respect to the consistent grid of preparation size 101 with amorphous silicon layer 103, the embodiment of the present invention, because the size of described grid 101 is less than the size of described amorphous silicon layer 103, makes preparation technology more simple; On this basis, on the one hand, because the size of described grid 101 is less than the size of described amorphous silicon layer 103, make the overlapping region with described source electrode 105 and drain electrode 106 at described grid 101, hole accumulation layer in amorphous silicon layer 103 and ohmic contact layer 104 form PN junction, thereby have avoided the generation of hole leakage current; On the other hand, by described light blocking layer 107 and described grid 101, share effect, can stop that illumination is mapped to described amorphous silicon layer 103, thereby avoid the generation of photic leakage current.
Preferably, as shown in Figure 4, described light blocking layer 107 is arranged between described underlay substrate 101 and described grid 101, and described light blocking layer 107 is also corresponding with described grid 101.
That is: the size of described light blocking layer 107 is greater than the size of described amorphous silicon layer 103, and the projection of described light blocking layer 107 on described underlay substrate 100 covers the projection of described amorphous silicon layer 103 on described underlay substrate 100 completely.
On this basis, if the material of described light blocking layer 107 is insulating material, described light blocking layer 107 can directly contact with described grid 101; If the material of described light blocking layer 107 is conductor material, between described light blocking layer 107 and described grid 101, a layer insulating can be set, specifically can arrange according to actual conditions, at this, do not limit.
Like this, only need when preparing thin-film transistor, additionally make one deck light blocking layer 107, and make the size of described light blocking layer 107 be greater than the size of described amorphous silicon layer 103, just can avoid the generation of photic leakage current and hole leakage current, make preparation technology relatively simple simultaneously.
Further, the material of described light blocking layer 107 is opaque resin.
Described opaque resin can be for example the material identical with making black matrix.
Preferably, as shown in Figure 5, described light blocking layer 107 with described grid 101 with layer and be integrated; Wherein, described light blocking layer 107 obtains for after described grid 101 materials are oxidized away from the surperficial material of described underlay substrate 100, and the material of the remainder of described light blocking layer 107 is identical with described grid 101 materials.
Here, for example can realize in the following way the integral structure of described light blocking layer 107 and described grid 101, that is: when preparing thin-film transistor, by a composition technique, first form the grid metal level that size is greater than amorphous silicon layer 103 sizes, this grid metal level comprises that size to be formed is less than the grid 101 of amorphous silicon layer 103 sizes and is positioned at grid 101 light blocking layer to be formed 107 around, then by related process, make the grid material surface oxidation in described light blocking layer 107 regions, thereby form light blocking layer 107, and make not oxidized grid metal level partly form described grid 101.
It should be noted that, the first, when selecting grid 101 material, answering after selective oxidation is nonconducting grid 101 materials.
Although the bottom of the second light blocking layer 107 is not oxidized part, still contact with grid 101, because the insulating barrier of the oxidized rear formation in surface of light blocking layer 107 can intercept electric field, therefore, still can avoid the generation of hole leakage current.
Like this, only need form described light blocking layer 107 at formation grid 101 simultaneously, just can avoid the generation of photic leakage current and hole leakage current, and can avoid the increase of composition technique and the increase of thin-film transistor 10 integral thickness.
The embodiment of the present invention also provides a kind of array base palte, and as shown in Figure 6, this array base palte comprises above-mentioned thin-film transistor 10, certainly can also comprise the pixel electrode 20 being electrically connected to the drain electrode 106 of described thin-film transistor 10.
Process complexity with respect to the consistent grid of preparation size 101 with the thin-film transistor of amorphous silicon layer 103, thin-film transistor 10 in the array base palte that the embodiment of the present invention provides, because the size of described grid 101 is less than the size of described amorphous silicon layer 103, makes preparation technology more simple; On this basis, on the one hand, because the size of described grid 101 is less than the size of described amorphous silicon layer 103, make the overlapping region with described source electrode 105 and drain electrode 106 at described grid 101, hole accumulation layer in amorphous silicon layer 103 and ohmic contact layer 104 form PN junction, thereby have avoided the generation of hole leakage current; On the other hand, by described light blocking layer 107 and described grid 101, share effect, can stop that illumination is mapped to described amorphous silicon layer 103, thereby avoid the generation of photic leakage current.
On this basis, as shown in Figure 7, described array base palte can also comprise public electrode 30.
Wherein, the array base palte that the embodiment of the present invention provides goes for the production of a senior super dimension switch technology (Advanced Super Dimensional Switching is called for short ADS) type liquid crystal indicator.Wherein, a senior super dimension switch technology, its core technology characteristic description is: the electric field producing by electric field that in same plane, gap electrode edge produces and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved liquid crystal operating efficiency and increased light transmission efficiency.A senior super dimension switch technology can improve the picture quality of TFT-LCD product, has high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (Push Mura).
The embodiment of the present invention also provides a kind of liquid crystal indicator, comprises above-mentioned array base palte.
Herein, described in the embodiment of the present invention, display unit can be specifically product or the parts that liquid crystal display, LCD TV, DPF, mobile phone, panel computer etc. have any Presentation Function.
The embodiment of the present invention also provides a kind of preparation method of thin-film transistor 10, shown in figure 4 and Fig. 5, the method is included on underlay substrate 100 and forms successively grid 101, amorphous silicon layer 103 and ohmic contact layer 104, and the size of described grid 101 is less than the size of described amorphous silicon layer 103; On this basis, described method also comprises: between described amorphous silicon layer 103 and described underlay substrate 100, form light blocking layer 107, the remainder of described light blocking layer 107 and the amorphous silicon layer not blocked by described grid 101 is corresponding and exceed described amorphous silicon layer 103.
Certainly, described method also comprises: the formation gate insulation layer 102 between described grid 101 and described amorphous silicon layer 103, at described ohmic contact layer 104, away from underlay substrate 100 1 sides, form source electrodes 105 and drain electrode 106.
Process complexity with respect to the consistent grid of preparation size 101 with amorphous silicon layer 103, the embodiment of the present invention, because the size of described grid 101 is less than the size of described amorphous silicon layer 103, makes preparation technology more simple; On this basis, on the one hand, because the size of described grid 101 is less than the size of described amorphous silicon layer 103, make the overlapping region with described source electrode 105 and drain electrode 106 at described grid 101, hole accumulation layer in amorphous silicon layer 103 and ohmic contact layer 104 form PN junction, thereby have avoided the generation of hole leakage current; On the other hand, by described light blocking layer 107 and described grid 101, share effect, can stop that illumination is mapped to described amorphous silicon layer 103, thereby avoid the generation of photic leakage current.
Preferably, shown in figure 4, described light blocking layer 107 is formed between described underlay substrate 100 and described grid 101, and described light blocking layer 107 is also corresponding with described grid 101.
That is: the size of described light blocking layer 107 is greater than the size of described amorphous silicon layer 103, and the projection of described light blocking layer 107 on described underlay substrate 100 covers the projection of described amorphous silicon layer 103 on described underlay substrate 100 completely.
On this basis, if the material of described light blocking layer 107 is insulating material, described light blocking layer 107 can directly contact with described grid 101; If the material of described light blocking layer 107 is conductor material, between described light blocking layer 107 and described grid 101, can form a layer insulating, specifically can arrange according to actual conditions, at this, do not limit.
Like this, only need when preparing thin-film transistor, additionally make one deck light blocking layer 107, and make the size of described light blocking layer 107 be greater than the size of described amorphous silicon layer 103, just can avoid the generation of photic leakage current and hole leakage current, make preparation technology relatively simple simultaneously.
Further, the material of preferred described light blocking layer 107 is opaque resin, can on underlay substrate 100, first form described light blocking layer 107 that is:, then above light blocking layer 107, forms described grid 101, and described light blocking layer 107 contacts with described grid 101.
Concrete, form described grid 101, described light blocking layer 107 comprises the steps:
S101, as shown in Figure 8 a forms successively light blocking layer film 107a, grid metallic film 101a, and form photoresist 40 on described grid metallic film 101a on underlay substrate 100.
S102, as shown in Figure 8 b, adopts normal masks plate to being formed with the base board to explosure of described photoresist 40, forms the complete reserve part 401 of photoresist and photoresist is removed part 402 completely after developing; Wherein, the size of the complete reserve part 401 of described photoresist is greater than the size of described grid 101, and the complete reserve part 401 of described photoresist covers described grid 101 completely, and described photoresist is removed corresponding other regions of part 402 completely.
S103, as shown in Figure 8 c, adopts wet-etching technology pair to remove described grid metallic film 101a corresponding to part 402 completely with described photoresist and carries out etching, forms described grid 101.
In this step, adopt wet-etching technology, because wet etching has anisotropy, not only there is vertical etching, also has horizontal undercutting, thereby not only etching is removed described grid metallic film 101a corresponding to part 402 completely with described photoresist, can also etching be positioned at the grid metallic film 101a of the complete reserve part of described photoresist 401 belows, and then form the described grid 101 that size is less than the complete reserve part 401 of described photoresist.
It should be noted that, by controlling the etching parameters of wet etching, can controlling, be positioned at the degree that the grid metallic film 101a of the complete reserve part of described photoresist 401 belows is etched, thereby control the size of the grid 101 forming.
S104, as shown in Fig. 8 d, the complete reserve part 401 of the described photoresist of take is mask, adopts dry etch process to carry out etching to described light blocking layer film 107a, forms described light blocking layer 107.
In this step, adopt dry etch process, be because dry etching can only have vertical etching, thereby only by removing light blocking layer film 107a corresponding to part 402 completely with described photoresist, etch away.
It should be noted that, due to the size of the complete reserve part 401 of photoresist and the consistent size of described light blocking layer 107, and the object that forms described light blocking layer 107 is to stop that illumination is mapped to the remainder of the amorphous silicon layer 103 not blocked by grid 101, therefore, those skilled in the art will be appreciated that, in above-mentioned steps S102, when the size of controlling the complete reserve part 401 of described photoresist is greater than the size of described grid 101, need to consider to make the size of amorphous silicon layer 103 of follow-up formation between the size of described grid 101 and the size of the complete reserve part 401 of described photoresist.
S105, as shown in Fig. 8 e, adopt stripping technology to remove the photoresist of the complete reserve part of described photoresist.
On this basis, shown in figure 4, when forming described amorphous silicon layer 103, only need make its size be greater than the size of described grid 101 and be less than the size of described light blocking layer 107.
By above-mentioned steps S101-S105, can only pass through a composition technique, just can form described light blocking layer 107 and described grid 101.
Preferably, described light blocking layer 107 with described grid 101 with layer and be integrated.On this basis, form described grid 101, described light blocking layer 107 specifically can comprise the steps:
S201, as shown in Fig. 9 a, on underlay substrate 100, form grid metallic film 101a, and form photoresist 40 on described grid metallic film 101a.
S202, as shown in Fig. 9 b, adopt half rank or gray-tone mask plate to being formed with the base board to explosure of described photoresist, after developing, form the complete reserve part 401 of photoresist, photoresist half reserve part 403 and photoresist and remove part 402 completely; Wherein, the region of the corresponding described grid 101 of the complete reserve part 401 of described photoresist, the region of the corresponding described light blocking layer 107 of described photoresist half reserve part 403, described photoresist is removed corresponding other regions of part 402 completely.
It should be noted that, owing to forming the object of described light blocking layer 107, be to stop that illumination is mapped to the remainder of the amorphous silicon layer 103 not blocked by grid 101, therefore, those skilled in the art will be appreciated that, when the size of photoresist half reserve part 403 is set, need to consider to make the size of amorphous silicon layer 103 of follow-up formation between the size and described grid 101 and the overall dimensions of described light blocking layer 107 of described grid 101.
S203, as shown in Fig. 9 c, adopt etching technics to remove the described grid metallic film 101a that described photoresist is removed part completely.
S204, as shown in Fig. 9 d, using plasma bombards described photoresist half reserve part 403, removes the photoresist of described photoresist half reserve part 403; And adjust plasma parameter, make the surface oxidation of the described grid metallic film 101a corresponding with described photoresist half reserve part 403 form described light blocking layer 107, the described grid metallic film 101a corresponding with the complete reserve part 401 of described photoresist forms grid 101, removes the photoresist of the complete reserve part 401 of described photoresist simultaneously.
Here, for example can use Ar/O
2, or Ar/O
2/ N
2plasma carries out two step bombardments to described photoresist half reserve part 403.The first step is bombarded the photoresist of removing described photoresist half reserve part 403 fast, second step reduces the O2 content in above-mentioned plasma, slowly bombardment, make the surface oxidation of the described grid metallic film 101a corresponding with described photoresist half reserve part 403 form described light blocking layer 107, and remove the photoresist of the complete reserve part 401 of described photoresist simultaneously.
Wherein, oxidation depth for example can reach 50～80nm.
It should be noted that, although the bottom of light blocking layer 107 is not oxidized part, still contact with grid 101, because the insulating barrier of the oxidized rear formation in surface of light blocking layer 107 can intercept electric field, therefore, still can avoid the generation of hole leakage current.
On this basis, shown in figure 5, when forming described amorphous silicon layer 103, only need make its size be greater than the size of described grid 101 and be less than the overall dimensions of described grid 101 and described light blocking layer 107.
By above-mentioned steps S201-S204, can only pass through a composition technique, just can form described light blocking layer 107 and described grid 101.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (10)
1. a thin-film transistor, comprises the grid, amorphous silicon layer and the ohmic contact layer that are successively set on underlay substrate, it is characterized in that, the size of described grid is less than the size of described amorphous silicon layer;
Described thin-film transistor also comprises: be arranged on the light blocking layer between described amorphous silicon layer and described underlay substrate, the remainder of described light blocking layer and the amorphous silicon layer not blocked by described grid is corresponding and exceed described amorphous silicon layer.
2. thin-film transistor according to claim 1, is characterized in that, described light blocking layer is arranged between described underlay substrate and described grid, and described light blocking layer is also corresponding with described grid.
3. thin-film transistor according to claim 2, is characterized in that, the material of described light blocking layer is opaque resin.
4. thin-film transistor according to claim 1, is characterized in that, described light blocking layer and described grid with layer and be integrated; Wherein, described light blocking layer obtains for after described grid material is oxidized away from the surperficial material of described underlay substrate, and the material of the remainder of described light blocking layer is identical with described grid material.
5. an array base palte, is characterized in that, comprises the thin-film transistor described in claim 1 to 4 any one.
6. a liquid crystal indicator, is characterized in that, comprises array base palte claimed in claim 5.
7. a preparation method for thin-film transistor, is included on underlay substrate and forms successively grid, amorphous silicon layer and ohmic contact layer, it is characterized in that, the size of described grid is less than the size of described amorphous silicon layer;
Described method also comprises: between described amorphous silicon layer and described underlay substrate, form light blocking layer, the remainder of described light blocking layer and the amorphous silicon layer not blocked by described grid is corresponding and exceed described amorphous silicon layer.
8. method according to claim 7, is characterized in that, described light blocking layer is formed between described underlay substrate and described grid, and described light blocking layer is also corresponding with described grid.
9. method according to claim 8, is characterized in that, the material of described light blocking layer is opaque resin;
Form described grid, described light blocking layer specifically comprises:
On underlay substrate, form successively light blocking layer film, grid metallic film, and form photoresist on described grid metallic film;
Adopt normal masks plate to being formed with the base board to explosure of described photoresist, after developing, the formation complete reserve part of photoresist and photoresist are removed part completely; Wherein, the size of the complete reserve part of described photoresist is greater than the size of described grid, and the complete reserve part of described photoresist covers described grid completely, and described photoresist is removed corresponding other regions of part completely;
Adopt wet-etching technology pair to remove described grid metallic film corresponding to part completely with described photoresist and carry out etching, form described grid;
The complete reserve part of described photoresist of take is mask, adopts dry etch process to carry out etching to described light blocking layer film, forms described light blocking layer;
Adopt stripping technology to remove the photoresist of the complete reserve part of described photoresist.
10. method according to claim 7, is characterized in that, described light blocking layer and described grid with layer and be integrated;
Form described grid, described light blocking layer specifically comprises:
On underlay substrate, form grid metallic film, and form photoresist on described grid metallic film;
Adopt half rank or gray-tone mask plate to being formed with the base board to explosure of described photoresist, after developing, form the complete reserve part of photoresist, photoresist half reserve part and photoresist and remove part completely; Wherein, the region of the corresponding described grid of the complete reserve part of described photoresist, the region of the corresponding described light blocking layer of described photoresist half reserve part, described photoresist is removed corresponding other regions of part completely;
Adopt etching technics to remove the described grid metallic film that described photoresist is removed part completely;
Using plasma bombards described photoresist half reserve part, removes the photoresist of described photoresist half reserve part; And adjust plasma parameter, make the surface oxidation of the described grid metallic film corresponding with described photoresist half reserve part form described light blocking layer, the described grid metallic film corresponding with the complete reserve part of described photoresist forms grid, removes the photoresist of the complete reserve part of described photoresist simultaneously.
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