CN104241112B - The forming method of amorphous semiconductor material and the forming method of metal silicide - Google Patents
The forming method of amorphous semiconductor material and the forming method of metal silicide Download PDFInfo
- Publication number
- CN104241112B CN104241112B CN201310232183.5A CN201310232183A CN104241112B CN 104241112 B CN104241112 B CN 104241112B CN 201310232183 A CN201310232183 A CN 201310232183A CN 104241112 B CN104241112 B CN 104241112B
- Authority
- CN
- China
- Prior art keywords
- equal
- semiconductor material
- forming method
- amorphous semiconductor
- less
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 195
- 239000000463 material Substances 0.000 title claims abstract description 115
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 80
- 239000002184 metal Substances 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 78
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 39
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 239000007789 gas Substances 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000000137 annealing Methods 0.000 claims abstract description 44
- 238000002360 preparation method Methods 0.000 claims abstract description 32
- 239000002912 waste gas Substances 0.000 claims abstract description 17
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 47
- 229910052710 silicon Inorganic materials 0.000 claims description 46
- 239000010703 silicon Substances 0.000 claims description 46
- 239000002243 precursor Substances 0.000 claims description 27
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
- 229910052739 hydrogen Inorganic materials 0.000 claims description 16
- 239000001257 hydrogen Substances 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 15
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 14
- 238000001816 cooling Methods 0.000 claims description 10
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910007264 Si2H6 Inorganic materials 0.000 claims description 6
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 6
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims description 5
- 239000007792 gaseous phase Substances 0.000 claims description 5
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 3
- 238000010521 absorption reaction Methods 0.000 claims description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 claims 1
- 239000007769 metal material Substances 0.000 description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 description 12
- 150000002431 hydrogen Chemical class 0.000 description 8
- 238000005381 potential energy Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 229910003828 SiH3 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- VGRFVJMYCCLWPQ-UHFFFAOYSA-N germanium Chemical compound [Ge].[Ge] VGRFVJMYCCLWPQ-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- 229910005487 Ni2Si Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000012686 silicon precursor Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
A kind of forming method of amorphous semiconductor material and the forming method of metal silicide.The forming method of the amorphous semiconductor material includes：Semiconductor preparation layers are formed on a semiconductor substrate；Ultraviolet treatment with irradiation to semiconductor preparation layers are carried out to semiconductor preparation layers and are decomposed into amorphous semiconductor material and waste gas；Remove removing exhaust gas；The step of being repeatedly formed semiconductor preparation layers, ultraviolet treatment with irradiation and remove removing exhaust gas, until forming the amorphous semiconductor material of predetermined thickness on a semiconductor substrate.The forming method of the metal silicide includes：Semiconductor substrate is provided, Semiconductor substrate includes source region and drain region；Metal level is formed respectively in source region and drain region；Carry out first time annealing；Amorphous semiconductor material is formed using the forming method of above-mentioned amorphous semiconductor material on the metal layer；Second is carried out to make annealing treatment；Remove amorphous semiconductor material.The present invention can be at 400 DEG C and following temperature formation amorphous semiconductor material.
Description
Technical field
The present invention relates to the forming method and gold of technical field of manufacturing semiconductors, more particularly to a kind of amorphous semiconductor material
Belong to the forming method of silicide.
Background technology
With the development of semiconductor technology, the application of amorphous semiconductor material is more and more extensive.By taking non-crystalline silicon as an example,
Because it can be compatible with silicon substrate progress well, non-crystalline silicon is applied in semiconductor devices in large quantities（Such as：Non-crystalline silicon is too
Positive energy battery）Manufacturing process in.
The forming method of non-crystalline silicon comprises the following steps in the prior art：
Semiconductor base is provided；
In semiconductor substrate surface formation SiH4Layer；
It is heat-treated, makes SiH4Layer is decomposed into amorphous Si and H at a temperature of more than 400 DEG C2, specific chemical equation
For：SiH4=Si+2H2↑；
Remove the H2。
Above-mentioned non-crystalline silicon is formed under the hot conditions more than 400 DEG C.Similarly, other amorphous half in the prior art
Conductor material is also all formed under the high temperature conditions.
With the further development of semiconductor technology, wish in some circumstances under the cryogenic conditions below 400 DEG C
Amorphous semiconductor material is formed, so that the forming process of amorphous semiconductor material does not produce influence etc. to other semiconductor layers.
Therefore, it is just urgently to be resolved hurrily as those skilled in the art that amorphous semiconductor material how is formed at a lower temperature
One of problem.
The content of the invention
The problem of present invention is solved is to provide a kind of forming method of amorphous semiconductor material and the formation of metal silicide
Method, can be at 400 DEG C and following temperature formation amorphous semiconductor material.
To solve the above problems, the present invention provides a kind of forming method of amorphous semiconductor material, including：
Semiconductor preparation layers are formed on a semiconductor substrate；
Ultraviolet treatment with irradiation is carried out to the semiconductor preparation layers, until the semiconductor preparation layers are decomposed into amorphous half
Conductor material and waste gas, the temperature of the ultraviolet treatment with irradiation are less than or equal to 400 DEG C；
Remove the waste gas；
The step of repeating above-mentioned formation semiconductor preparation layers, ultraviolet treatment with irradiation and remove removing exhaust gas, until described half
The amorphous semiconductor material of predetermined thickness is formed in conductor substrate.
Optionally, the temperature of the ultraviolet treatment with irradiation is more than or equal to 20 DEG C and less than or equal to 300 DEG C.
Optionally, the semiconductor preparation layers are formed using chemical gaseous phase depositing process.
Optionally, the gas that the chemical gaseous phase depositing process is used includes：Si2H6、SiH2Cl2（That is DCS）、SiH3With
SiH4In one kind or any combination.
Optionally, the gas that the chemical gaseous phase depositing process is used includes：Ge2H6、GeH3And GeH4In one kind or appoint
Meaning combination.
Optionally, the gas that the chemical gaseous phase depositing process is used also includes：Oxygen.
Optionally, the flow of every kind of gas is more than or equal to 1sccm and less than or equal to 300sccm.
Optionally, the time for forming the semiconductor preparation layers every time is more than or equal to 0.01s and less than or equal to 10s.
Optionally, the power of the ultraviolet treatment with irradiation is more than or equal to 10W and less than or equal to 1000W, and pressure is big
In or equal to 0.1Torr and less than or equal to 500Torr.
Optionally, the waste gas is removed using one kind in argon gas and hydrogen or combination.
Optionally, the flow of the argon gas and hydrogen is more than or equal to 1sccm and less than or equal to 1000sccm.
Optionally, the time that the waste gas is removed every time is more than or equal to 0.1s and less than or equal to 10s.
Optionally, while ultraviolet treatment with irradiation is carried out, in addition to：The semiconductor base is carried out at cooling
Reason, the temperature of the cooling treatment is more than or equal to 20 DEG C and less than or equal to 300 DEG C.
To solve the above problems, present invention also offers a kind of forming method of metal silicide, including：
Semiconductor substrate is provided, the Semiconductor substrate includes source region and drain region；
At least metal level is formed in the source region and drain region；
First time annealing is carried out, the temperature of the first time annealing is more than or equal to 200 DEG C and is less than or waits
In 400 DEG C；
Amorphous semiconductor material is formed using the forming method of above-mentioned amorphous semiconductor material on the metal layer；
Carry out second to make annealing treatment, the temperature of second of annealing is more than or equal to 400 DEG C and is less than or waits
In 700 DEG C；
Remove the amorphous semiconductor material.
Optionally, the time of the first time annealing is more than or equal to 10s and less than or equal to 20s, described second
The time of secondary annealing is more than or equal to 10s and less than or equal to 20s.
Optionally, the thickness of the amorphous semiconductor material is more than or equal to 10 angstroms and less than or equal to 200 angstroms.
Optionally, the amorphous semiconductor material is removed using wet etching method.
Optionally, the amorphous semiconductor material is non-crystalline silicon, and the wet etching method is used in TMAH and KOH solution
One kind or combination.
Optionally, gate electrode is also included in the Semiconductor substrate, the material of the gate electrode is polysilicon；The metal
The forming method of silicide also includes：While forming the metal level in the source region and drain region, on the gate electrode
Form metal level；While amorphous semiconductor material is formed on the metal level, the amorphous semiconductor material is while shape
Into on the metal level on gate electrode.
Optionally, the material of the metal level includes nickel.
Compared with prior art, technical scheme has advantages below：
In the forming method for the amorphous semiconductor material that the present invention is provided, semiconductor preparation layers are formed on a semiconductor substrate
Afterwards, the heat treatment of prior art high temperature is substituted with ultraviolet treatment with irradiation, i.e., is caused by carrying out ultraviolet treatment with irradiation
Semiconductor preparation layers are decomposed into amorphous semiconductor material and waste gas, just can be on a semiconductor substrate after the waste gas is removed
The amorphous semiconductor material of individual layer is formed, and then semiconductor preparation layers, ultraviolet treatment with irradiation can be repeatedly formed as needed
With the process for removing removing exhaust gas.Because the temperature of ultraviolet treatment with irradiation is less than or equal to 400 DEG C, so that whole amorphous semiconductor material
Temperature of the forming process of material all without experience higher than 400 DEG C, may finally avoid producing influence etc. to other semiconductor layers.
Further, while ultraviolet treatment with irradiation is carried out, the semiconductor base can also be carried out at cooling
Reason, the temperature of the cooling treatment is more than or equal to 20 DEG C and less than or equal to 300 DEG C, is being formed so as to be further ensured that
During amorphous semiconductor material, semiconductor base is at low-temperature condition, may finally improve and partly be led including the amorphous
The performance of the semiconductor devices of body material.
In the forming method for the metal silicide that the present invention is provided, the metal level on to source region and drain region carries out low temperature
After making annealing treatment for the first time, amorphous is first formed using the forming method of above-mentioned amorphous semiconductor material under cryogenic and partly led
Body material, to avoid metal material from diffusing to source region and drain region during amorphous semiconductor material is formed, is then carried out again
Second of annealing of high temperature, so that in second of annealing process, metal material can diffuse to amorphous semiconductor material
In material rather than source region and drain region are diffused to, erosion of the metal material to Semiconductor substrate may finally be suppressed, improve and partly lead
The yield of body device.
Brief description of the drawings
Fig. 1 is the schematic diagram of the forming method of metal silicide in the prior art；
Fig. 2 to Fig. 9 is the schematic diagram of the embodiment of forming method one of amorphous semiconductor material of the present invention；
Figure 10 to Figure 12 is the schematic diagram of the embodiment of forming method one of metal silicide of the present invention.
Embodiment
In the prior art, all it is to form amorphous semiconductor material under the high temperature conditions, so that semiconductor technology can not be met
Development need.
Prior art comprises the following steps when forming metal silicide：
With reference to shown in Fig. 1, silicon substrate 60 is first provided, the silicon substrate 60 includes source region 61 and drain region 62, the silicon lining
Include grid structure on bottom 60, the grid structure includes：Gate dielectric layer 81 on silicon substrate 60, positioned at gate dielectric layer 81
On metal gate electrode 82, the side wall 83 on the silicon substrate 60 of gate dielectric layer 81 and the both sides of metal gate electrode 82.
With continued reference to shown in Fig. 1, metal level 71 is formed in source region 61, and forms on drain region 62 metal level 72.
Then, first time annealing processing is carried out, so that metal level 71 and 72 is changed into the transition state product of high resistant.
Then, carry out second to make annealing treatment, so that the transition state product of high resistant is changed into the metal silicide of low-resistance.
Because the temperature of second of annealing will be far above the temperature made annealing treatment for the first time, so as to carry out second
During annealing, the metal material in metal level 71 and 72 can be downward（Such as arrow direction in Fig. 1）Corrode and be located at transistor
Silicon materials below side wall 83, and can enter in the channel region under grid structure, eventually result in crystal tube short circuit so that partly lead
Body yield of devices declines to a great extent.
Inventor has found that：During metal silicide is formed, after first time annealing is carried out
And before second of annealing is carried out, one layer of amorphous semiconductor material can be first formed on the metal layer（Such as：Non-crystalline silicon
Layer）, because the potential energy of amorphous semiconductor material is less than the potential energy of metal level, and the compactness of amorphous semiconductor material is poor,
So that when carrying out second and making annealing treatment, metal material can remove the amorphous semiconductor material corroded above it, it is to avoid invade
Silicon substrate is lost, the yield of semiconductor devices may finally be greatly improved.
When forming amorphous semiconductor material on the metal layer using the method for prior art, due to being hot conditions, its
The temperature difference of temperature range and second of annealing is little, therefore will make during amorphous semiconductor material is formed
Metal material is obtained to diffuse in silicon substrate.Based on this, it is necessary to which reduction forms the temperature of amorphous semiconductor material so that in metal
When forming amorphous semiconductor material on layer, metal material will not be diffused in silicon substrate.
Inventor has found after further research, when forming amorphous semiconductor material, can be less than or wait by temperature
High-temperature heat treatment of the prior art is replaced in 400 DEG C of ultraviolet treatment with irradiation, in this temperature range, metal material will not
It is diffused into silicon substrate, that is, form the process of amorphous semiconductor material does not influence on metal level and silicon substrate, finally
When second makes annealing treatment, metal material changes dispersal direction, it is to avoid the influence to silicon substrate.
The method of above-mentioned formation amorphous semiconductor material be also applied to making other semiconductor devices during, its
Do not limit the scope of the invention.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
A kind of forming method of amorphous semiconductor material is present embodiments provided, for simplicity, below with amorphous
Illustrated exemplified by silicon.
There is provided semiconductor base 10 with reference to shown in Fig. 2.
The semiconductor base 10 can be silicon substrate, germanium silicon substrate or silicon on insulated substrate, or people in the art
Other known semiconductive material substrates of member.Device layer and interconnection structure etc. can also be formed with the semiconductor base 10.
With continued reference to shown in Fig. 2, semiconductor base 10 is put into reaction chamber（It is not shown）In, and carry out chemical vapor deposition
Technique, i.e., be passed through the precursor gas 20 of silicon into reaction chamber, and the precursor gas 20 of the part silicon can be adsorbed in semiconductor base
10 upper surface, the precursor gas 20 of the part silicon is unadsorbed on semiconductor base 10 but in suspended state.
The precursor gas of the silicon can include Si2H6、SiH2Cl2、SiH3And SiH4In one or more any groups
Close, the precursor gas 20 of silicon is Si in the present embodiment2H6。
Can being more than or equal to 1sccm with flow and being less than or equal to 300sccm for the precursor gas 20 of the silicon, is passed through institute
0.01s can be more than or equal to and less than or equal to 10s by stating the time of the precursor gas 20 of silicon.
With reference to shown in Fig. 3, the precursor gas 20 of the silicon in suspended state in Fig. 2 is removed, so that only remaining absorption
Semiconductor preparation layers are used as in the precursor gas 20 of the silicon of the upper surface of semiconductor base 10.
Specifically, the one kind that can be passed through into reaction chamber in argon gas and hydrogen or its combination, the flow model of every kind of gas
Enclose including 1sccm~1000sccm, the time for being passed through gas can be 0.1s~10s, so as to can just remove in reaction chamber not
Adsorb the precursor gas 20 in the silicon of the upper surface of semiconductor base 10.
Semiconductor preparation layers are formed by adsorption in the present embodiment, and will not reacted by argon gas or hydrogen etc.
Gas drive reative cell out of, so as to adsorb the semiconductor preparation layers on semiconductor base 10 carry out subsequent treatment.
With reference to shown in Fig. 4, the precursor gas 20 to remaining silicon carries out ultraviolet treatment with irradiation, i.e., irradiated using ultraviolet
The precursor gas 20 in the silicon of the upper surface of semiconductor base 10 is adsorbed in Fig. 3, until the precursor gas 20 of silicon is decomposed into non-crystalline silicon
21 and hydrogen 22.
The temperature of the ultraviolet treatment with irradiation can be less than or equal to 400 DEG C, so as to ensure forming non-crystalline silicon 21
During, without undergoing high temperature.
The temperature of the present embodiment middle-ultraviolet lamp treatment with irradiation can be more than or equal to 20 DEG C and less than or equal to 300 DEG C, such as：
20 DEG C, 70 DEG C, 100 DEG C, 180 DEG C, 250 DEG C or 300 DEG C etc., i.e., at these tem-peratures the precursor gas 20 of silicon can be decomposed into it is non-
Crystal silicon 21 and hydrogen 22.
Specifically, because the precursor gas 20 of silicon in the present embodiment is Si2H6, therefore silicon precursor gas 20 in ultraviolet
The process that non-crystalline silicon 21 and hydrogen 22 are decomposed under irradiation is：Si2H6=2Si+3H2↑, wherein non-crystalline silicon 21 is used as amorphous semiconductor
Material, hydrogen 22 is used as waste gas.
It should be noted that when precursor gas of other gases of selection as silicon, waste gas may change, and such as work as
The precursor gas of silicon is SiH2Cl2When, waste gas now is HCl.
The power of the ultraviolet treatment with irradiation can be more than or equal to 10W and less than or equal to 1000W, and pressure can be big
In or equal to 0.1Torr and less than or equal to 500Torr.
The time of the ultraviolet treatment with irradiation is relevant with temperature, and temperature is higher, and the time is shorter, when the precursor gas 20 of silicon
It can just stop the ultraviolet treatment with irradiation when decomposing completely.
Optionally, while ultraviolet treatment with irradiation is being carried out, it can also include：The semiconductor base 10 is carried out
Cooling treatment, the temperature of the cooling treatment is more than or equal to 20 DEG C and less than or equal to 300 DEG C, so as to be further ensured that
During non-crystalline silicon 21 is formed, semiconductor base 10 is at low-temperature condition, may finally improve including the non-crystalline silicon
The performance of 21 semiconductor devices.The cooling treatment can be that water cooling can also be air-cooled, and it does not influence the protection of the present invention
Scope.
With reference to shown in Fig. 5, the hydrogen 22 in Fig. 4 is removed, so as to form amorphous silicon layer 30 on semiconductor base 10.
Specifically, the one kind that can be passed through into reaction chamber in argon gas and hydrogen or its combination, the flow model of every kind of gas
Enclose including 1sccm~1000sccm, the time for being passed through gas can be 0.1s~10s, so as to can just remove in reaction chamber
Waste gas（That is hydrogen 22）.
The thickness of the amorphous silicon layer 30 now formed on semiconductor base 10 is only 0.1 angstrom~5 angstroms, can not typically be met
Demand.
With reference to shown in Fig. 6, the precursor gas 40 of silicon is passed through into reaction chamber, the precursor gas 40 of the part silicon can be adsorbed
In the upper surface of amorphous silicon layer 30, the precursor gas 40 of the part silicon is unadsorbed on amorphous silicon layer 30 but in suspension
State.
Step corresponding to Fig. 2 specifically is may be referred to, be will not be repeated here.
With reference to shown in Fig. 7, the precursor gas 40 of the unadsorbed silicon on amorphous silicon layer 30 in Fig. 6 is removed, so that useization
Learn gas-phase deposition and semiconductor preparation layers are formd on amorphous silicon layer 30.
Step corresponding to Fig. 3 specifically is may be referred to, be will not be repeated here.
With reference to shown in Fig. 8, ultraviolet treatment with irradiation is carried out to amorphous silicon layer 30, so as to adsorb the silicon on amorphous silicon layer 30
Precursor gas be decomposed into non-crystalline silicon 41 and hydrogen 42.
Step corresponding to Fig. 4 specifically is may be referred to, be will not be repeated here.
With reference to shown in Fig. 9, the hydrogen 42 in Fig. 8 is removed, amorphous silicon layer 50 is formed on amorphous silicon layer 30.
Step corresponding to Fig. 5 specifically is may be referred to, be will not be repeated here.
Subsequently can be as needed, repeat above-mentioned formation semiconductor preparation layers, ultraviolet treatment with irradiation and remove removing exhaust gas
Step is one or many, until forming the non-crystalline silicon of predetermined thickness on the semiconductor base 10.
In other embodiments of the invention, when the amorphous semiconductor material to be formed is amorphous germanium, now using
Gas during chemical vapor deposition method formation semiconductor preparation layers can include Ge2H6、GeH3And GeH4In one or more
Any combination；When the amorphous semiconductor material to be formed is amorphous silica, now chemical vapor deposition method is being used
Gas during formation semiconductor preparation layers is except including Si2H6、SiH2Cl2、SiH3And SiH4In one or more any groups
Outside conjunction, in addition it is also necessary to including oxygen；When the amorphous semiconductor material to be formed is amorphous oxide germanium, now using chemical gas
Gas during phase depositing operation formation semiconductor preparation layers is except including Ge2H6、GeH3And GeH4In it is one or more any
Outside combination, in addition it is also necessary to including oxygen.
Above-described embodiment is formed after semiconductor preparation layers on a semiconductor substrate, is substituted with ultraviolet treatment with irradiation existing
The heat treatment of technology high temperature, i.e., by carrying out ultraviolet treatment with irradiation so that semiconductor preparation layers are decomposed into amorphous semiconductor material
Material and waste gas, the amorphous semiconductor material of individual layer can be just formed on a semiconductor substrate after the waste gas is removed, and then
It can need to be repeatedly formed semiconductor preparation layers, ultraviolet treatment with irradiation and the process for removing removing exhaust gas.At ultraviolet irradiation
The temperature of reason is less than or equal to 400 DEG C, so that the forming process of whole amorphous semiconductor material is all higher than 400 DEG C without experience
Temperature, may finally avoid producing influence etc. to other semiconductor layers.
The present embodiment additionally provides a kind of forming method of metal silicide, comprises the following steps：
There is provided Semiconductor substrate 100 with reference to shown in Figure 10, the Semiconductor substrate 100 includes source region 110 and drain region
120, grid structure is included in the Semiconductor substrate 100.
The Semiconductor substrate 100 can be silicon substrate, germanium silicon substrate or silicon on insulated substrate, or people in the art
Other known semiconductive material substrates of member.Semiconductor substrate 100 includes arbitrary transistor, and and transistor in the present embodiment
The material of the corresponding Semiconductor substrate 100 of middle source region 110 and drain region 120 is single-crystal semiconductor material, such as：Monocrystalline silicon.
Specifically, the grid structure is situated between including the gate dielectric layer 210 in Semiconductor substrate 100, positioned at the grid
Gate electrode 220 on matter layer 210 and the Semiconductor substrate positioned at the side of gate dielectric layer 210 and the side of the gate electrode 220
Side wall 230 on 100.
The material of the gate dielectric layer 210 can be silica or high-k dielectric material；The gate electrode 220
Material can be polysilicon or metal material.
Gate dielectric layer 210 described in the present embodiment is high-k dielectric material, and the gate electrode 220 is metal material, so that nothing
Metal silicide need to be formed on grid structure.
It should be noted that the grid structure can also use other structures, it is not limited the scope of the invention.
With continued reference to shown in Figure 10, metal level 310a is formed in the source region 110, and formed on the drain region 120
Metal level 320a.
The material of the metal level 310a and 320a can be nickel, cobalt or titanium.
Metal level 310a described in the present embodiment is nickel.Specifically, first using physical vapour deposition (PVD) or chemical vapor deposition
Nickel material is formed in Semiconductor substrate 100 and grid structure, the nickel material is then etched by selective etch technique, directly
Nickel material to only remaining source region 110 and drain region 120, so as to obtain metal level 310a and 320a.
It should be noted that when gate electrode is polysilicon, when etching nickel material, in addition it is also necessary to be located at grid electricity while retaining
Nickel material on extremely.
Then, first time annealing is carried out, the temperature of the first time annealing is more than or equal to 200 DEG C and is less than
Or equal to 400 DEG C.
The time of the first time annealing can be more than or equal to 10s and less than or equal to 20s.
The temperature selection of the first time annealing is relatively low so that there was only the part gold adjacent with source region 110 after annealing
The category layer 310a and part metal level 320a adjacent with drain region 120 forms metal silicide with pasc reaction, and topmost still
There are part metals to fail to react with silicon.Further, since the temperature selected is relatively low, the metal silicide now produced is one kind
The transition state product of high resistant, such as：Ni2Si, GoSi etc..
Because the temperature of first time annealing is than relatively low, therefore metal level 310a and metal level 320 will not corrode and be located at
Silicon materials below transistor side wall 230, and will not enter in the channel region under grid structure.
Then, with reference to shown in Figure 11, first time make annealing treatment after, can using wet-etching technology remove not with silicon
The metal level 310a and 320a reacted, so as to leave behind the metal silicide 310b and 320b of high resistant.
With continued reference to shown in Figure 11, formed on the metal silicide 310b and 320b of high resistant and the surface of grid structure
Amorphous semiconductor material 400.
The amorphous semiconductor material 400 is needed in low temperature environment（Less than or equal to 400 DEG C）It is lower to be formed.In the present embodiment
The amorphous semiconductor material 400 is non-crystalline silicon, and it can specifically be formed using the method for above-described embodiment, now the gold of high resistant
Belong to silicide 310b and 320b and grid structure as the semiconductor base, will not be repeated here.
The thickness of the amorphous semiconductor material 400 can be more than or equal to 10 angstroms and less than or equal to 200 angstroms, such as：10
Angstrom, 50 angstroms, 100 angstroms, 150 angstroms or 200 angstroms.
Due to only needing to be formed in source region 110 and drain region 120 in metal silicide, therefore the present embodiment in the present embodiment
Amorphous semiconductor material 400 can be only located on metal level 310a and metal level 320a.But be also required to when on gate electrode 230
When forming metal silicide, then amorphous semiconductor material 400 is also required to while on the metal level on gate electrode 230.
Due to now forming the temperature of amorphous semiconductor material 400 than relatively low, thus the metal silicide 310b of high resistant and
Metal in 320b will not spread downwards.
Then, with reference to reference to shown in Figure 12, for the metal silicide of high resistant formed after making annealing treatment for the first time
310b and 320b are converted into the metal silicide 310c and 320c of low-resistance, carry out second and make annealing treatment, second of the annealing
The temperature of processing is more than or equal to 400 DEG C and less than or equal to 700 DEG C.
The time of second of annealing can be more than or equal to 10s and less than or equal to 20s.
The temperature of second of annealing is more than the temperature of annealing for the first time, so as to form the gold of low-resistance
Belong to silicide 310c and 320c, such as：GoSi2, NiSi etc., the electrical contact quality of formation is preferable.
Although the temperature of second of annealing is higher, metal can further spread in being made annealing treatment at second,
Be due to the amorphous semiconductor material 400 being now placed on the metal silicide 310b and 320b of high resistant potential energy be much smaller than high resistant
Metal silicide potential energy, and its compactness is poor, and the Semiconductor substrate 100 of amorphous silicon material then potential energy than larger, and
Quality is closer, therefore now the dispersal direction of metal can be upward（As shown in arrow in Figure 11）, i.e., from the high ground of potential energy
The low place diffusion of direction potential energy, that is, diffuse into amorphous semiconductor material 400, be located at transistor side wall without corroding
Silicon materials below 230, and will not enter in the channel region under grid structure, metal material may finally be suppressed semiconductor is served as a contrast
The erosion at bottom 100, improves the yield of semiconductor devices.
Then, with continued reference to shown in Figure 12, the amorphous semiconductor material 400 in Figure 11 is removed, so that the shape in source region 110
Into the metal silicide 310c of low-resistance, and on drain region 120 formed low-resistance metal silicide 320c.
Specifically, the amorphous semiconductor material 400 can be removed using wet etching method.It is non-described in the present embodiment
Brilliant semi-conducting material 400 is non-crystalline silicon, so as to molten as wet etching using one kind in TMAH and KOH solution or combination
Liquid is to remove the non-crystalline silicon.
The present embodiment adds between twice annealing process and forms amorphous semiconductor material 400 under cryogenic
Step, so as to when second makes annealing treatment, can make metal material can diffuse in amorphous semiconductor material 400 without
It is to diffuse to source region 110 and drain region 120, erosion of the metal material to Semiconductor substrate 100 may finally be suppressed, improve and partly lead
The yield of body device.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (20)
1. a kind of forming method of amorphous semiconductor material, it is characterised in that including：
Semiconductor preparation layers are formed on a semiconductor substrate, and the forming process of the semiconductor preparation layers is：Lead into reaction chamber
Enter the precursor gas of silicon, the precursor gas absorption of the part silicon forms semiconductor preparation layers in the upper surface of semiconductor base,
The precursor gas of the part silicon is unadsorbed on a semiconductor substrate but in suspended state；Remove the institute in suspended state
State the precursor gas of silicon；
Ultraviolet treatment with irradiation is carried out to the semiconductor preparation layers, until the semiconductor preparation layers are decomposed into amorphous semiconductor
Material and waste gas, the temperature of the ultraviolet treatment with irradiation are less than or equal to 400 DEG C；
The waste gas is removed, the amorphous semiconductor material of individual layer is formed on a semiconductor substrate；
The step of repeating above-mentioned formation semiconductor preparation layers, ultraviolet treatment with irradiation and remove removing exhaust gas, until in the semiconductor
The amorphous semiconductor material of predetermined thickness is formed in substrate.
2. the forming method of amorphous semiconductor material as claimed in claim 1, it is characterised in that the ultraviolet treatment with irradiation
Temperature be more than or equal to 20 DEG C and less than or equal to 300 DEG C.
3. the forming method of amorphous semiconductor material as claimed in claim 1, it is characterised in that the semiconductor preparation layers are adopted
Formed with chemical gaseous phase depositing process.
4. the forming method of amorphous semiconductor material as claimed in claim 3, it is characterised in that the chemical vapor deposition side
The gas that method is used includes：Si2H6、SiH2Cl2And SiH4In one kind or any combination.
5. the forming method of amorphous semiconductor material as claimed in claim 3, it is characterised in that the chemical vapor deposition side
The gas that method is used includes：Ge2H6And GeH4。
6. the forming method of the amorphous semiconductor material as described in claim 4 or 5, it is characterised in that the chemical vapor deposition
The gas that product method is used also includes：Oxygen.
7. the forming method of the amorphous semiconductor material as described in claim 4 or 5, it is characterised in that every kind of gas
Flow is more than or equal to 1sccm and less than or equal to 300sccm.
8. the forming method of amorphous semiconductor material as claimed in claim 3, it is characterised in that form the semiconductor every time
The time of preparation layers is more than or equal to 0.01s and less than or equal to 10s.
9. the forming method of amorphous semiconductor material as claimed in claim 1, it is characterised in that the ultraviolet treatment with irradiation
Power be more than or equal to 10W and less than or equal to 1000W, pressure is more than or equal to 0.1Torr and is less than or equal to
500Torr。
10. the forming method of amorphous semiconductor material as claimed in claim 1, it is characterised in that using in argon gas and hydrogen
One kind or combination remove the waste gas.
11. the forming method of amorphous semiconductor material as claimed in claim 10, it is characterised in that the argon gas and hydrogen
Flow is more than or equal to 1sccm and less than or equal to 1000sccm.
12. the forming method of amorphous semiconductor material as claimed in claim 10, it is characterised in that remove the waste gas every time
Time be more than or equal to 0.1s and less than or equal to 10s.
13. the forming method of amorphous semiconductor material as claimed in claim 1, it is characterised in that carrying out ultraviolet irradiation
While processing, in addition to：Cooling treatment is carried out to the semiconductor base, the temperature of the cooling treatment is more than or equal to 20
DEG C and less than or equal to 300 DEG C.
14. a kind of forming method of metal silicide, it is characterised in that including：
Semiconductor substrate is provided, the Semiconductor substrate includes source region and drain region；
At least metal level is formed in the source region and drain region；
First time annealing is carried out, the temperature of the first time annealing is more than or equal to 200 DEG C and less than or equal to 400
℃；
Form non-on the metal layer using the forming method of the amorphous semiconductor material as any one of claim 1 to 13
Brilliant semi-conducting material；
Carry out second to make annealing treatment, the temperature of second of annealing is more than or equal to 400 DEG C and less than or equal to 700
℃；
Remove the amorphous semiconductor material.
15. the forming method of metal silicide as claimed in claim 14, it is characterised in that the first time annealing
Time is more than or equal to 10s and less than or equal to 20s, and the time of second of annealing is more than or equal to 10s and is less than
Or equal to 20s.
16. the forming method of metal silicide as claimed in claim 14, it is characterised in that the amorphous semiconductor material
Thickness is more than or equal to 10 angstroms and less than or equal to 200 angstroms.
17. the forming method of metal silicide as claimed in claim 14, it is characterised in that removed using wet etching method
The amorphous semiconductor material.
18. the forming method of metal silicide as claimed in claim 17, it is characterised in that the amorphous semiconductor material is
Non-crystalline silicon, the wet etching method uses one kind or combination in TMAH and KOH solution.
19. the forming method of metal silicide as claimed in claim 14, it is characterised in that also wrapped in the Semiconductor substrate
Gate electrode is included, the material of the gate electrode is polysilicon；The forming method of the metal silicide also includes：In the source region and
While forming the metal level on drain region, metal level is formed on the gate electrode；Forming described on the metal level
While amorphous semiconductor material, the amorphous semiconductor material is formed on the metal level on gate electrode simultaneously.
20. the forming method of metal silicide as claimed in claim 14, it is characterised in that the material of the metal level includes
Nickel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310232183.5A CN104241112B (en) | 2013-06-09 | 2013-06-09 | The forming method of amorphous semiconductor material and the forming method of metal silicide |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310232183.5A CN104241112B (en) | 2013-06-09 | 2013-06-09 | The forming method of amorphous semiconductor material and the forming method of metal silicide |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104241112A CN104241112A (en) | 2014-12-24 |
| CN104241112B true CN104241112B (en) | 2017-11-03 |
Family
ID=52228968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310232183.5A Active CN104241112B (en) | 2013-06-09 | 2013-06-09 | The forming method of amorphous semiconductor material and the forming method of metal silicide |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104241112B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101818721B1 (en) * | 2015-03-27 | 2018-02-21 | 에이피시스템 주식회사 | Thin film transistor manufacture apparatus and the method for thin film transistor using it |
| CN104779202B (en) | 2015-04-24 | 2018-11-06 | 京东方科技集团股份有限公司 | A kind of method making array substrate and its array substrate and display device |
| CN108010836A (en) * | 2017-12-12 | 2018-05-08 | 江苏博普电子科技有限责任公司 | The forming method of the short grid low square resistance value grid silicides of RF-LDMOS |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4585671A (en) * | 1982-11-15 | 1986-04-29 | Mitsui Toatsu Chemicals, Incorporated | Formation process of amorphous silicon film |
| CN1727526A (en) * | 2005-03-04 | 2006-02-01 | 中国科学院长春光学精密机械与物理研究所 | The method for preparing microcrystal silicon |
| CN101675180A (en) * | 2007-02-27 | 2010-03-17 | 斯克司聪先进材料公司 | Method for forming a film on a substrate |
-
2013
- 2013-06-09 CN CN201310232183.5A patent/CN104241112B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4585671A (en) * | 1982-11-15 | 1986-04-29 | Mitsui Toatsu Chemicals, Incorporated | Formation process of amorphous silicon film |
| CN1727526A (en) * | 2005-03-04 | 2006-02-01 | 中国科学院长春光学精密机械与物理研究所 | The method for preparing microcrystal silicon |
| CN101675180A (en) * | 2007-02-27 | 2010-03-17 | 斯克司聪先进材料公司 | Method for forming a film on a substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104241112A (en) | 2014-12-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7952088B2 (en) | Semiconducting device having graphene channel | |
| JP5741382B2 (en) | Thin film forming method and film forming apparatus | |
| CN104241112B (en) | The forming method of amorphous semiconductor material and the forming method of metal silicide | |
| CN103187283A (en) | Graphene field-effect-transistor and manufacturing method thereof | |
| KR101321424B1 (en) | Method of surface treatment and thin film growth, and equipment for surface treatment and thin film growth | |
| CN105575790A (en) | Nickel metal silicide preparation method | |
| CN107527803B (en) | The preparation method of SiC device gate dielectric layer and SiC device structure | |
| CN103377887B (en) | Field-effect transistor and preparation method thereof | |
| US20230163197A1 (en) | Semiconductor Device and Method of Manufacture | |
| TWI517265B (en) | Manufacturing method of thin film transistor | |
| CN103377942A (en) | Forming method of semiconductor structure and forming method of transistor | |
| Li et al. | Highly-defective graphene as a metal-free catalyst for chemical vapor deposition growth of graphene glass | |
| CN104217957B (en) | Transistor and forming method thereof | |
| CN105140130A (en) | Low-temperature polycrystalline silicon thin-film transistor and preparation method thereof | |
| CN102569089B (en) | Semiconductor device forming method | |
| JP4852261B2 (en) | Method for forming silicon compound | |
| KR101019710B1 (en) | Method of manufacturing semiconductor device | |
| Slaoui et al. | Polycrystalline silicon films for electronic devices | |
| CN104465346B (en) | The method for forming grid | |
| CN103107068A (en) | Nickel (Ni) film annealing side gate graphene transistor preparation method based on reaction of silicon carbide (SiC) and chlorine gas | |
| TWI520335B (en) | Methods and apparatus for forming semiconductor structures | |
| US20130052820A1 (en) | Method of forming conductive pattern | |
| US10692986B2 (en) | Compound film of tungsten and germanium, and semiconductor device | |
| TWI220568B (en) | Semiconductor manufacturing process for improving crystal defect in epitaxy layer | |
| CN101589463B (en) | Method for fabricating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |