CN104242825A - CMOS down-conversion mixer - Google Patents
CMOS down-conversion mixer Download PDFInfo
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- CN104242825A CN104242825A CN201310237459.9A CN201310237459A CN104242825A CN 104242825 A CN104242825 A CN 104242825A CN 201310237459 A CN201310237459 A CN 201310237459A CN 104242825 A CN104242825 A CN 104242825A
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Abstract
The invention discloses a CMOS down-conversion mixer. The CMOS down-conversion mixer comprises a radio frequency differential input circuit and a switching circuit. Load circuits formed by connecting resistors and PMOS transistors in parallel are connected between the normal phase output end of the switching circuit and a supply voltage and between the reversal phase output end of the switching circuit and the supply voltage; grid electrodes of the PMOS transistors of the load circuits are connected with a first control voltage, and therefore load impedance of the load circuits can be adjusted. Drain electrodes of two NMOS transconductance tubes of the radio frequency differential input circuit are respectively connected with a constant current source, and source electrodes of the NMOS transconductance tubes of the radio frequency differential input circuit are jointly connected with an LC parallel circuit. According to the CMOS down-conversion mixer, gains can be improved and are adjustable, the linearity and the noise performance can be improved, and the working voltage can be reduced.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of CMOS down-conversion mixer.
Background technology
Transceiver radio frequency (RF) front end mainly completes the function of frequency translation in itself, receiver radio frequency front end converts the radiofrequency signal received to baseband signal, and the baseband signal that transmitter radio-frequency front-end will be launched converts radiofrequency signal to, frequency translation function is completed by frequency mixer.Frequency mixer is the important module in radio-frequency (RF) front-end circuit, its a kind of nonlinear circuit, rely on circuit itself non-linear come frequency translation function.Down-conversion mixer is transformed into a lower frequency the RF signal that receives, and is called intermediate frequency (IF).Visible multiplication creates in the frequency of input signal and place and the output signal at difference on the frequency place, and their amplitude is proportional to the product of RF and local oscillation signal (LO) amplitude.Therefore, if LO amplitude is constant, so in RF signal, any which amplitude modulation is all transmitted and is given IF signal.
Ambipolar double balanced mixer (Gilbert multiplier) has good LO-RF, RF-IF, LO-IF port isolation, therefore often adopts this structure in the design.Fig. 1 is the circuit diagram of existing CMOS Gilbert down-conversion mixer; Gilbert multiplier comprises:
The radio-frequency differential input circuit be made up of NMOS tube 101 and NMOS tube 102, the source electrode of NMOS tube 101 and NMOS tube 102 links together also and the current source be made up of NMOS tube 103 links together.NMOS tube 101 and the grid of NMOS tube 102 are connected differential radio frequency voltage signal RFP or RFN respectively.The source ground of NMOS tube 103, grid meets bias voltage Vbiasn.Radio-frequency differential input circuit produces in the drain electrode of NMOS tube 101 and NMOS tube 102 current radio frequency signal comprising the frequency of radio frequency voltage signal RFP or RFN respectively.
The switching circuit be made up of NMOS tube 104, NMOS tube 105, NMOS tube 106 and NMOS tube 107, NMOS tube 104 is all connected with the drain electrode of NMOS tube 101 with the source electrode of NMOS tube 105, NMOS tube 106 is all connected with the drain electrode of NMOS tube 102 with the source electrode of NMOS tube 107, the grid of NMOS tube 104 and NMOS tube 107 all meets a difference local oscillation signal LOP, and the grid of NMOS tube 105 and NMOS tube 106 all meets another difference local oscillation signal LON.NMOS tube 104 is connected with the drain electrode of NMOS tube 106 and as the output of a differential intermediate frequency IFP, and NMOS tube 105 is connected with the drain electrode of NMOS tube 107 and as the output of another differential intermediate frequency IFN.Also be connected with load between the drain electrode of NMOS tube 104 and NMOS tube 106 and power supply, between the drain electrode of NMOS tube 105 and NMOS tube 107 and power supply, be also connected with load.The frequency of differential intermediate frequency is the difference on the frequency of difference local oscillation signal and differential radio frequency voltage signal.
Existing CMOS Gilbert down-conversion mixer is as shown in Figure 1 compared single balance mixer, isolation performance is good, especially local oscillator improves to some extent to the isolation performance of intermediate frequency port, that the range of linearity is larger in addition, but along with further developing and the expansion of application of technique, more application demand is proposed to the performance of frequency mixer, objectively requires more high performance frequency mixer.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of CMOS down-conversion mixer, can improve gain and realize adjustable gain, can improve the linearity and noiseproof feature, can reduce operating voltage.
For solving the problems of the technologies described above, CMOS down-conversion mixer provided by the invention comprises:
Radio-frequency differential input circuit, comprise the first NMOS tube and the second NMOS tube, described first NMOS tube is also connected two differential radio frequency voltage signals with the grid of described second NMOS tube respectively as two rf inputs, the source electrode of described first NMOS tube and described second NMOS tube links together, the drain electrode of described first NMOS tube and described second NMOS tube as described radio-frequency differential input circuit two outputs and export the two-pass DINSAR current radio frequency signal identical with described differential radio frequency voltage signal frequency respectively.
Switching circuit, described switching circuit comprises two symmetries and is the first switching branches of fully differential structure and second switch branch road, described first switching branches is connected two difference local oscillation signals all respectively with the control end of described second switch branch road, the input of described first switching branches connects the drain electrode of described first NMOS tube, the input of described second switch branch road connects the drain electrode of described second NMOS tube, the positive output end of described first switching branches and described second switch branch road links together and exports the positive phase signals of difference voltage intermediate frequency signal, the reversed-phase output of described first switching branches and described second switch branch road links together and exports the inversion signal of difference voltage intermediate frequency signal.
Be connected with the first load circuit between the positive output end of described first switching branches and described second switch branch road and supply voltage, between the reversed-phase output of described first switching branches and described second switch branch road and supply voltage, have the second load circuit.
Described first load circuit is formed in parallel by the first resistance and the first PMOS, described first resistance is connected with the drain electrode of described first PMOS and connects the positive output end of two described switching branches, and described first resistance is connected with the source electrode of described first PMOS and connects supply voltage.
Described second load circuit is formed in parallel by the second resistance and the second PMOS, described second resistance is connected with the drain electrode of described second PMOS and connects the reversed-phase output of two described switching branches, and described second resistance is connected with the source electrode of described second PMOS and connects supply voltage.
Described first resistance is identical with the resistance of described second resistance, described first PMOS is identical with the structure of described second PMOS, described first PMOS is all connected the first control voltage with the grid of described second PMOS, by regulating the load of the first load circuit and described second load circuit described in the size adjustment of described first control voltage, realize the gain-adjusted of described CMOS down-conversion mixer.
Further improvement is, CMOS down-conversion mixer also comprises: the first constant-current source, between the drain electrode being connected to described first NMOS tube and supply voltage, described first constant-current source is used for releasing to the direct current of described first NMOS tube, reduces described first switching branches electric current; Second constant-current source, between the drain electrode being connected to described second NMOS tube and supply voltage; Described second constant-current source is used for releasing to the direct current of described second NMOS tube, reduces described second switch branch current.
Further improvement is, described first constant-current source is made up of the 3rd PMOS, and the drain electrode of described 3rd PMOS connects the drain electrode of described first NMOS tube, and the source electrode of described 3rd PMOS connects supply voltage; Described second constant-current source is made up of the 4th PMOS, and the drain electrode of described 4th PMOS connects the drain electrode of described second NMOS tube, and the source electrode of described 4th PMOS connects supply voltage; Described 3rd PMOS is connected identical bias voltage with the grid of described 4th PMOS.
Further improvement is, described radio-frequency differential input circuit also comprises a LC parallel circuits, described LC parallel circuits is formed by the first electric capacity and the first inductance in parallel, described first electric capacity links together with the first end of described first inductance and is connected the source electrode of described first NMOS tube and described second NMOS tube, and the second end of described first electric capacity and described first inductance links together and ground connection.
Further improvement is, described switching circuit comprises the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube.
Described first switching branches is made up of described 3rd NMOS tube and described 4th NMOS tube, and described second switch props up the 5th NMOS tube described in route and described 6th NMOS tube composition.
Described 3rd NMOS tube is connected with the source electrode of described 4th NMOS tube and is connected the drain electrode of described first NMOS tube; Described 5th NMOS tube is connected with the source electrode of described 6th NMOS tube and is connected the drain electrode of described second NMOS tube; The source electrode of described 3rd NMOS tube and described 4th NMOS tube is as the input of described first switching branches, and the source electrode of described 5th NMOS tube and described 6th NMOS tube is as the input of described second switch branch road.
Described 3rd NMOS tube and the grid of described 6th NMOS tube are all connected an identical described difference local oscillation signal, and described 4th NMOS tube and the grid of described 5th NMOS tube are all connected difference local oscillation signal described in identical another; The control end of described first switching branches of grid composition of described 3rd NMOS tube and described 4th NMOS tube, the grid of described 5th NMOS tube and described 6th NMOS tube forms the control end of described second switch branch road.
The drain electrode of described 3rd NMOS tube and described 5th NMOS tube links together and exports the positive phase signals of described difference voltage intermediate frequency signal, and the drain electrode of described 4th NMOS tube and described 6th NMOS tube links together and exports the inversion signal of described difference voltage intermediate frequency signal; The drain electrode of described 3rd NMOS tube and described 5th NMOS tube is respectively as the positive output end of described first switching branches and described second switch branch road, and the drain electrode of described 4th NMOS tube and described 6th NMOS tube is respectively as the reversed-phase output of described first switching branches and described second switch branch road.
The present invention can obtain following beneficial effect:
1, the present invention passes through the setting of the first load circuit and the second load circuit formed by resistance and PMOS parallel connection, operating state and the resistance value of PMOS can be regulated by the first control voltage be arranged on the grid of PMOS, thus the resistance value of whole first load circuit or the second load circuit can be regulated, thus the adjustable gain of realizing circuit.
2, the present invention passes through the setting of the first constant-current source and the second constant-current source, can under the constant condition of the electric current of two of a radio-frequency differential input circuit NMOS tube, reduce the electric current of each transistor of switching circuit, thus the overdrive voltage of the local oscillation signal of switching circuit can be reduced, thus effectively can improve the voltage conversion gain of circuit and promote the headroom voltage of circuit.
3, the present invention is by the setting of LC parallel circuits, higher radio-frequency (RF) impedance can be provided thus the linearity of circuit can be improved, LC parallel circuits does not consume extra direct current pressure drop and does not introduce significant noise simultaneously, thus can improve the noiseproof feature of circuit, and can reduce the operating voltage of circuit.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the circuit diagram of existing ambipolar two balance CMOS down-conversion mixer;
Fig. 2 is the circuit diagram of embodiment of the present invention CMOS down-conversion mixer.
Embodiment
As shown in Figure 2, be the circuit diagram of embodiment of the present invention CMOS down-conversion mixer, embodiment of the present invention CMOS down-conversion mixer comprises:
Radio-frequency differential input circuit, be made up of the first NMOS tube MN1 and the second NMOS tube MN2, described first NMOS tube MN1 is also connected two differential radio frequency voltage signal RFP and RFN with the grid of described second NMOS tube MN2 respectively as two rf inputs, the source electrode of described first NMOS tube MN1 and described second NMOS tube MN2 links together, the drain electrode of described first NMOS tube MN1 and described second NMOS tube MN2 as described radio-frequency differential input circuit two outputs and export the two-pass DINSAR current radio frequency signal identical with RFN frequency with described differential radio frequency voltage signal RFP respectively.
Described radio-frequency differential input circuit also comprises a LC parallel circuits, described LC parallel circuits is formed in parallel by the first electric capacity C and the first inductance L, described first electric capacity C links together with the first end of described first inductance L and is connected the source electrode of described first NMOS tube MN1 and described second NMOS tube MN2, and the second end of described first electric capacity C and described first inductance L links together and ground connection.
Switching circuit, described switching circuit comprises two symmetries and is the first switching branches of fully differential structure and second switch branch road.Described first switching branches is made up of the 3rd NMOS tube MN3 and the 4th NMOS tube MN4, and described second switch props up route the 5th NMOS tube MN5 and the 6th NMOS tube MN6 and forms.
Described 3rd NMOS tube MN3 is connected with the source electrode of described 4th NMOS tube MN4 and is connected the drain electrode of described first NMOS tube MN1; Described 5th NMOS tube MN5 is connected with the source electrode of described 6th NMOS tube MN6 and is connected the drain electrode of described second NMOS tube MN2; The source electrode of described 3rd NMOS tube MN3 and described 4th NMOS tube MN4 is as the input of described first switching branches, and the source electrode of described 5th NMOS tube MN5 and described 6th NMOS tube MN6 is as the input of described second switch branch road.
Described 3rd NMOS tube MN3 and the grid of described 6th NMOS tube MN6 are all connected an identical described difference local oscillation signal LOP, and described 4th NMOS tube MN4 and the grid of described 5th NMOS tube MN5 are all connected difference local oscillation signal LON described in identical another; The control end of described first switching branches of grid composition of described 3rd NMOS tube MN3 and described 4th NMOS tube MN4, the grid of described 5th NMOS tube MN5 and described 6th NMOS tube MN6 forms the control end of described second switch branch road.
The drain electrode of described 3rd NMOS tube MN3 and described 5th NMOS tube MN5 links together and exports the positive phase signals IFP of described difference voltage intermediate frequency signal, and the drain electrode of described 4th NMOS tube MN4 and described 6th NMOS tube MN6 links together and exports the inversion signal IFN of described difference voltage intermediate frequency signal; The drain electrode of described 3rd NMOS tube MN3 and described 5th NMOS tube MN5 is respectively as the positive output end of described first switching branches and described second switch branch road, and the drain electrode of described 4th NMOS tube MN4 and described 6th NMOS tube MN6 is respectively as the reversed-phase output of described first switching branches and described second switch branch road.
Be connected with the first load circuit between the positive output end of described first switching branches and described second switch branch road and supply voltage AVDD, between the reversed-phase output of described first switching branches and described second switch branch road and supply voltage AVDD, have the second load circuit.
Described first load circuit is formed in parallel by the first resistance RL1 and the first PMOS MP1, described first resistance RL1 is connected with the drain electrode of described first PMOS MP1 and connects the positive output end of two described switching branches, and described first resistance RL1 is connected with the source electrode of described first PMOS MP1 and meets supply voltage AVDD.
Described second load circuit is formed in parallel by the second resistance RL2 and the second PMOS MP2, described second resistance RL2 is connected with the drain electrode of described second PMOS MP2 and connects the reversed-phase output of two described switching branches, and described second resistance RL2 is connected with the source electrode of described second PMOS MP2 and meets supply voltage AVDD.
Described first resistance RL1 is identical with the resistance of described second resistance RL2, described first PMOS MP1 is identical with the structure of described second PMOS MP2, described first PMOS MP1 is connected the first control voltage Vc with the grid of described second PMOS MP2, described first control voltage Vc can control operating state and the resistance sizes of described first PMOS MP1 and described second PMOS MP2, so the load by regulating the size of described first control voltage Vc can regulate described first load circuit and described second load circuit, realize the gain-adjusted of described CMOS down-conversion mixer.
CMOS down-conversion mixer also comprises: the first constant-current source, between the drain electrode being connected to described first NMOS tube MN1 and supply voltage AVDD, described first constant-current source is used for releasing to the direct current of described first NMOS tube MN1, reduces described first switching branches electric current; Second constant-current source, between the drain electrode being connected to described second NMOS tube MN2 and supply voltage AVDD; Described second constant-current source is used for releasing to the direct current of described second NMOS tube MN2, reduces described second switch branch current.Be preferably, described first constant-current source is made up of the 3rd PMOS MP3, and the drain electrode of described 3rd PMOS MP3 connects the drain electrode of described first NMOS tube MN1, and the source electrode of described 3rd PMOS MP3 connects supply voltage AVDD; Described second constant-current source is made up of the 4th PMOS MP4, and the drain electrode of described 4th PMOS MP4 connects the drain electrode of described second NMOS tube MN2, and the source electrode of described 4th PMOS MP4 connects supply voltage AVDD; Described 3rd PMOS MP3 is connected identical bias voltage with the grid of described 4th PMOS MP4.
Frequency mixer is the important module in radio-frequency (RF) front-end circuit, and it is a kind of nonlinear circuit, rely on circuit itself non-linear come frequency translation function.Down-conversion mixer is transformed into lower intermediate frequency (IF) signal of a frequency the radio frequency received (RF) signal.The amplitude of intermediate-freuqncy signal is proportional to the product of RF signal and local oscillator (LO) signal amplitude.Therefore, if LO signal amplitude is constant, so in RF signal, any which amplitude modulation is all transmitted and is given IF signal.The usual better performances of frequency mixer based on multiplication function, in addition because the input of the two-way of frequency mixer and road output are connected to three ports, respectively so the isolation between three signals and RF, LO, IF signal is better.Because CMOS can work on off state preferably, the multiplier of the excellent performance based on switch can be realized.Assuming that the transistor that local oscillator drives is in switching over state completely, the conversion gain of frequency mixer so can be obtained.Based on above-mentioned hypothesis, in the embodiment of the present invention, differential output current can think that the leakage current of the first NMOS tube MN1 and the second NMOS tube MN2 is multiplied by the result of unit amplitude square wave.If output is connected to load resistance RL, so voltage conversion gain is
Known by formula (1), if the gain of frequency mixer will be improved, the mutual conductance radio frequency input pipe i.e. mutual conductance g of the first NMOS tube MN1 and the second NMOS tube MN2 can be improved
m, load resistance RL, local oscillation signal amplitude V
lO, reduce the overdrive voltage i.e. (V of switching tube i.e. the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5 and the 6th NMOS tube MN6
gs-V
t)
sw.But improve mutual conductance g
mneed to consume power consumption, electric current increase can affect noise; The amplitude V of local oscillation signal
lOexcessive, switch tube is to the parasitic capacitance discharge and recharge of the i.e. common source node of the first switching branches or second switch branch road, and large local oscillation signal also easily causes leakage, so by improving mutual conductance g
mwith local oscillation signal amplitude V
lOmethod improve gain and all have a negative impact.By improving two constant-current sources be made up of the 3rd PMOS M3 and the 4th PMOS M4 in the embodiment of the present invention, when the first NMOS tube MN1 and the second NMOS tube MN2 electric current constant, flow through the electric current reduction that switching tube is right, overdrive voltage (V
gs-V
t)
swreduce, and the size constancy of switching tube, parasitic capacitance is constant, helpful to improving gain when not causing large parasitism like this, simultaneously favourable to alleviation headroom voltage.
In the embodiment of the present invention, more direct effective method is that the method for the size changing load resistance RL is to realize the adjustment of voltage conversion gain, as shown in Figure 2, load resistance RL in the embodiment of the present invention is the first load circuit and the second load circuit, wherein said first load circuit is formed in parallel by the first resistance RL1 and the first PMOS MP1, second load circuit is formed in parallel by the second resistance RL2 and the second PMOS MP2, by the first control voltage Vc regulating described first PMOS MP1 to be connected with the grid of described second PMOS MP2, operating state and the resistance sizes of described first PMOS MP1 and described second PMOS MP2 can be controlled, thus the load of described first load circuit and described second load circuit can be regulated, realize the gain-adjusted of described CMOS down-conversion mixer.
In addition, in the embodiment of the present invention, radio-frequency differential input circuit also comprises a LC parallel circuits, does not consume extra direct current pressure drop and does not introduce significant noise while that LC parallel circuits improving radio-frequency (RF) impedance thus improve the linearity.
Than traditional Gilbert frequency mixer, embodiment of the present invention circuit requires to reduce to supply voltage, provides variable gain selection, achieves the good linearity and noiseproof feature simultaneously.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (5)
1. a CMOS down-conversion mixer, is characterized in that, comprising:
Radio-frequency differential input circuit, comprises the first NMOS tube and the second NMOS tube; Described first NMOS tube is also connected two differential radio frequency voltage signals with the grid of described second NMOS tube respectively as two rf inputs, the source electrode of described first NMOS tube and described second NMOS tube links together, the drain electrode of described first NMOS tube and described second NMOS tube as described radio-frequency differential input circuit two outputs and export the two-pass DINSAR current radio frequency signal identical with described differential radio frequency voltage signal frequency respectively;
Switching circuit, described switching circuit comprises two symmetries and is the first switching branches of fully differential structure and second switch branch road, described first switching branches is connected two difference local oscillation signals all respectively with the control end of described second switch branch road, the input of described first switching branches connects the drain electrode of described first NMOS tube, the input of described second switch branch road connects the drain electrode of described second NMOS tube, the positive output end of described first switching branches and described second switch branch road links together and exports the positive phase signals of difference voltage intermediate frequency signal, the reversed-phase output of described first switching branches and described second switch branch road links together and exports the inversion signal of difference voltage intermediate frequency signal,
Be connected with the first load circuit between the positive output end of described first switching branches and described second switch branch road and supply voltage, between the reversed-phase output of described first switching branches and described second switch branch road and supply voltage, have the second load circuit;
Described first load circuit is formed in parallel by the first resistance and the first PMOS, described first resistance is connected with the drain electrode of described first PMOS and connects the positive output end of two described switching branches, and described first resistance is connected with the source electrode of described first PMOS and connects supply voltage;
Described second load circuit is formed in parallel by the second resistance and the second PMOS, described second resistance is connected with the drain electrode of described second PMOS and connects the reversed-phase output of two described switching branches, and described second resistance is connected with the source electrode of described second PMOS and connects supply voltage;
Described first resistance is identical with the resistance of described second resistance, described first PMOS is identical with the structure of described second PMOS, described first PMOS is all connected the first control voltage with the grid of described second PMOS, by regulating the load of the first load circuit and described second load circuit described in the size adjustment of described first control voltage, realize the gain-adjusted of described CMOS down-conversion mixer.
2. CMOS down-conversion mixer as claimed in claim 1, is characterized in that, also comprise:
First constant-current source, between the drain electrode being connected to described first NMOS tube and supply voltage, described first constant-current source is used for releasing to the direct current of described first NMOS tube, reduces described first switching branches electric current;
Second constant-current source, between the drain electrode being connected to described second NMOS tube and supply voltage; Described second constant-current source is used for releasing to the direct current of described second NMOS tube, reduces described second switch branch current.
3. CMOS down-conversion mixer as claimed in claim 2, is characterized in that:
Described first constant-current source is made up of the 3rd PMOS, and the drain electrode of described 3rd PMOS connects the drain electrode of described first NMOS tube, and the source electrode of described 3rd PMOS connects supply voltage;
Described second constant-current source is made up of the 4th PMOS, and the drain electrode of described 4th PMOS connects the drain electrode of described second NMOS tube, and the source electrode of described 4th PMOS connects supply voltage;
Described 3rd PMOS is connected identical bias voltage with the grid of described 4th PMOS.
4. CMOS down-conversion mixer as claimed in claim 1, it is characterized in that: described radio-frequency differential input circuit also comprises a LC parallel circuits, described LC parallel circuits is formed by the first electric capacity and the first inductance in parallel, described first electric capacity links together with the first end of described first inductance and is connected the source electrode of described first NMOS tube and described second NMOS tube, and the second end of described first electric capacity and described first inductance links together and ground connection.
5. CMOS down-conversion mixer as claimed in claim 1, is characterized in that: described switching circuit comprises the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube;
Described first switching branches is made up of described 3rd NMOS tube and described 4th NMOS tube, and described second switch props up the 5th NMOS tube described in route and described 6th NMOS tube composition;
Described 3rd NMOS tube is connected with the source electrode of described 4th NMOS tube and is connected the drain electrode of described first NMOS tube; Described 5th NMOS tube is connected with the source electrode of described 6th NMOS tube and is connected the drain electrode of described second NMOS tube; The source electrode of described 3rd NMOS tube and described 4th NMOS tube is as the input of described first switching branches, and the source electrode of described 5th NMOS tube and described 6th NMOS tube is as the input of described second switch branch road;
Described 3rd NMOS tube and the grid of described 6th NMOS tube are all connected an identical described difference local oscillation signal, and described 4th NMOS tube and the grid of described 5th NMOS tube are all connected difference local oscillation signal described in identical another; The control end of described first switching branches of grid composition of described 3rd NMOS tube and described 4th NMOS tube, the grid of described 5th NMOS tube and described 6th NMOS tube forms the control end of described second switch branch road;
The drain electrode of described 3rd NMOS tube and described 5th NMOS tube links together and exports the positive phase signals of described difference voltage intermediate frequency signal, and the drain electrode of described 4th NMOS tube and described 6th NMOS tube links together and exports the inversion signal of described difference voltage intermediate frequency signal; The drain electrode of described 3rd NMOS tube and described 5th NMOS tube is respectively as the positive output end of described first switching branches and described second switch branch road, and the drain electrode of described 4th NMOS tube and described 6th NMOS tube is respectively as the reversed-phase output of described first switching branches and described second switch branch road.
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| CN106026928B (en) * | 2016-05-13 | 2018-09-07 | 东南大学 | A kind of low-voltage singly balanced current multiplexing passive frequency mixer |
| CN110504956A (en) * | 2019-07-05 | 2019-11-26 | 加驰（厦门）微电子股份有限公司 | A kind of broadband pre-divider that power consumption is adaptive |
| CN114785287A (en) * | 2022-06-17 | 2022-07-22 | 成都旋极星源信息技术有限公司 | Transmitter circuit and electronic equipment |
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| CN104242825B (en) | 2017-12-05 |
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