CN104377136A - Fin type field effect transistor structure and manufacturing method thereof - Google Patents
Fin type field effect transistor structure and manufacturing method thereof Download PDFInfo
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- CN104377136A CN104377136A CN201310360739.9A CN201310360739A CN104377136A CN 104377136 A CN104377136 A CN 104377136A CN 201310360739 A CN201310360739 A CN 201310360739A CN 104377136 A CN104377136 A CN 104377136A
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- 230000005669 field effect Effects 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000000463 material Substances 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 29
- 230000004888 barrier function Effects 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 5
- 238000009832 plasma treatment Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 6
- 230000004044 response Effects 0.000 abstract description 5
- 239000007772 electrode material Substances 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 67
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
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- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- 230000005684 electric field Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
Abstract
The invention provides a fin type field effect transistor structure and a manufacturing method thereof. The fin type field effect transistor structure comprises a substrate, a second gate dielectric layer and a pair of side walls. A first grid electrode and a second grid electrode which are separate are arranged in the substrate in a concave mode. The second gate dielectric layer is in a strip shape and covers the first grid electrode and the second grid electrode. A second grid electrode material layer is formed on the middle zone of the second gate dielectric layer. The second grid electrode material layer and the second gate dielectric layer below form a third grid electrode. The side walls are formed on the two longitudinal-opposite side walls of the second gate dielectric layer. A source electrode zone and a drain electrode zone are formed in the substrate on the two sides of the side walls. The fin type field effect transistor structure is provided with three independent grid electrodes, different voltages can be added to the three grid electrodes respectively for controlling a channel, operation is flexible, higher current and quicker response speed can be obtained, the performance of the transistor structure is effectively improved, the channel is placed in the substrate, technology difficulty is lowered, and cost is saved.
Description
Technical field
The invention belongs to field of semiconductor manufacture, relate to a kind of transistor, particularly relate to a kind of fin formula field effect transistor structure and preparation method thereof.
Background technology
Current semiconductor manufacturing industry develops rapidly under the guidance of Moore's Law, constantly improves performance and the integration density of integrated circuit, reduces the power consumption of integrated circuit as much as possible simultaneously.Therefore, the ultrashort channel device of preparation high-performance, low-power consumption will become the manufacturing focus of future semiconductor.For complete depletion type transistor, in order to obtain the ideal sub-threshold gradients of transistor, the thickness of silicon main body must be about 1/3rd of transistor gate length.But reduce along with grid length, the demand as far as possible reducing silicon film thickness becomes more and more unactual, because the processing that thickness is less than the silicon fiml of 10 nanometers is extremely difficult.On the one hand, the consistency that the magnitude of a nanometer obtains wafer is abnormal difficult, and on the other hand, thin silicon films is easy to be consumed in follow-up various cleaning procedures, follow-up source-drain electrode is grown and becomes extremely difficult.
There is the fin semiconductor device of double grid or multi-gate structure at present, can solve the problem to a certain extent.In general, double-gated devices has electrode in raceway groove both sides, so the thickness of silicon main body can be the twice of single grid, and still can obtain complete depletion type transistor; Multi-gate structure in like manner.Pass through multi-gate structure, the control ability of grid for raceway groove can be strengthened very well, make electric field line be difficult to directly arrive source through raceway groove from drain terminal, so just significantly can improve and leak to potential barrier reduction effect, reduce leakage current, and well suppress short-channel effect.In addition, channel region does not need as conventional planar field-effect transistor, to carry out heavy doping to suppress short-channel effect, the advantage of light dope channel region is to reduce the mobility that scattering brings and declines, thus the mobility of multi-gate structure device is significantly improved.Fin formula field effect transistor as a kind of new construction device, very potential alternative conventional planar field-effect transistor.
Current fin formula field effect transistor structure has following shortcoming: (1) technological requirement is high, because form strip fin to need to etch away substrate surface major part material, only leave very little strip fin structure, technology difficulty is higher, usually also need by regrowth to obtain the fin structure of ideal form after etching, technique relative complex; (2) two or more grid can only add identical voltage, operating flexibility is not high, is unfavorable for the performance improving transistor further.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of fin formula field effect transistor structure and preparation method thereof, for solving the problem that in prior art, fin formula field effect transistor structural manufacturing process is complicated, operating flexibility is not high.
For achieving the above object and other relevant objects, the invention provides a kind of manufacture method of fin formula field effect transistor structure, at least comprise the following steps:
S1 a: substrate is provided, the first grid that recessed formation is discrete in described substrate and second grid; Described first grid and second grid include first grid material layer and surround the first grid dielectric layer of described first grid material layer sidewall and bottom; Described first grid and second grid upper surface flush with described substrate top surface;
S2: form the list structure that covers described first grid and second grid over the substrate; Described strip structure comprises second gate dielectric layer and second grid material layer from bottom to top successively;
S3: form a side wall respectively on two sides that described list structure is longitudinally relative; Then in the substrate of a pair side wall both sides, source region and drain region is formed respectively;
S4: etch described strip structure two ends until exposed portion second gate dielectric layer upper surface; After etching, the second gate dielectric layer of remaining second grid material layer and below thereof forms the 3rd grid;
S5: form insulating barrier and carry out polishing until described insulating barrier upper surface flushes with described 3rd gate upper surface in the structure that step S4 obtains; Finally above described first grid, second grid, source region and drain region, form contact hole respectively.
Alternatively, described first grid and second grid being projected as in the horizontal plane is square, and altitude range is 20nm ~ 60nm, and width range is 10nm ~ 30nm.
Alternatively, longitudinal width of described 3rd grid is more than or equal to longitudinal width of described first grid and second grid.
Alternatively, the transverse width of described 3rd grid is less than or equal to the spacing of described first grid and second grid.
Alternatively, described source region and drain region are formed by doping, and the degree of depth of doping is less than or equal to the height of described first grid and second grid.
Alternatively, in described step S1, form first grid and second grid before also comprise the step of described substrate being carried out to plasma treatment; Described plasma comprise in N, F or Ar one or more.
Alternatively, described substrate is Si substrate or SOI substrate.
The present invention also provides a kind of fin formula field effect transistor structure, comprising:
Substrate, recessedly in described substrate is formed with discrete first grid and second grid; Described first grid and second grid include first grid material layer and surround the first grid dielectric layer of described first grid material layer sidewall and bottom; Described first grid and second grid upper surface flush with described substrate top surface;
Second gate dielectric layer, described second gate dielectric layer is strip and covers described first grid and second grid; Described second gate dielectric layer zone line is formed with second grid material layer, and the second gate dielectric layer of described second grid material layer and below thereof forms the 3rd grid;
A pair side wall, be formed on the longitudinal relative two side of described second gate dielectric layer and the longitudinal relative two side of described second grid material layer, described side wall upper surface flushes with described 3rd gate upper surface; Source region and drain region is formed respectively in the substrate of described side wall both sides;
Insulating barrier, described insulating barrier is formed at the second gate dielectric layer surface at described 3rd grid two ends, surface, described source region and surface, described drain region; Described insulating barrier upper surface flushes with described 3rd gate upper surface; Contact hole is formed above described first grid, second grid, source electrode and drain region.
Alternatively, longitudinal width of described 3rd grid is more than or equal to longitudinal width of described first grid and second grid.
Alternatively, the transverse width of described 3rd grid is less than or equal to the spacing of described first grid and second grid.
As mentioned above, fin formula field effect transistor structure of the present invention and preparation method thereof, there is following beneficial effect: fin formula field effect transistor structure of the present invention has three independently grids, different voltage can be added respectively on three grids to control raceway groove, obtain larger electric current and response speed faster, effectively promote the performance of transistor arrangement; Fin formula field effect transistor raceway groove of the present invention is arranged in substrate, without the need to etching away a large amount of substrates during making, because this reducing etch period, having saved cost, and reduces technology difficulty.
Accompanying drawing explanation
Fig. 1 is shown as the process chart of the manufacture method of fin formula field effect transistor structure of the present invention.
The manufacture method that Fig. 2 is shown as fin formula field effect transistor structure of the present invention on substrate, form mask and graphical after cross-sectional view.
Fig. 3 is shown as the vertical view of structure shown in Fig. 2.
Fig. 4 is shown as the manufacture method etched substrate formation groove of fin formula field effect transistor structure of the present invention and the cross-sectional view after trenched side-wall and bottom form first grid dielectric layer.
Fig. 5 is shown as the vertical view of structure shown in Fig. 4.
Fig. 6 is shown as the cross-sectional view after the manufacture method formation first grid material layer of fin formula field effect transistor structure of the present invention.
The manufacture method that Fig. 7 is shown as fin formula field effect transistor structure of the present invention forms the cross-sectional view after first grid and second grid.
Fig. 8 is shown as the vertical view of structure shown in Fig. 7.
Fig. 9 is shown as the cross-sectional view after the manufacture method formation one covering first grid of fin formula field effect transistor structure of the present invention and the list structure of second grid.
Figure 10 is shown as the vertical view of structure shown in Fig. 9.
Structure vertical view after the manufacture method that Figure 11 is shown as fin formula field effect transistor structure of the present invention forms side wall on two sides that list structure is longitudinally relative.
The manufacture method that Figure 12 is shown as fin formula field effect transistor structure of the present invention forms the structure vertical view behind source region and drain region.
Figure 13 is shown as the structure vertical view after manufacture method formation the 3rd grid of fin formula field effect transistor structure of the present invention.
Figure 14 is shown as the generalized section of structure shown in Figure 13.
Figure 15 is shown as the cross-sectional view after the manufacture method formation insulating barrier of fin formula field effect transistor structure of the present invention.
Figure 16 is shown as the vertical view of structure shown in Figure 15.
Figure 17 is shown as the cross-sectional view of fin formula field effect transistor structure of the present invention.
Figure 18 is shown as the vertical view of structure shown in Figure 17.
Element numbers explanation
S1 ~ S5 step
1 substrate
2 masks
3 grooves
4 first grid dielectric layers
5 first grid material layers
6 first grids
7 second grids
8 second gate dielectric layers
9 second grid material layers
10 side walls
11 source regions
12 drain regions
13 the 3rd grids
14 insulating barriers
15 contact holes
D
1the height of first grid
D
2the width of first grid
D
3longitudinal width of first grid
D
4the spacing of first grid and second grid
D
5longitudinal width of the 3rd grid
D
6the transverse width of the 3rd grid
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 to Figure 18.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment 1
Refer to Fig. 1, be shown as the process chart of the manufacture method of fin formula field effect transistor structure of the present invention, the manufacture method of fin formula field effect transistor structure of the present invention at least comprises the following steps:
Step S1, provides a substrate, the first grid that recessed formation is discrete in described substrate and second grid; Described first grid and second grid include first grid material layer and surround the first grid dielectric layer of described first grid material layer sidewall and bottom; Described first grid and second grid upper surface flush with described substrate top surface.
Concrete, described substrate can be any known Semiconductor substrate, includes but not limited to Si substrate or SOI substrate.Substrate described in the present embodiment is described for Si substrate.Refer to Fig. 2, as shown in the figure, form a mask 2 by conventional methods such as chemical vapour deposition (CVD)s first on substrate 1, then at graphical described mask 2, in described mask 2, form two grooves 3.Described mask 2 can be photoresist or hard mask, is preferably hard mask, is conducive to being formed more even curface in the present embodiment.The material of described hard mask includes but not limited to SiN.Refer to Fig. 3, be shown as the vertical view of structure shown in Fig. 2.
Refer to Fig. 4, as shown in the figure, after graphical described mask 2, the basis of this mask etches described substrate 1, in substrate 1 under described groove 3 region, etchback goes out the groove that two are respectively used to be formed first grid and second grid, then on the sidewall and bottom of described groove, forms first grid dielectric layer 4.The material of described first grid dielectric layer 4 includes but not limited to conventional oxide or high K dielectric, high K dielectric a kind ofly replaces the material of silicon dioxide as gate medium, it possesses good insulation attribute, can produce higher field effect between grid and silicon bottom passage, high K dielectric material comprises ZrO simultaneously
2, HfO
2, Al
2o
3, one or more in HfSiO, HfSiON.Substrate described in the present embodiment adopts Si substrate to be described, and can directly be oxidized described trenched side-wall and bottom, forms silica first grid dielectric layer 4.For the substrate 1 for other material, the methods such as deposition also can be adopted to form described first grid dielectric layer 4.Refer to Fig. 5, be shown as the vertical view of structure shown in Fig. 4.
Refer to Fig. 6, as shown in the figure, fill first grid material layer 5 in the trench, the material of described first grid material layer 5 includes but not limited to polysilicon or metal material, for polysilicon in the present embodiment.After forming described first grid material layer 5, the methods such as chemico-mechanical polishing are adopted to remove the outer unnecessary first grid material layer material of described groove and mask, thus form first grid and second grid, refer to Fig. 7, be shown as the generalized section of said structure, as shown in the figure, described first grid 6 and second grid 7 discrete and to be recessedly formed in described substrate 1.Described first grid 6 and second grid 7 include first grid material layer 5 and surround the first grid dielectric layer 4 of described first grid material layer 5 sidewall and bottom; Described first grid 6 and second grid 7 upper surface and described substrate 1 upper surface flush.In the present embodiment, described first grid 6 and second grid 7 being projected as in the horizontal plane is square, and as shown in Figure 7, the height of first grid is d
1, the width of first grid is d
2, wherein d
1span be 20nm ~ 60nm, d
2span be 10nm ~ 30nm, height and the width range of described second grid 7 and described first grid 6 are identical.Refer to Fig. 8, be shown as the vertical view of structure shown in Fig. 7, there is shown longitudinal width d of first grid
3and the spacing d of first grid and second grid
4.In the present embodiment, described second grid 7 and first grid 6 have identical longitudinal width.
Concrete, plasma treatment can also be carried out to described substrate 1 before formation first grid 6 and second grid 7, described plasma comprise in N, F or Ar one or more, its effect utilizes ionic state and the unsaturated state of substrate surface carry out chemical reaction thus reduce substrate surface dangling bonds, improves device reliability.
Step S2, refers to Fig. 9 to Figure 10, forms the list structure that covers described first grid and second grid over the substrate; Described strip structure comprises second gate dielectric layer and second grid material layer from bottom to top successively.
First refer to Fig. 9, be shown as the cross-sectional view of said structure, described strip structure comprises second gate dielectric layer 8 and second grid material layer 9 formed thereon.The material of described second gate dielectric layer 8 includes but not limited to oxide or high K dielectric.The material of described second grid material layer 9 includes but not limited to polysilicon or metal.For the situation that described substrate 1 is Si substrate, the forming process of described strip structure can be first all be oxidized by the structure upper surface that step S1 obtains, and then deposits second grid material layer, then is patterned and obtains described strip structure.Refer to Figure 10, be shown as the vertical view of structure shown in Fig. 9, as shown in the figure, described strip structure covers described first grid 6 and second grid 7.
Step S3, refers to Figure 11 to Figure 12, and two sides that described list structure is longitudinally relative form a side wall respectively; Then in the substrate of a pair side wall both sides, source region and drain region is formed respectively.
First refer to Figure 11, as shown in the figure, two sides that described strip structure is longitudinally relative are formed with side wall 10 respectively, and the material of described side wall 10 includes but not limited to SiN, and described side wall is by deposit and the common process such as etching is formed.Refer to Figure 12 again, as shown in the figure, in the substrate of a pair side wall 10 both sides, be formed with source region 11 and drain region 12 respectively.Concrete, described source region 11 and drain region 12 are by formation of adulterating in the substrate, and the degree of depth of doping is less than or equal to the height of described first grid 6 and second grid 7, and channel region can be made to be formed between described first grid and second grid.
It is to be noted, the transverse width of described source region and described drain region is more than or equal to the spacing between described first grid and second grid, be preferably greater than the spacing between described first grid and second grid, with to ensure in the raceway groove that described first grid is adjacent with second grid charge carrier normal through.What show in Figure 12 is the very wide situation of source region and drain region transverse width.In addition, the transverse width of described side wall is more than or equal to the spacing between described first grid and second grid equally, and the transverse width of described side wall is wider, is more conducive to reducing the parasitic capacitance between source region and each grid, improves device performance.
Step S4, refers to Figure 13 to Figure 14, etches described strip structure two ends until exposed portion second gate dielectric layer upper surface; After etching, the second gate dielectric layer of remaining second grid material layer and below thereof forms the 3rd grid.
Wherein, Figure 13 is shown as the vertical view of the structure that step S4 obtains, and Figure 14 is shown as the generalized section of this structure, and as shown in figure 14, after etching, the second gate dielectric layer of remaining second grid material layer 9 and below thereof forms the 3rd grid 13.Longitudinal width d of the 3rd grid is also show in Figure 13
5and the 3rd transverse width d of grid
6, wherein, longitudinal width d of the 3rd grid
5be more than or equal to longitudinal width d of described first grid
3, longitudinal width d of the 3rd grid
5also longitudinal width of second grid is more than or equal to; The transverse width d of the 3rd grid
6be less than or equal to the spacing d of described first grid 6 and second grid 7
4.Figure 14 display be the transverse width d of the 3rd grid
6equal the spacing d of described first grid 6 and second grid 7
4situation.Longitudinal width for the 3rd grid is greater than the situation of described first grid and the longitudinal width of second grid, because the window's position of source and drain ion implantation is actual is add what side wall determined by longitudinal width of the 3rd grid, although so longitudinal width of the 3rd grid is greater than longitudinal width of described first grid and second grid, if but ensure that source-drain area ion diffuse is enough to have a common boundary the border to three grid by optimizing the means such as annealing, just can ensure each raceway groove normally.For the transverse width d of the 3rd grid
6be less than the spacing d of described first grid 6 and second grid 7
4situation, can reduce the 3rd parasitic capacitance of parasitic capacitance and the 3rd between grid and second grid between grid and first grid, device performance is better.
Step S5, refers to Figure 15 to Figure 18, the structure that step S4 obtains forms insulating barrier and carries out polishing until described insulating barrier upper surface flushes with described 3rd gate upper surface; Finally above described first grid, second grid, source region and drain region, form contact hole respectively.
First Figure 15 is referred to, be shown as step S4 obtain structure on depositing insulating layer 14 and carry out polishing until described insulating barrier 14 upper surface flush with described 3rd gate upper surface after cross-sectional view, Figure 16 is shown as the vertical view of structure shown in Figure 15.Figure 17 is shown as the generalized section of the structure after forming contact hole 15, so far, defines fin formula field effect transistor structure of the present invention.Figure 18 is shown as the vertical view of this structure.
The manufacture method of fin formula field effect transistor structure of the present invention defines three discrete grids: first grid 6, second grid 7 and the 3rd grid 13, thus in substrate 1, define three raceway grooves, lay respectively in the adjacent substrate of two laterally relative medial surfaces of described first grid 6 and second grid 7 and in substrate that described 3rd grid lower surface is adjacent.During work, different voltage can be added respectively on three grids and raceway groove is controlled, obtain larger electric current and response speed faster, effectively promote the performance of transistor arrangement; In addition, fin formula field effect transistor raceway groove of the present invention is arranged in substrate, without the need to etching away a large amount of substrates during making, because this reducing etch period, having saved cost, and reduces technology difficulty.
Embodiment 2
Refer to Figure 17 and Figure 18, the present invention also provides a kind of fin formula field effect transistor structure, comprising:
Substrate 1, recessedly in described substrate 1 is formed with discrete first grid 6 and second grid 7; Described first grid 6 and second grid 7 include first grid material layer 5 and surround the first grid dielectric layer 4 of described first grid material layer 5 sidewall and bottom; Described first grid 6 and second grid 7 upper surface and described substrate 1 upper surface flush;
Second gate dielectric layer 8, described second gate dielectric layer 8 is strip and covers described first grid 6 and second grid 7; Described second gate dielectric layer 8 zone line is formed with second grid material layer 9, and the second gate dielectric layer of described second grid material layer 9 and below thereof forms the 3rd grid 13;
A pair side wall 10, is formed on the longitudinal relative two side of described second gate dielectric layer 8 and the longitudinal relative two side of described second grid material layer 9, described side wall 10 upper surface and described 3rd grid 13 upper surface flush; Source region and drain region is formed respectively in the substrate of described side wall 10 both sides;
Insulating barrier 14, described insulating barrier 14 is formed at second gate dielectric layer 8 surface at described 3rd grid 13 two ends, surface, described source region and surface, described drain region; Described insulating barrier 14 upper surface and described 3rd grid 13 upper surface flush; Contact hole 15 is formed above described first grid 6, second grid 7, source electrode and drain region.
Concrete, longitudinal width of described 3rd grid 13 is more than or equal to longitudinal width of described first grid 6 and second grid 7, and the transverse width of described 3rd grid 13 is less than or equal to the spacing of described first grid 6 and second grid 7.
Concrete, described first grid 6, second grid 7 and the 3rd grid 13 are based on the grid structure of polysilicon or for high-K metal gate structure, can also be polysilicon and metal composite structure, in described first grid 6, second grid 7 and the 3rd grid 13, can alloy be comprised.Described first grid material layer 5 and second grid material layer 9 can be single layer structure, also can be composite lamainated structure.
Fin formula field effect transistor structure of the present invention comprises three discrete grids, be formed with three raceway grooves in the substrate, three grids can add identical or different voltage respectively, can opereating specification large, have more flexibility, larger electric current and response speed faster can be obtained, thus effectively promote the performance of transistor arrangement.
In sum, the manufacture method of fin formula field effect transistor structure of the present invention produces three independently grids in transistor arrangement, different voltage can be added respectively on three grids to control raceway groove, obtain larger electric current and response speed faster, effectively promote the performance of transistor arrangement; Fin formula field effect transistor raceway groove of the present invention is arranged in substrate, without the need to etching away a large amount of substrates during making, because this reducing etch period, having saved cost, and reduces technology difficulty.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. a manufacture method for fin formula field effect transistor structure, is characterized in that, at least comprises the following steps:
S1 a: substrate is provided, the first grid that recessed formation is discrete in described substrate and second grid; Described first grid and second grid include first grid material layer and surround the first grid dielectric layer of described first grid material layer sidewall and bottom; Described first grid and second grid upper surface flush with described substrate top surface;
S2: form the list structure that covers described first grid and second grid over the substrate; Described strip structure comprises second gate dielectric layer and second grid material layer from bottom to top successively;
S3: form a side wall respectively on two sides that described list structure is longitudinally relative; Then in the substrate of a pair side wall both sides, source region and drain region is formed respectively;
S4: etch described strip structure two ends until exposed portion second gate dielectric layer upper surface; After etching, the second gate dielectric layer of remaining second grid material layer and below thereof forms the 3rd grid;
S5: form insulating barrier and carry out polishing until described insulating barrier upper surface flushes with described 3rd gate upper surface in the structure that step S4 obtains; Contact hole is formed respectively above described first grid, second grid, source region and drain region.
2. the manufacture method of fin formula field effect transistor structure according to claim 1, is characterized in that: described first grid and second grid being projected as in the horizontal plane is square, and altitude range is 20nm ~ 60nm, and width range is 10nm ~ 30nm.
3. the manufacture method of fin formula field effect transistor structure according to claim 1, is characterized in that: longitudinal width of described 3rd grid is more than or equal to longitudinal width of described first grid and second grid.
4. the manufacture method of fin formula field effect transistor structure according to claim 1, is characterized in that: the transverse width of described 3rd grid is less than or equal to the spacing of described first grid and second grid.
5. the manufacture method of fin formula field effect transistor structure according to claim 1, is characterized in that: described source region and drain region are formed by doping, and the degree of depth of doping is less than or equal to the height of described first grid and second grid.
6. the manufacture method of fin formula field effect transistor structure according to claim 1, is characterized in that: also comprised the step of described substrate being carried out to plasma treatment form first grid and second grid in described step S1 before; Described plasma comprise in N, F or Ar one or more.
7. the manufacture method of fin formula field effect transistor structure according to claim 1, is characterized in that: described substrate is Si substrate or SOI substrate.
8. a fin formula field effect transistor structure, is characterized in that, comprising:
Substrate, recessedly in described substrate is formed with discrete first grid and second grid; Described first grid and second grid include first grid material layer and surround the first grid dielectric layer of described first grid material layer sidewall and bottom; Described first grid and second grid upper surface flush with described substrate top surface;
Second gate dielectric layer, described second gate dielectric layer is strip and covers described first grid and second grid; Described second gate dielectric layer zone line is formed with second grid material layer, and the second gate dielectric layer of described second grid material layer and below thereof forms the 3rd grid;
A pair side wall, be formed on the longitudinal relative two side of described second gate dielectric layer and the longitudinal relative two side of described second grid material layer, described side wall upper surface flushes with described 3rd gate upper surface; Source region and drain region is formed respectively in the substrate of described side wall both sides;
Insulating barrier, described insulating barrier is formed at the second gate dielectric layer surface at described 3rd grid two ends, surface, described source region and surface, described drain region; Described insulating barrier upper surface flushes with described 3rd gate upper surface; Contact hole is formed above described first grid, second grid, source electrode and drain region.
9. fin formula field effect transistor structure according to claim 1, is characterized in that: longitudinal width of described 3rd grid is more than or equal to longitudinal width of described first grid and second grid.
10. fin formula field effect transistor structure according to claim 1, is characterized in that: the transverse width of described 3rd grid is less than or equal to the spacing of described first grid and second grid.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030113970A1 (en) * | 2001-12-14 | 2003-06-19 | Fried David M. | Implanted asymmetric doped polysilicon gate FinFET |
| US6876042B1 (en) * | 2003-09-03 | 2005-04-05 | Advanced Micro Devices, Inc. | Additional gate control for a double-gate MOSFET |
| CN101068029A (en) * | 2007-06-05 | 2007-11-07 | 北京大学 | Double-fin type channel double-grid multifunction field effect transistor and producing method thereof |
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2013
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030113970A1 (en) * | 2001-12-14 | 2003-06-19 | Fried David M. | Implanted asymmetric doped polysilicon gate FinFET |
| US6876042B1 (en) * | 2003-09-03 | 2005-04-05 | Advanced Micro Devices, Inc. | Additional gate control for a double-gate MOSFET |
| CN101068029A (en) * | 2007-06-05 | 2007-11-07 | 北京大学 | Double-fin type channel double-grid multifunction field effect transistor and producing method thereof |
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