CN104393029A - Low-input capacitance power semiconductor field effect transistor and self-alignment manufacture method thereof - Google Patents
Low-input capacitance power semiconductor field effect transistor and self-alignment manufacture method thereof Download PDFInfo
- Publication number
- CN104393029A CN104393029A CN201410619738.6A CN201410619738A CN104393029A CN 104393029 A CN104393029 A CN 104393029A CN 201410619738 A CN201410619738 A CN 201410619738A CN 104393029 A CN104393029 A CN 104393029A
- Authority
- CN
- China
- Prior art keywords
- polysilicon
- gate
- field plate
- micron
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 230000005669 field effect Effects 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 121
- 229920005591 polysilicon Polymers 0.000 claims abstract description 121
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- 238000001465 metallisation Methods 0.000 claims abstract description 6
- 239000008186 active pharmaceutical agent Substances 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims description 20
- 238000001039 wet etching Methods 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 6
- 239000003990 capacitor Substances 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract 3
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention relates to a low-input capacitance power semiconductor field effect transistor and a self-alignment manufacture method thereof and belongs to the semiconductor device technical field. The objective of the invention is to solve the problem of a Miller capacitance effect in an existing MOSFET device structure. A polysilicon gate of the semiconductor field effect device is disconnected at edges of two sides of a JFET region, so that polysilicon gates at two sides and a polysilicon field plate on the JFET region at the middle can be formed; an interval is formed between the polysilicon gates at two sides and the polysilicon field plate respectively; and the polysilicon field plate is connected with source region metal of the device at the edge of an active region of a chip, so that a capacitor between the DS of the device can be formed. The method includes the following steps that: a gate oxide layer is grown on an epitaxial layer, and a polysilicon layer is deposited on the gate oxide layer, and photo etching is performed, and therefore, polysilicon gates and a polysilicon field plate can be formed; an insulating layer is deposited; photo etching is performed on the insulating layer so as to expose the polysilicon gates at two sides; and injection and diffusion of a P well region and an N+ source region are performed, and photo etching is performed on contact holes of the gates and sources, and front-surface and back-surface metallization treatment is performed.
Description
Technical field
The present invention relates to mos field effect transistor, especially DMOS and the IGBT constant power semiconductor device of the hyperstructure of power VDMOSFET FET, IGBT, plane (the parallel chip surface of raceway groove), be specifically related to low input capacitance power semiconductor field effect transistor and autoregistration manufacture method thereof, belong to technical field of semiconductor device.
Background technology
Mos field effect transistor (MOSFET), as switching device, is widely used in the fields such as power supply.As shown in Figure 1, mos field effect transistor general principle forms semiconductor surface at NPN, p type island region wherein covers the PN junction of both sides, form oxide layer metal (or silicon) grid structure above, utilize the p type island region below grid under gate bias, form inversion layer and make the N-type region UNICOM of both sides and the grid-control semiconductor device that forms.In order to realize high pressure, form device architecture as shown in Figure 2, device withstand voltage drift region changes vertical structure into; In order to process implementing is convenient and in order to reach withstand voltage raising or withstand voltage stablizing, metal (or silicon) grid will have certain length to cover on drift region usually, serve as field plate effect.Result is the withstand voltage of raising device, but because this field plate and drift region form capacitance structure, and be connected with device control gate, the charge and discharge process of this electric capacity acts directly on the control gate of device, there is Miller capacitance effect, the switching speed of device is reduced, changes the dynamic gain of device, increase switch power loss; Reduce circuit efficiency.
Summary of the invention
The present invention there will be Miller capacitance effect to solve MOSFET element structure in prior art, the switching speed of device is reduced, increase switch power loss, reduce the problem of circuit efficiency, provide a kind of low input capacitance power semiconductor field effect transistor and autoregistration manufacture method thereof.
Low input capacitance power semiconductor field effect transistor, it is characterized in that, the polysilicon gate of semiconductor field device disconnects at both sides of the edge place of JFET district, form the polysilicon field plate in both sides polysilicon gate and middle JFET district, all there is spacing between both sides polysilicon gate and polysilicon field plate, described polysilicon field plate is connected with the source region metal of this device at chip active area edge, the electric capacity between the DS forming this device.
The width of polysilicon gate is less than or equal to described gap length, and described spacing between 0.2 micron to 5 microns, and is greater than gate oxide thickness more than 4 times.
The autoregistration manufacture method of low input capacitance power semiconductor field effect transistor, is characterized in that, comprise the following steps:
Step one, carries out thermal oxidation and forms gate oxide, gate oxide deposits one deck polysilicon above epitaxial loayer, thickness 0.3 micron to 0.8 micron, chemical wet etching polysilicon layer, forms polysilicon gate and polysilicon field plate, realizes the autoregistration of polysilicon gate and polysilicon field plate; The width of polysilicon gate is less than or equal to channel length; The spacing of polysilicon gate and polysilicon field plate between 0.2 micron to 5 microns, and is greater than gate oxide thickness more than 4 times;
Step 2, depositing insulating layer, thickness 0.2 micron to 1 micron;
Step 3, chemical wet etching insulating barrier, the polysilicon gate of both sides is exposed in local;
Step 4, according to common MOSFET element technique, carries out P well region, diffusion is injected in N+ source region, then deposited oxide layer, and the contact hole of chemical wet etching grid and source electrode, finally carries out positive back side metallization technology.
The invention has the beneficial effects as follows: structure of the present invention reduces the input capacitance of device, overcomes metal oxide semiconductor field-effect device the Miller effect, and then shorten and improve switching speed switching time; Increase the output capacitance of device simultaneously, the high-tension electricity stress of device in high voltage switch circuit can be reduced.If the input and output capacitors numerical value of optimal design device, device zero voltage turn-off in circuit can be realized.
The processing step that realizes of the present invention is that polysilicon gate and polysilicon field plate chemical wet etching are formed, achieve the self-registered technology of the well region of fieldtron, source region, conducting channel, achieve the autoregistration of polysilicon gate and polysilicon field plate simultaneously, solve the device withstand voltage of lithography registration deviation generation and the consistency problem of channel resistance and JFET district resistance, reduce technology difficulty.
Accompanying drawing explanation
Fig. 1 is existing MOSFET element sectional view.
Fig. 2 is ordinary power VDMOSFET device sectional view.
Fig. 3 is VDMOSFET device architecture sectional view of the present invention.
In Fig. 4 (a) be device grids polycrystalline of the present invention and field plate polycrystalline chip active area edge respectively with gate metal and source metal connection layout; B () is the partial enlarged drawing of (a).
Fig. 5 is ordinary power VDMOSFET device equivalent circuit diagram.
Fig. 6 VDMOSFET device of the present invention equivalent circuit diagram.
Fig. 7 is device of the present invention, improves Cds ' structural section figure.
Fig. 8 is device of the present invention, improves Cds ' structural section figure.
Fig. 9-13 is steps of device execution mode one implementation method of the present invention.
Figure 14-20 is steps of device execution mode two implementation method of the present invention.
In figure: 1, source region metal, 2, insulating barrier, 3, grid, 4, N+ source region, 5, P type trap zone, 6, withstand voltage drift region, 7, drain metal, 8, drift region field plate, 9, insulating barrier under field plate.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further details.
Execution mode one:
For VDMOSFET device, as shown in Figure 2, the polysilicon gate of existing device is disconnected at JFET area edge place, be divided into the polysilicon gate of device and the polysilicon field plate of active area, form low input capacitance power semiconductor field effect transistor as shown in Figure 3, wherein the width of polysilicon gate is less than or equal to channel length, and the spacing of polysilicon gate and polysilicon field plate is between 0.2 micron to 5 microns, and described spacing is greater than gate oxide thickness more than 4 times.As shown in Figure 4, described polysilicon field plate is connected with the source region metal of device at chip active area edge, the electric capacity between the DS of formation device.
As shown in Figure 5, the equivalent electric circuit of conventional VDMOSFET device.Low input capacitance power semiconductor field effect transistor of the present invention, the device polysilicon grid of routine are disconnected at JFET area edge place, by the polysilicon gate of device controller part work with realize withstand voltage JFET district polysilicon field plate and separate, the electric capacity that polysilicon field plate produces is not connected with the polysilicon gate of device and is connected with the source electrode of device, and device equivalent electric circuit of the present invention as shown in Figure 6.Compared with conventional device, the Cgd electric capacity of this device becomes the Cds electric capacity of device, achieves and reduces the effect that input capacitance increases output capacitance.
Implementation method of the present invention:
Step one, as shown in Figure 9, carry out thermal oxidation above epitaxial loayer and form gate oxide, gate oxide deposits one deck polysilicon, thickness 0.3 micron to 0.8 micron, chemical wet etching polysilicon layer, form polysilicon gate and polysilicon field plate, as shown in Figure 10, realize the autoregistration of polysilicon gate and polysilicon field plate, the width of polysilicon gate is less than or equal to channel length; The spacing of polysilicon gate and polysilicon field plate between 0.2 micron to 5 microns, and is greater than gate oxide thickness more than 4 times.
Step 2, as shown in figure 11, depositing insulating layer, as SiO2 etc., thickness 0.2 micron to 1 micron.
Step 3, as shown in figure 12, chemical wet etching insulating barrier, polysilicon gate outer end, both sides is exposed in local.
Step 4, as shown in figure 13, according to common MOSFET element technique, carries out P well region, diffusion is injected in N+ source region, then deposited oxide layer, and the contact hole of chemical wet etching grid and source electrode, finally carries out positive back side metallization technology.
Execution mode two:
Fig. 7 is according to a VDMOSFET chip cross-section figure implemented of the present invention, the polysilicon gate of device is disconnected at JFET area edge place, be divided into the polysilicon field plate in the polysilicon gate of device and JFET district, realize the autoregistration of polysilicon gate and polysilicon field plate, form the structure as Fig. 7, wherein the width of polysilicon gate is less than or equal to channel length, and the spacing of polysilicon gate and polysilicon field plate between 0.2 micron to 5 microns, and is greater than gate oxide thickness more than 4 times.Be connected by polysilicon layer above the polysilicon gate of both sides, and be separated by by insulating barrier between this structure and polysilicon field plate.
Described polysilicon field plate is connected with the source region metal of device at chip active area edge.Electric capacity between the DS of formation device, its equivalent electric circuit as shown in Figure 6.
This process implementation method comprises the following steps:
Step one, as shown in figure 14, gate oxide deposits one deck polysilicon, thickness 0.3 micron to 0.8 micron, chemical wet etching polysilicon layer, forms polysilicon gate and polysilicon field plate, realizes the autoregistration of polysilicon gate and polysilicon field plate, as shown in figure 15, the width of polysilicon gate is less than or equal to channel length; The spacing of polysilicon gate and polysilicon field plate between 0.2 micron to 5 microns, and is greater than gate oxide thickness more than 4 times.
Step 2, as shown in figure 16, depositing insulating layer, as SiO2 etc., thickness 0.2 micron to 1 micron.
Step 3, as shown in figure 17, chemical wet etching insulating barrier, the outer end of both sides polysilicon gate is exposed in local.
Step 4, as shown in figure 18, deposition second layer polysilicon, thickness 0.3 micron to 0.8 micron.
Step 5, as shown in figure 19, chemical wet etching second layer polysilicon, exposes the side of ground floor polysilicon gate, forms the structure that both sides polysilicon gate is connected by the second layer polysilicon of deposition.
Step 6, as shown in figure 20, according to common MOSFET element technique, carries out P well region, diffusion is injected in N+ source region, then deposited oxide layer, and the contact hole of chemical wet etching grid and source electrode, finally carries out positive back side metallization technology.
Execution mode three:
As shown in Figure 8, it is the improvement that execution mode two carries out, in order to better reduce device shutoff voltage stress, increase the thickness of gate oxide, reduce Cgs electric capacity, the thickness of the insulating barrier below thinning polysilicon field plate, increase Cds ' electric capacity, realize increasing turn-off speed, increase Cds electric capacity and the voltage stress produced in turn off process is absorbed.Realize zero voltage turn-off.
This process implementation method comprises the following steps:
Step one, carries out thermal oxidation and forms gate oxide, oxidated layer thickness above epitaxial loayer
Step 2, the oxide layer below chemical wet etching partial polysilicon field plate, residue oxide thickness
etching width is slightly wider than the width of polysilicon field plate.
Step 3, deposition one deck polysilicon, thickness 0.3 micron to 0.8 micron, chemical wet etching, form polysilicon gate and polysilicon field plate, the width of polysilicon gate is less than or equal to channel length; The spacing of polysilicon gate and polysilicon field plate between 0.2 micron to 5 microns, and is greater than gate oxide thickness more than 4 times.
Step 4, depositing insulating layer, as SiO2 etc., thickness 0.2 micron to 1 micron.
Step 5, chemical wet etching insulating barrier, the outer end of both sides polysilicon gate is exposed in local.
Step 6, deposition second layer polysilicon, thickness 0.3 micron to 0.8 micron.
Step 7, chemical wet etching second layer polysilicon, exposes the side that ground floor polysilicon forms polysilicon gate, forms the structure that both sides polysilicon gate is connected by the second layer polysilicon of deposition.
Step 8, according to common MOSFET element technique, carries out P well region, diffusion is injected in N+ source region, then deposited oxide layer, and the contact hole of chemical wet etching grid and source electrode, finally carries out positive back side metallization technology.
Claims (5)
1. low input capacitance power semiconductor field effect transistor, it is characterized in that, the polysilicon gate of semiconductor field device disconnects at both sides of the edge place of JFET district, form the polysilicon field plate in both sides polysilicon gate and middle JFET district, all there is spacing between both sides polysilicon gate and polysilicon field plate, described polysilicon field plate is connected with the source region metal of this device at chip active area edge, the electric capacity between the DS forming this device.
2. low input capacitance power semiconductor field effect transistor according to claim 1, is characterized in that, the width of polysilicon gate is less than or equal to described channel length, and described spacing between 0.2 micron to 5 microns, and is greater than gate oxide thickness more than 4 times.
3. low input capacitance power semiconductor field effect transistor according to claim 1, is characterized in that, is connected, and is separated by by insulating barrier between this structure and polysilicon field plate above two polysilicon gates by polysilicon layer.
4. the autoregistration manufacture method of low input capacitance power semiconductor field effect transistor, is characterized in that, comprise the following steps:
Step one, carries out thermal oxidation and forms gate oxide, gate oxide deposits one deck polysilicon above epitaxial loayer, thickness 0.3 micron to 0.8 micron, chemical wet etching polysilicon layer, forms polysilicon gate and polysilicon field plate, realizes the autoregistration of polysilicon gate and polysilicon field plate; The width of polysilicon gate is less than or equal to channel length; The spacing of polysilicon gate and polysilicon field plate between 0.2 micron to 5 microns, and is greater than gate oxide thickness more than 4 times;
Step 2, depositing insulating layer, thickness 0.2 micron to 1 micron;
Step 3, chemical wet etching insulating barrier, the outer end of both sides polysilicon gate is exposed in local;
Step 4, according to common MOSFET element technique, carries out P well region, diffusion is injected in N+ source region, then deposited oxide layer, and the contact hole of chemical wet etching grid and source electrode, finally carries out positive back side metallization technology.
5. the autoregistration manufacture method of low input capacitance power semiconductor field effect transistor according to claim 4, is characterized in that, between step 3 and step 4, add following steps, deposition second layer polysilicon, thickness 0.3 micron to 0.8 micron; Chemical wet etching second layer polysilicon, exposes the side of ground floor polysilicon gate, forms the structure that both sides polysilicon gate is connected by the second layer polysilicon of deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410619738.6A CN104393029A (en) | 2014-11-03 | 2014-11-03 | Low-input capacitance power semiconductor field effect transistor and self-alignment manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410619738.6A CN104393029A (en) | 2014-11-03 | 2014-11-03 | Low-input capacitance power semiconductor field effect transistor and self-alignment manufacture method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104393029A true CN104393029A (en) | 2015-03-04 |
Family
ID=52610902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410619738.6A Pending CN104393029A (en) | 2014-11-03 | 2014-11-03 | Low-input capacitance power semiconductor field effect transistor and self-alignment manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104393029A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105161540A (en) * | 2015-09-15 | 2015-12-16 | 电子科技大学 | VDMOS device structure with low miller capacitance and manufacturing method of VDMOS device structure |
| CN108565289A (en) * | 2018-06-26 | 2018-09-21 | 南京方旭智芯微电子科技有限公司 | The manufacturing method of superjunction field-effect tube and superjunction field-effect tube |
| CN109659236A (en) * | 2018-12-17 | 2019-04-19 | 吉林华微电子股份有限公司 | Reduce the process and its VDMOS semiconductor devices of VDMOS recovery time |
| CN109728076A (en) * | 2018-12-28 | 2019-05-07 | 电子科技大学 | A kind of anti-radiation power unit structure of transverse direction |
| CN112635559A (en) * | 2019-09-24 | 2021-04-09 | 南通尚阳通集成电路有限公司 | Plane gate super junction MOSFET |
| CN112802906A (en) * | 2021-04-15 | 2021-05-14 | 成都蓉矽半导体有限公司 | Separated gate planar MOSFET device with floating gate |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4455565A (en) * | 1980-02-22 | 1984-06-19 | Rca Corporation | Vertical MOSFET with an aligned gate electrode and aligned drain shield electrode |
| DE19905421A1 (en) * | 1999-02-10 | 2000-08-24 | Semikron Elektronik Gmbh | Power semiconductor component with reduced Miller capacity such as IGBT or MOSFET in current rectifier, half-bridges, and switches |
| US20020017682A1 (en) * | 2000-07-12 | 2002-02-14 | Shuming Xu | Semiconductor device |
| US20060043479A1 (en) * | 2004-09-02 | 2006-03-02 | Patrice Parris | Metal oxide semiconductor device including a shielding structure for low gate-drain capacitance |
| CN102569385A (en) * | 2010-12-17 | 2012-07-11 | 上海华虹Nec电子有限公司 | VDMOS (vertical double-diffused metal oxide semiconductor) structure provided with shielding grid and preparation method thereof |
| CN102569386A (en) * | 2010-12-17 | 2012-07-11 | 上海华虹Nec电子有限公司 | VDMOS (vertical double-diffused metal oxide semiconductor) device with shield grid and preparation method of VDMOS device |
| CN204375754U (en) * | 2014-11-03 | 2015-06-03 | 吉林华微电子股份有限公司 | Low input capacitance power semiconductor field effect transistor |
-
2014
- 2014-11-03 CN CN201410619738.6A patent/CN104393029A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4455565A (en) * | 1980-02-22 | 1984-06-19 | Rca Corporation | Vertical MOSFET with an aligned gate electrode and aligned drain shield electrode |
| DE19905421A1 (en) * | 1999-02-10 | 2000-08-24 | Semikron Elektronik Gmbh | Power semiconductor component with reduced Miller capacity such as IGBT or MOSFET in current rectifier, half-bridges, and switches |
| US20020017682A1 (en) * | 2000-07-12 | 2002-02-14 | Shuming Xu | Semiconductor device |
| US20060043479A1 (en) * | 2004-09-02 | 2006-03-02 | Patrice Parris | Metal oxide semiconductor device including a shielding structure for low gate-drain capacitance |
| CN102569385A (en) * | 2010-12-17 | 2012-07-11 | 上海华虹Nec电子有限公司 | VDMOS (vertical double-diffused metal oxide semiconductor) structure provided with shielding grid and preparation method thereof |
| CN102569386A (en) * | 2010-12-17 | 2012-07-11 | 上海华虹Nec电子有限公司 | VDMOS (vertical double-diffused metal oxide semiconductor) device with shield grid and preparation method of VDMOS device |
| CN204375754U (en) * | 2014-11-03 | 2015-06-03 | 吉林华微电子股份有限公司 | Low input capacitance power semiconductor field effect transistor |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105161540A (en) * | 2015-09-15 | 2015-12-16 | 电子科技大学 | VDMOS device structure with low miller capacitance and manufacturing method of VDMOS device structure |
| CN108565289A (en) * | 2018-06-26 | 2018-09-21 | 南京方旭智芯微电子科技有限公司 | The manufacturing method of superjunction field-effect tube and superjunction field-effect tube |
| CN109659236A (en) * | 2018-12-17 | 2019-04-19 | 吉林华微电子股份有限公司 | Reduce the process and its VDMOS semiconductor devices of VDMOS recovery time |
| CN109728076A (en) * | 2018-12-28 | 2019-05-07 | 电子科技大学 | A kind of anti-radiation power unit structure of transverse direction |
| CN112635559A (en) * | 2019-09-24 | 2021-04-09 | 南通尚阳通集成电路有限公司 | Plane gate super junction MOSFET |
| CN112802906A (en) * | 2021-04-15 | 2021-05-14 | 成都蓉矽半导体有限公司 | Separated gate planar MOSFET device with floating gate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104393029A (en) | Low-input capacitance power semiconductor field effect transistor and self-alignment manufacture method thereof | |
| US9240469B2 (en) | Transverse ultra-thin insulated gate bipolar transistor having high current density | |
| US9825149B2 (en) | Split gate power semiconductor field effect transistor | |
| CN102364688B (en) | Vertical double-diffusion metal oxide semiconductor field effect transistor (MOSFET) | |
| CN204375754U (en) | Low input capacitance power semiconductor field effect transistor | |
| US8557678B2 (en) | Method for manufacturing semiconductor substrate of large-power device | |
| CN105070759A (en) | Nldmos device and manufacturing method thereof | |
| US11888022B2 (en) | SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof | |
| CN114122123B (en) | Silicon carbide split gate MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with high-speed freewheeling diode and preparation method | |
| CN107464837B (en) | Super junction power device | |
| TWI229941B (en) | High voltage metal-oxide semiconductor device | |
| CN110010692B (en) | Power semiconductor device and manufacturing method thereof | |
| JP2011522402A (en) | Power field effect transistor | |
| CN108807505A (en) | A kind of silicon carbide MOSFET device and its manufacturing method | |
| CN101692426A (en) | Method for preparing vertical double-diffusion MOS transistor | |
| WO2022121306A1 (en) | High-voltage ldmos device having asymmetric structure and preparation method therefor | |
| CN102386227B (en) | Both-way surface field subdued drain electrode isolation double diffused drain metal-oxide -semiconductor field effect transistor (DDDMOS) transistor and method | |
| CN203707141U (en) | Integrated finger-gate vertical-channel SOI LDMOS unit | |
| Wang et al. | Experimental of folded accumulation lateral double-diffused transistor with low specific on resistance | |
| WO2022067946A1 (en) | Semiconductor power device | |
| CN115425079A (en) | Groove type double-layer gate power device and manufacturing method thereof | |
| CN108258040A (en) | Igbt with wide band gap semiconducter substrate material and preparation method thereof | |
| CN208336233U (en) | The semiconductor devices terminal structure of voltage endurance capability can be improved | |
| CN107863343B (en) | Planar MOS device and manufacturing method thereof | |
| CN105977301B (en) | A kind of internal grid-type MOS |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150304 |