CN104409533B - InSb infrared focal plane detector array and preparation method thereof - Google Patents
InSb infrared focal plane detector array and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035209—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions comprising a quantum structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a kind of InSb infrared focal plane detector array and preparation method thereof.This detector array includes N-shaped InSb substrate (1) and passivation layer (7), and N-shaped InSb substrate (1) is etched with t × t table top (2), and t is integer and t >=1；Each table top (2) top is deposited with anode (5), and N-shaped InSb substrate (1) edge upper part is deposited with " returning " font negative electrode (6)；Described N-shaped InSb substrate (1) top and each table top (2) side are deposited with protective layer (4)；Being provided with m identical p-type isosceles triangle doped region (3) in N-shaped InSb substrate (1) immediately below each table top (2), m is integer and m >=1, and these p-type isosceles triangle doped regions constitute pn-junction with N-shaped InSb substrate.The present invention has the advantage that technique is simple, quantum efficiency is high, cross-talk is low, can be used for infrared detection and Infrared Therapy field.
Description
Technical field
The invention belongs to semiconductor photovoltaic type detector technology field, particularly to InSb infrared focal plane detector array,
Can be used for infrared detection, infrared guidance and Infrared Therapy.
Technical background
Infrared focal plane detector array is the core parts of infrared system, and its function is that infra-red radiation changes into other I
The signal that is capable of identify that.In earth observation from space, photoelectronic warfare, robot vision, medical and industrial thermal imaging, search
Rope has important with military and civilian fields such as tracking and guided missile precise guidances and is widely applied, and high-performance is the most infrared
Focus planardetector array has been widely used in various great national security projects and important new weapon system.Due to
It has irreplaceable status and effect, and infrared focal plane array device is all prepared skill by the big state of key industry in the world
Art is classified as the high technology item given priority to.
The mode of operation of Infrared Detectors mainly has guide type and photovoltaic type two kinds, and photovoltaic type Infrared Detectors is owing to existing
Built in field, dark current is less, so being widely used in military affairs, wherein photovoltaic type InSb Infrared Detectors is to grind at present
Studying carefully most a kind of photovoltaic detectors, this detector is most based on pn-junction, may be constructed photovoltaic type focal plane
Array.In recent years, Infrared Focal plane Array Technologies presented that specification is increasing, pixel centre-to-centre spacing is more and more less,
The development trend that multispectral sensing application is more and more, new material continues to bring out etc..In senior infrared application system energetically
Under driving, infrared detection technique from unit and the linear array of the first generation, progressed into large area array, miniaturization and
The developmental stage of the third generation infrared focal plane detector of the features such as multicolor.Along with space flight and the at full speed of military field are sent out
Exhibition, more and more higher to the performance requirement of medium wave infrared detector, improve detector performance by improving quality of materials
Far from meeting current application demand, therefore using device architecture optimization design to improve detector performance has become domestic
Outer study hotspot.
Quantum efficiency and cross-talk are to weigh the important parameter index of InSb photovoltaic type infrared focal plane detector array performance, it
Can affect the detectivity of detector array, decide the Effect on Detecting of detector to a great extent.In order to improve quantum
Efficiency, the cross-talk that reduces, 1981, Zhao Wenqin proposed to use H+implantation to be formed in InSb detector array first
Resistive formation carries out the method isolated, and the cross-talk of the InSb detector array of preparation is reduced to 1.7～3.76%, but quantum is imitated
The improvement of rate is the most inconspicuous, and only 45%, see the blanketing effect of InSb proton bombardment damage, Zhao Wenqin, quasiconductor
Report, Vol.2, No.1, pp.14-21,1981.2006, leaf Zhenhua et al. reported a kind of red with antireflective convergence microlens
Outer focus planardetector, is effectively improved the photoelectric current of detector, cross-talk can be reduced to 1%, see patent CN
100433328C.But, this invention is the performance improving detector by being introduced from outside into novel antireflective convergence microlens,
On the one hand, preparing of antireflective convergence microlens is complex, on the other hand, in semiconductor device structure design side in this patent
The innovation of face not essence.2011, Hu Weida et al. reported a kind of micro lens array InSb infrared focus plane battle array
The structure of row, this structure is by using silicon microlens structure to add light absorption, thus improves device performance, passes through
Silicon microlens structure optimization can make cross-talk be reduced to 4.2%, sees patent CN 102201487 B.But, this invention
Needing hetero-epitaxy InSb material on a silicon substrate, this will cause in N-shaped InSb region especially silicon substrate and N-shaped
Produce a large amount of dislocations or defect near InSb region interface, affect the generation of photo-generated carrier, and a large amount of photoproduction load can be captured
Stream, this invention also needs to prepare silicon lenticule in addition, and therefore to realize difficulty bigger in this invention.
Summary of the invention
It is an object of the invention to overcome the deficiency of above-mentioned prior art, manufacturing process is simple, cross-talk is little, amount to propose one
InSb infrared focal plane detector array that sub-efficiency is high and preparation method thereof, to improve infrared focal plane detector array
Performance.
To achieve these goals, the invention provides a kind of InSb infrared focal plane detector array, this structure is from upper
Under include: N-shaped InSb substrate and passivation layer, N-shaped InSb substrate is etched with t × t table top, t is integer and t >=1,
Each table top top is deposited with anode, and N-shaped InSb edges of substrate top is deposited with " returning " font negative electrode；Described N-shaped InSb
Substrate top and mesa sides are deposited with protective layer, it is characterised in that: set in the N-shaped InSb substrate immediately below each table top
Having the p-type isosceles triangle doped region that m is identical, m is integer and m >=1, these p-type isosceles triangle doped regions with
N-shaped InSb substrate constitutes pn-junction structure.
As preferably, the described thickness k before N-shaped InSb substrate etching is 3.5～20 μm, and the thickness s after etching is
3～10 μm, doping content is 1 × 1011cm-3～1 × 1016cm-3。
As preferably, the upper and lower surface of described each table top is square, and foursquare length of side L is 10～60 μm,
The height H of each table top is the most identical, and H deducts s equal to k, and span is 0.5～10 μm.
As preferably, described distance d between adjacent two table tops1Edge table top and N-shaped InSb edges of substrate
Between distance d2Equal, and span is 0.4～60 μm.
As preferably, base a length of r, the r=L/m of m described p-type isosceles triangle doped region, high h less than or
Equal to the thickness s after N-shaped InSb substrate etching, and h is equal to
M the p-type isosceles triangle doped region as preferably, immediately below the lower surface of described each table top and this table top
Bottom surface connect.
For achieving the above object, the method for the making InSb infrared focal plane detector array that the present invention provides, including as follows
Process:
The first step, makes mask on N-shaped InSb substrate for the first time, utilizes this mask to etch on N-shaped InSb substrate
Make t × t table top；
Second step, is 3～10 μm at N-shaped InSb substrate top, each table top top and each mesa sides deposition thickness
Dielectric layer；
3rd step, on dielectric layer, second time makes mask, utilizes this mask to etch in the dielectric layer on each table top top
Making m identical isosceles v-depression, the degree of depth of these isosceles v-depressions is less than or equal to the thickness of dielectric layer；
4th step, carries out n-type impurity ion implanting to the N-shaped InSb material of each isosceles v-depression bottom, it is achieved
The p-type of each table top is adulterated, and forms m identical p-type isosceles triangle doped region in each table top bottom, and
Base a length of r, the r=L/m of p-type isosceles triangle doped region, high h are less than or equal to after N-shaped InSb substrate etching
Thickness s, h are equal to
5th step, on dielectric layer, third time makes mask, utilizes this mask etching to remove N-shaped InSb substrate top, every
Individual table top top and the dielectric layer of each mesa sides；
6th step, deposits protective layer at N-shaped InSb substrate top, each table top top and each mesa sides, i.e. with absolutely
Edge dielectric material is covered each by N-shaped InSb substrate top, each table top top and the region of each mesa sides；
7th step, makes mask the 4th time on the protection layer, utilizes this mask etching to remove N-shaped InSb edges of substrate top
Protective layer with each table top top；
8th step, makes mask the 5th time on each table top and on N-shaped InSb edges of substrate, utilizes this mask each
Table top top deposit metal makes anode, makes " returning " font at N-shaped InSb edges of substrate top deposit metal cloudy simultaneously
Pole；
9th step, deposits passivation layer, i.e. covers n with saturating infra-red radiation insulating dielectric materials in the bottom of N-shaped InSb substrate
The region of type InSb substrate bottom, thus complete the making of whole detector array.
Array of the present invention compares with traditional InSb infrared focal plane detector array and has the advantage that
1, m identical p-type isoceles triangle it has been respectively formed in due to the fact that the N-shaped InSb substrate under each table top
Shape doped region, reduces pn-junction interface and photo-generated carrier and produces the distance between district, and increases the junction area of pn-junction,
Thus enhance the ability of pn-junction interface extraction photo-generated carrier, effectively inhibit photo-generated carrier to other probe unit
Motion, therefore substantially reduce the cross-talk of InSb infrared focal plane detector array, significantly improve quantum efficiency.
2, the present invention improves InSb infrared focus plane by introducing triangle doped region in N-shaped InSb substrate under table top
The performance of detector array, it is to avoid optical microlens system in tradition InSb infrared focal plane detector array fabrication process
The process complications problem that standby, hetero-epitaxy etc. is brought, reduces the manufacture difficulty of detector array.
Simulation result shows, the performance of InSb infrared focal plane detector array of the present invention is substantially better than traditional infrared focal plane
The performance of detector array.
Technology contents and the effect of the present invention is further illustrated below in conjunction with drawings and Examples.
Accompanying drawing explanation
Fig. 1 is the plan structure schematic diagram of InSb infrared focal plane detector array of the present invention；
Fig. 2 is the cross-sectional view of AB horizontal to Fig. 1；
Fig. 3 is the cross-sectional view to Fig. 1 longitudinal direction CD；
Fig. 4 is the technique Making programme figure of InSb infrared focal plane detector array of the present invention；
Fig. 5 is the hole concentration simulation comparison figure of the present invention and traditional InSb infrared focal plane detector array；
Fig. 6 is that the present invention emulates along the longitudinal electric field in incident radiation direction with traditional InSb infrared focal plane detector array
Comparison diagram；
Fig. 7 is that the present invention emulates along the transverse electric field in incident radiation direction with traditional InSb infrared focal plane detector array
Comparison diagram.
Detailed description of the invention
With reference to Fig. 1, Fig. 2 and Fig. 3, InSb infrared focal plane detector array of the present invention is based on InSb semi-conducting material
Pn-junction structure, this structure includes from top to bottom: N-shaped InSb substrate 1 and passivation layer 7.
Being etched with t × t table top 2 on described N-shaped InSb substrate 1, t is integer and t >=1, wherein N-shaped InSb substrate 1
Thickness k before etching is 3.5～20 μm, and the thickness s after etching is 3～10 μm, and doping content is
1×1011cm-3～1 × 1016cm-3；The upper and lower surface of each table top 2 is square, and square length of side L is 10～60 μm,
The height H of each table top is the most identical, and the span of H is 0.5～10 μm；Distance between adjacent two table tops 2 is
d1, the distance between edge table top and N-shaped InSb substrate 1 edge is d2, d1Equal to d2, and span is
0.4～60 μm.Each table top 2 top is deposited with anode 5；N-shaped InSb substrate 1 edge upper part is deposited with " returning " font
Negative electrode 6, this " returning " zigzag pattern each inner edge length is equal and each outside length is equal, wherein a length of t × L+ in outside (t+1) × d1,
Distance between the outer length of side and the interior length of side is d2/2.M it is provided with in N-shaped InSb substrate 1 immediately below each table top 2
Identical p-type isosceles triangle doped region 3, m is integer and m >=1, these p-type isosceles triangle doped regions 3 all with
N-shaped InSb substrate 1 constitutes pn-junction structure；The lower surface of each table top 2 all with this table top immediately below m p-type etc.
The bottom surface of lumbar triangle shape doped region 3 connects, base a length of r, the r=L/m of p-type isosceles triangle doped region 3, high h
Less than or equal to the thickness s after N-shaped InSb substrate 1 etching, and h is equal toN-shaped InSb substrate 1 top and
Each table top 2 side is deposited with protective layer 4.
In above-mentioned InSb infrared focal plane detector array: protective layer 4 uses SiO2、ZnS、SiN、Al2O3、Sc2O3、
HfO2、TiO2Or other insulating dielectric materials, its thickness is 0.1～1 μm；Anode 5 is identical with the thickness of negative electrode 6, and
All using identical Cr/Au metallic combination, metal thickness is 0.03～0.05 μm/0.5～1 μm, and lower metal thickness is little
In upper strata metal thickness；Passivation layer 7 uses ZnS, SiO2、SiN、Al2O3、HfO2、TiO2Or other saturating infrared spoke
Penetrating insulating dielectric materials, its thickness is 0.05～1 μm.
With reference to Fig. 4, the present invention makes InSb infrared focal plane detector array and provides following three kinds of embodiments:
Embodiment one: making protective layer is SiN, passivation layer is SiN, and immediately below each table top, p-type isosceles triangle is mixed
Number m=10 in miscellaneous district, array size is the InSb infrared focal plane detector array of 20 × 20.
Step 1, etches 20 × 20 table tops 2 of making, such as Fig. 4 a on N-shaped InSb substrate 1.
1a) thickness k be 20 μm, doping content be 1 × 1016cm-3N-shaped InSb substrate 1 on make for the first time and cover
Film, the array that this mask pattern is made up of the square that 20 × 20 length of sides L are 60 μm, adjacent two squares it
Between distance d1, and edge square and N-shaped InSb substrate 1 edge between distance d2It is 60 μm；
This mask 1b) is utilized to use reactive ion etching technology to etch 20 × 20 table tops 2 on N-shaped InSb substrate 1,
The height H of the most each table top 2 is 10 μm, and the thickness s after N-shaped InSb substrate 1 etching is 10 μm.Etching platform
The process conditions that face uses are: Ar/CH4/H2Flow-rate ratio is 1:2:6.6, and pressure is 0.35Pa, and power is 500W.
Step 2, on N-shaped InSb substrate 1 top, 20 × 20 table top 2 tops and the deposit of 20 × 20 table top 2 sides
Dielectric layer 8, such as Fig. 4 b.
Using plasma strengthen chemical vapor deposition techniques on N-shaped InSb substrate 1 top, 20 × 20 table top 2 tops
With the SiO that 20 × 20 table top 2 side deposition thicknesses are 10 μm2Dielectric layer 8.
The process conditions that dielectric layer deposited uses are: N2O flow is 900sccm, SiH4Flow is 225sccm, temperature
Being 275 DEG C, RF power is 27.5W, and pressure is 1250mTorr.
Step 3, in dielectric layer 8, etching makes isosceles v-depression 9, such as Fig. 4 c.
On dielectric layer 8, second time makes mask, uses reactive ion etching technology Jie on 20 × 20 table top 2 tops
In matter layer 8, all etching makes 10 identical isosceles v-depressions 9, and the degree of depth of isosceles v-depression 9 is 10 μm, the end
Edge lengths is 6 μm.
The process conditions that etched recesses uses are: SF6Flow is 7.5sccm, O2Flow is 2.5sccm, and pressure is
12.5mTorr, bias voltage is 125V.
Step 4, carries out n-type impurity ion implanting to the N-shaped InSb material of isosceles v-depression 9 bottom, it is achieved table top
The p-type doping of 2, and form p-type isosceles triangle doped region 3, such as Fig. 4 d.
The N-shaped InSb material of each isosceles v-depression 9 bottom is carried out n-type impurity ion implanting, it is achieved to 20 × 20
The p-type doping of individual table top 2, is formed and in dielectric layer 8 in the N-shaped InSb substrate 1 of each table top 2 bottom simultaneously
The p-type isosceles triangle doped region 3 that 10 isosceles v-depression 9 shapes are similar, p-type isosceles triangle doped region 3
Base r is 6 μm, and high h is 10 μm, and wherein impurity is boron ion, and doping content is 1 × 1018cm-3。
The process conditions that ion implanting uses are: implantation dosage is 7 × 1013cm-2, Implantation Energy is 800keV.
Step 5, removes dielectric layer 8, such as Fig. 4 e.
On dielectric layer 8, third time makes mask, uses reactive ion etching technology etching to remove N-shaped InSb substrate 1
Top, 20 × 20 table top 2 tops and the dielectric layer 8 of 20 × 20 table top 2 sides.
The process conditions that etch media layer uses: CF4Flow is 50sccm, O2Flow is 7.5sccm, and pressure is
17.5mTorr, power is 275W.
Step 6, on N-shaped InSb substrate 1 top, 20 × 20 table top 2 tops and the deposit of 20 × 20 table top 2 sides
Protective layer 4, such as Fig. 4 f.
Using plasma strengthen chemical vapor deposition techniques on N-shaped InSb substrate 1 top, 20 × 20 table top 2 tops
With the SiN protective layer 4 that 20 × 20 table top 2 side deposition thicknesses are 1 μm.
The process conditions that deposit protective layer uses are: gas is NH3、N2And SiH4, gas flow be respectively 2.2sccm,
925sccm and 225sccm, temperature, RF power and pressure are respectively 275 DEG C, 22.5W and 925mTorr.
Step 7, etching removal N-shaped InSb substrate 1 edge upper part and the protective layer 4 on 20 × 20 table top 2 tops, as
Fig. 4 g.
7a) making mask the 4th time on protective layer 4, this mask is to be made up of anode mask pattern and negative electrode mask pattern,
The array that its Anodic mask pattern is made up of by the square of 60 μm 20 × 20 length of sides L, adjacent two pros
Spacing d of shape1, edge square and N-shaped InSb substrate 1 edge between distance d2It is 60 μm；Negative electrode mask
Figure is " returning " zigzag pattern, and this " returning " zigzag pattern each inner edge length is equal and each outside length is equal, the outer length of side
Being 2460 μm, the outer length of side is 30 μm with the spacing of the interior length of side；
Above-mentioned mask 7b) is utilized to use reactive ion etching technology etching to remove N-shaped InSb substrate 1 edge upper part and 20 × 20
The protective layer 4 on individual table top 2 top.The process conditions that etch-protecting layer uses are: CF4Flow is 25sccm, O2Flow
For 3sccm, pressure is 25mTorr, and bias voltage is 150V.
Step 8, on table top 2 top, deposit metal makes anode 5, deposits in N-shaped InSb substrate 1 edge upper part simultaneously
Metal makes " returning " font negative electrode 6, such as Fig. 4 h.
8a) make mask, this mask pattern the 5th time on 20 × 20 table tops 2 and on N-shaped InSb substrate 1 edge
Identical with the mask pattern that the in step 7 the 4th time makes；
8b) utilize above-mentioned mask, use electron beam evaporation technique on each table top 2 top and N-shaped InSb substrate 1 limit
Edge top deposits Cr, Au metal successively, makes anode 5 and " returning " font negative electrode 6, and metal thickness is 0.05 μm/1 μm,
Again at N2Atmosphere carries out short annealing.
The process conditions that deposit metal uses are: vacuum is less than 1.8 × 10-3Pa, power bracket is 200～1000W, steams
Send out speed to be less thanThe process conditions that short annealing uses are: temperature is 700 DEG C, and the time is 30s.
Step 9, deposits passivation layer 7, such as Fig. 4 i in the bottom of N-shaped InSb substrate 1.
It is 1 μm at the bottom deposition thickness of N-shaped InSb substrate 1 that using plasma strengthens chemical vapor deposition techniques
SiN passivation layer 7, thus complete the making of whole detector array.
The process conditions of deposit passivation layer are: gas is NH3、N2And SiH4, gas flow be respectively 2.2sccm,
925sccm and 225sccm, temperature, RF power and pressure are respectively 275 DEG C, 22.5W and 925mTorr.
Embodiment two: making protective layer is SiO2, passivation layer is SiO2, immediately below each table top, p-type isosceles triangle is mixed
Number m=4 in miscellaneous district, array size is the InSb infrared focal plane detector array of 256 × 256.
Step one, etches 256 × 256 table tops 2 of making, such as Fig. 4 a on N-shaped InSb substrate 1.
Thickness k be 11 μm, doping content be 1 × 1014cm-3N-shaped InSb substrate 1 on make for the first time mask,
This mask is utilized to use inductive couple plasma reactive ion etching technology, at Ar/CH4/H2Flow-rate ratio is 1:3:10, and pressure is
10Pa, power is under the process conditions of 550W, etches 256 × 256 table surface heights of making on N-shaped InSb substrate 1
H be 5 μm, length of side L be the square-shaped mesa 2 of 40 μm, spacing d of the most adjacent two table tops1, edge table top
And distance d between N-shaped InSb edges of substrate2It is 30 μm；Thickness s after N-shaped InSb substrate 1 etching is 6 μm.
Step 2, on N-shaped InSb substrate 1 top, 256 × 256 table top 2 tops and 256 × 256 table top 2 sides
Dielectric layer deposited 8, such as Fig. 4 b.
Using plasma strengthens chemical vapor deposition techniques, is NH at gas3、N2And SiH4, gas flow is respectively
2.5sccm, 950sccm and 250sccm, temperature, RF power and pressure are respectively 300 DEG C, 25W and 950mTorr
Process conditions under, on N-shaped InSb substrate 1 top, 256 × 256 table top 2 tops and 256 × 256 table top 2 sides
Face deposition thickness is the SiN dielectric layer 8 of 7 μm.
Step 3, in dielectric layer 8, etching makes isosceles v-depression 9, such as Fig. 4 c.
On dielectric layer 8, second time makes mask, uses reactive ion etching technology at CF4Flow is 42.5sccm,
O2Flow is 3sccm, and pressure is 10mTorr, and power is under the process conditions of 220W, at 256 × 256 table tops 2
In the dielectric layer 8 on top, etching makes 4 identical isosceles v-depressions 9, the bottom side length of each isosceles v-depression 9
Being 10 μm, depth of groove is 7 μm.
Step 4, carries out n-type impurity ion implanting to the N-shaped InSb material of isosceles v-depression 9 bottom, it is achieved platform
The p-type doping in face 2, and form p-type isosceles triangle doped region 3, such as Fig. 4 d.
N-shaped InSb material to each isosceles v-depression 9 bottom, is 4.2 × 10 at implantation dosage13cm-2, inject energy
Under the amount process conditions for 450keV, carry out boron ion implanting, it is achieved the p-type of 256 × 256 table tops 2 is adulterated,
Formed and interior 4 isosceles v-depression 9 shapes of dielectric layer 8 in the N-shaped InSb substrate 1 of each table top 2 bottom simultaneously
The p-type isosceles triangle doped region 3 that shape is similar, the bottom side length r of p-type isosceles triangle doped region 3 is 10 μm, high h
Being 6 μm, doping content is 1 × 1017cm-3。
Step 5, removes dielectric layer 8, such as Fig. 4 e.
On dielectric layer 8, third time makes mask, uses reactive ion etching technology at CF4Flow is 20sccm, O2
Flow is 2sccm, and pressure is 20mTorr, and bias voltage is under the process conditions of 100V, and etching is removed at N-shaped InSb
Substrate 1 top, 256 × 256 table top 2 tops and the dielectric layer 8 of 256 × 256 table top 2 sides.
Step 6, on N-shaped InSb substrate 1 top, 256 × 256 table top 2 tops and 256 × 256 table top 2 sides
Deposit protective layer 4, such as Fig. 4 f.
Using plasma strengthens chemical vapor deposition techniques, at N2O flow is 850sccm, SiH4Flow is 200sccm,
Temperature is 250 DEG C, and RF power is 25W, and pressure is under the process conditions of 1100mTorr, at N-shaped InSb substrate 1
Top, 256 × 256 table top 2 tops and 256 × 256 table top 2 side deposition thicknesses are the SiO of 0.5 μm2Protective layer
4。
Step 7, etching removal N-shaped InSb substrate 1 edge upper part and the protective layer 4 on 256 × 256 table top 2 tops,
Such as Fig. 4 g.
Making mask 4th time on protective layer 4, wherein this mask pattern includes anode mask pattern and negative electrode mask pattern
Two parts, the array that anode mask pattern is made up of by the square of 40 μm 256 × 256 length of sides L, Qi Zhongxiang
Adjacent two foursquare spacing d1, edge square and N-shaped InSb substrate 1 edge between distance d2It is 30 μm；
Negative electrode mask pattern is " returning " zigzag pattern, and this " returning " zigzag pattern each inner edge length is equal and each outside length is equal, its
The length of side is 17950 μm at home and abroad, and the outer length of side is 15 μm with the spacing of the interior length of side；This mask is utilized to use reactive ion etching
Technology, at SF6Flow is 10sccm, O2Flow is 5sccm, and pressure is 15mTorr, and bias voltage is 150V's
Under process conditions, etching removes N-shaped InSb substrate 1 edge upper part and the protective layer 4 on 256 × 256 table top 2 tops.
Step 8, on table top 2 top, deposit metal makes anode 5, deposits in N-shaped InSb substrate 1 edge upper part simultaneously
Metal makes " returning " font negative electrode 6, such as Fig. 4 h.
On 256 × 256 table tops 2 and N-shaped InSb substrate 1 edge on the 5th time make mask, this mask pattern with
The mask pattern that in step 7, the 4th time makes is identical；This mask is utilized to use electron beam evaporation technique little in vacuum
In 1.8 × 10-3Pa, power bracket is 300～1100W, and evaporation rate is less thanProcess conditions under, at each table top
2 tops and Cr, Au metal that N-shaped InSb substrate 1 edge upper part deposition thickness successively is 0.04 μm/0.75 μm, and
Be 750 DEG C in temperature, the time be 20s process conditions under carry out short annealing, make anode 5 and " returning " font the moon
Pole 6.
Step 9, deposits passivation layer 7, such as Fig. 4 i in the bottom of N-shaped InSb substrate 1.
Using plasma strengthens chemical vapor deposition techniques, at N2O flow is 850sccm, SiH4Flow is 200sccm,
Temperature is 250 DEG C, and RF power is 25W, and pressure is under the process conditions of 1100mTorr, at N-shaped InSb substrate 1
The SiO that bottom deposition thickness is 0.5 μm2Passivation layer 7, thus complete the making of whole detector array.
Embodiment three: making protective layer is SiN, passivation layer is SiO2, immediately below each table top, p-type isosceles triangle is mixed
Number m=1 in miscellaneous district, array size is the InSb infrared focal plane detector array of 15000 × 15000.
Step A, etches 15000 × 15000 table tops 2 of making, such as Fig. 4 a on N-shaped InSb substrate 1.
Thickness k be 3.5 μm, doping content be 1 × 1011cm-3N-shaped InSb substrate 1 on make for the first time mask,
Inductive couple plasma reactive ion etching technology is used to etch 15000 × 15000 length of sides L of making on N-shaped InSb substrate 1
It is the square-shaped mesa 2 of 10 μm, spacing d of adjacent two table tops 21, edge table top 2 and N-shaped InSb substrate 1
Distance d between edge2Being 0.4 μm, the height H of each table top is 0.5 μm；After N-shaped InSb substrate etching
Thickness s is 3 μm.The process conditions that etching table top uses are: Ar/CH4/H2Flow-rate ratio is 1:4:13, and pressure is 20Pa,
Power is 600W.
Step B, at N-shaped InSb substrate 1 top, 15000 × 15000 table top 2 tops and 15000 × 15000 platforms
Side, face 2 dielectric layer deposited 8, such as Fig. 4 b.
Using plasma strengthens chemical vapor deposition techniques at N-shaped InSb substrate 1 top, 15000 × 15000 table tops
2 tops and 15000 × 15000 table top 2 side deposition thicknesses are the SiO of 3 μm2Dielectric layer 8.Dielectric layer deposited uses
Process conditions be: N2O flow is 800sccm, SiH4Flow is 175sccm, and temperature is 225 DEG C, and RF power is
22.5W, pressure is 1000mTorr.
Step C, in dielectric layer 8, etching makes isosceles v-depression 9, such as Fig. 4 c.
On dielectric layer 8, second time makes mask, uses reactive ion etching technology on 15000 × 15000 table tops 2
All etch in the dielectric layer 8 in portion and make 1 isosceles v-depression 9, a length of 10 μm in base of isosceles v-depression 9,
Depth of groove is 3 μm.The process conditions that etched recesses uses are: SF6Flow is 5sccm, O2Flow is 2sccm,
Pressure is 10mTorr, and bias voltage is 100V.
Step D, carries out n-type impurity ion implanting to the N-shaped InSb material of isosceles v-depression 9 bottom, it is achieved platform
The p-type doping in face 2, and form p-type isosceles triangle doped region 3, such as Fig. 4 d.
N-shaped InSb material to 15000 × 15000 interior 1 isosceles v-depression 9 bottoms of table top 2 upper dielectric layer 8
Material carries out n-type impurity ion implanting, it is achieved adulterate the p-type of each table top 2, simultaneously the n in each table top 2 bottom
The p-type isosceles triangle forming 1 isosceles v-depression 9 shape interior to dielectric layer 8 similar in type InSb substrate 1 is mixed
Miscellaneous district 3, the base r of p-type isosceles triangle doped region 3 is 10 μm, and high h is 3 μm, wherein impurity be magnesium from
Son, doping content is 1 × 1016cm-3.The process conditions that ion implanting uses are: implantation dosage is 6.3 × 109cm-2, note
Entering energy is 30keV.
Step E, removes dielectric layer 8, such as Fig. 4 e.
On dielectric layer 8, third time makes mask, uses reactive ion etching technology etching to remove at N-shaped InSb substrate 1
Top, 15000 × 15000 table top 2 tops and the dielectric layer 8 of 15000 × 15000 table top 2 sides.Etch media
The process conditions that layer uses: CF4Flow is 40sccm, O2Flow is 2.5sccm, and pressure is 12.5mTorr, power
For 225W.
Step F, at N-shaped InSb substrate 1 top, 15000 × 15000 table top 2 tops and 15000 × 15000 platforms
Side, face 2 deposit protective layer 4, such as Fig. 4 f.
Using plasma strengthens chemical vapor deposition techniques at N-shaped InSb substrate 1 top, 15000 × 15000 table tops
2 tops and 15000 × 15000 table top 2 side deposition thicknesses are the SiN protective layer 4 of 0.1 μm.Deposit protective layer is adopted
Process conditions be: gas is NH3、N2And SiH4, gas flow is respectively 2sccm, 900sccm and 200sccm,
Temperature, RF power and pressure are respectively 250 DEG C, 25W and 900mTorr.
Step G, etching removes N-shaped InSb substrate 1 edge upper part and the protection on 15000 × 15000 table top 2 tops
Layer 4, such as Fig. 4 g.
Making mask 4th time on protective layer 4, wherein this mask pattern includes anode mask pattern and cathode pattern mask
Two parts, the array that anode mask pattern is made up of by the square of 10 μm 15000 × 15000 length of sides L, its
In adjacent two foursquare spacing d1, edge square and N-shaped InSb substrate 1 edge between distance d2It is
0.4μm；Negative electrode mask pattern is " returning " zigzag pattern, should " returning " zigzag pattern each inner edge length is equal and each outer length of side
Equal, wherein a length of 156000.4 μm in outside, the outer length of side is 0.2 μm with the spacing of the interior length of side；This mask is utilized to use anti-
Answer ion etching technology, etching removal N-shaped InSb substrate 1 edge upper part and 15000 × 15000 table top 2 tops
Protective layer 4.The process conditions that etch-protecting layer uses are: CF4Flow is 45sccm, O2Flow is 5sccm, pressure
For 15mTorr, power is 250W.
Step H, on table top 2 top, deposit metal makes anode 5, deposits in N-shaped InSb substrate 1 edge upper part simultaneously
Metal makes " returning " font negative electrode 6, such as Fig. 4 h.
Mask, this mask figure is made 5th time on 15000 × 15000 table tops 2 and on N-shaped InSb substrate 1 edge
Shape is identical with the mask pattern that the in step G the 4th time makes；This mask is utilized to use electron beam evaporation technique each
Table top 2 top and N-shaped InSb substrate 1 edge upper part deposit Cr, Au metal successively, make anode 5 and " returning " word
Shape negative electrode 6, metal thickness is 0.03 μm/0.5 μm.The process conditions that deposit metal uses are: vacuum is less than
1.8×10-3Pa, power bracket is 160～960W, and evaporation rate is less thanThe process conditions that short annealing uses are:
Temperature is 800 DEG C, and the time is 15s.
Step I, deposits passivation layer 7, such as Fig. 4 i in the bottom of N-shaped InSb substrate 1.
Using electron beam evaporation technique in the bottom of N-shaped InSb substrate 1, deposition thickness is the SiO of 0.05 μm2Passivation layer
7, thus complete the making of whole detector array.The process conditions that deposit passivation layer uses are: vacuum is less than
1.2×10-3Pa, power is less than 50W, and evaporation rate is less than
The effect of the present invention can be further illustrated by following emulation.
In emulation, traditional array and array of the present invention all use the array of 7 × 7, the thickness s after N-shaped InSb substrate etching
Being 10 μm, table top size L is 40 μm, and table surface height H is 5 μm, spacing d of adjacent two table tops1With
And distance d between edge table top and N-shaped InSb edges of substrate2Being 20 μm, N-shaped InSb doping content is
1×1015cm-3, p-type InSb doping content is 1 × 1018cm-3；Each table top lower p-type isosceles three in array of the present invention
Number m=2 of dihedral doped region, the bottom side length r of p-type isosceles triangle doped region is 20 μm, and high h is 10 μm；Imitative
Radiation source in very is from passivation layer side, i.e. to carry on the back incidence, and vertical irradiation bosom pixel.
Emulation 1: dense in the hole of pixel center, bosom along incident radiation direction with array of the present invention to traditional array
Degree emulates, result such as Fig. 5.
As seen from Figure 5: along incident radiation direction in the range of the overwhelming majority of pixel center, bosom, the present invention visits
The hole concentration surveying device array is all remarkably higher than the hole concentration of traditional array, illustrates that detector array of the present invention collects current-carrying
The ability of son is apparently higher than conventional detectors array.
Emulation 2: to conventional detectors array with pixel center, bosom in detector array of the present invention along incident radiation side
To longitudinal electric field emulate, result such as Fig. 6.
As seen from Figure 6: the electric field of array of the present invention is in the main generation region of photo-generated carrier, i.e. near passivation layer
In neighbouring N-shaped InSb substrate, hence it is evident that more than the electric field of traditional array, the array of the present invention master at photo-generated carrier is described
In region to be produced, pixel center in bosom is along the extraction effect to photo-generated carrier of the longitudinal electric field in incident radiation direction
It is obviously enhanced, this greatly reduces photo-generated carrier and produce the compound action of photo-generate electron-hole pair in region, and decrease
Photo-generated carrier produces the quantity of trap capture photo-generated carrier in region so that overwhelming majority photo-generated carrier Dou Bei center
Pixel is collected, and the photo-generated carrier quantity collected by other pixels greatly reduces, the quantum efficiency of array the most of the present invention
It is significantly better than that traditional array with cross-talk.
Emulation 3: to conventional detectors array with pixel center, detector array bosom of the present invention along incident radiation direction
Transverse electric field emulate, result such as Fig. 7.
As seen from Figure 7: the electric field of array of the present invention, especially photo-generated carrier mainly produce the electric field in region,
It is significantly less than the electric field of traditional array, the pixel center, the array bosom of the present invention horizontal electricity along incident radiation direction is described
The extraction effect of photo-generated carrier is substantially reduced by field, understands in conjunction with Fig. 6 simulation result, and overwhelming majority photo-generated carriers are all
Extracted along longitudinal highfield in incident radiation direction by center pel, and the photo-generated carrier quantity collected by other pixels is big
Big minimizing, quantum efficiency and the cross-talk of array the most of the present invention are significantly better than that traditional array.
For those skilled in the art, after having understood present invention and principle, it is possible to without departing substantially from the present invention
Principle and scope in the case of, the method according to the invention carries out the various corrections in form and details and change, but
These corrections based on the present invention and change are still within the claims of the present invention.
Claims (10)
1. an InSb infrared focal plane detector array, including N-shaped InSb substrate (1) and passivation layer (7), at N-shaped
Being etched with t × t table top (2) on InSb substrate (1), t is integer and t >=1, and each table top (2) top is deposited with anode (5),
N-shaped InSb edges of substrate top is deposited with " returning " font negative electrode (6)；Described N-shaped InSb substrate (1) top and each
Face (2) side is deposited with protective layer (4), it is characterised in that: N-shaped InSb substrate (1) immediately below each table top (2)
Inside being provided with m identical p-type isosceles triangle doped region (3), m is integer and m >=1, and these p-type isosceles triangles are mixed
Miscellaneous district (3) constitutes pn-junction structure with N-shaped InSb substrate (1).
InSb infrared focal plane detector array the most according to claim 1, it is characterised in that N-shaped InSb substrate (1)
Thickness k before etching is 3.5～20 μm, and the thickness s after etching is 3～10 μm, and doping content is 1 × 1011cm-3～1 × 1016cm-3。
InSb infrared focal plane detector array the most according to claim 1, it is characterised in that each table top (2) upper,
Lower surface is square, and foursquare length of side L is 10～60 μm, and the height H of each table top is the most identical, and H deducts equal to k
S, and span is 0.5～10 μm.
InSb infrared focal plane detector array the most according to claim 1, it is characterised in that adjacent two table tops (2)
Between distance d1Distance d between edge table top and N-shaped InSb substrate (1) edge2Equal, and span is
0.4～60 μm.
InSb infrared focal plane detector array the most according to claim 1, it is characterised in that m p-type isoceles triangle
Base a length of r, the r=L/m of shape doped region (3), high h are less than or equal to the thickness s after N-shaped InSb substrate (1) etches,
And h is equal toWherein L is the length of side of square-shaped mesa, d1For the distance between adjacent two table tops.
InSb infrared focal plane detector array the most according to claim 1, it is characterised in that under each table top (2)
Surface connects with the bottom surface of m p-type triangle doped region (3) immediately below this table top.
7. the method making InSb infrared focal plane detector array, including following process:
The first step, at the upper making mask for the first time of N-shaped InSb substrate (1), utilizes this mask at N-shaped InSb substrate (1)
Upper etching makes t × t table top (2)；
Second step, in N-shaped InSb substrate (1) top, each table top (2) top and each table top (2) side deposit thickness
Degree is the dielectric layer (8) of 3～10 μm；
3rd step, makes mask in the upper second time of dielectric layer (8), utilizes this mask at the dielectric layer on each table top (2) top
(8) in, etching makes the isosceles v-depression (9) that m is identical, the degree of depth of these isosceles v-depressions (9) less than or etc.
Thickness in dielectric layer (8)；
4th step, carries out n-type impurity ion implanting to the N-shaped InSb material of each isosceles v-depression (9) bottom, it is achieved
The p-type of each table top (2) is adulterated, and forms m identical p-type isosceles triangle doping in each table top (2) bottom
District (3), and base a length of r, the r=L/m of p-type isosceles triangle doped region (3), high h is less than or equal to N-shaped InSb
Thickness s after substrate (1) etching, and h is equal toWherein L is the length of side of square-shaped mesa, d1For adjacent two platforms
Distance between face；
5th step, makes mask in the upper third time of dielectric layer (8), utilizes this mask etching to remove on N-shaped InSb substrate (1)
The dielectric layer (8) of portion, each table top (2) top and each table top (2) side；
6th step, in N-shaped InSb substrate (1) top, each table top (2) top and each table top (2) side, deposit is protected
Sheath (4), is i.e. covered each by N-shaped InSb substrate (1) top, each table top (2) top with every with insulating dielectric materials
The region of individual table top (2) side；
7th step, makes mask upper 4th time at protective layer (4), utilizes this mask etching to remove N-shaped InSb substrate (1) limit
The protective layer (4) on edge top and each table top (2) top；
8th step, above and makes mask the 5th time on N-shaped InSb substrate (1) edge at each table top (2), utilizes this mask
On each table top (2) top, deposit metal makes anode (5), simultaneously at N-shaped InSb substrate (1) edge upper part deposit gold
Belong to and make " returning " font negative electrode (6)；
9th step, in the bottom of N-shaped InSb substrate (1) deposit passivation layer (7), i.e. with saturating infra-red radiation insulating dielectric materials
Cover the region of N-shaped InSb substrate (1) bottom, thus complete the making of whole detector array.
Method the most according to claim 7, it is characterised in that described 4th step n to isosceles v-depression (9) bottom
Type InSb material carries out n-type impurity ion implanting, and doping content is 1 × 1016cm-3～1 × 1018cm-3；Process conditions are: inject
Dosage is 6.3 × 109cm-2～7 × 1013cm-2, Implantation Energy is 30keV～800keV.
Method the most according to claim 7, it is characterised in that the anode (5) of described 8th step making and negative electrode (6),
Thickness is identical, all uses identical Cr/Au double layer of metal to combine, and its thickness is 0.03～0.05 μm/0.5～1 μm, and lower metal
Thickness is less than upper strata metal thickness.
Method the most according to claim 7, it is characterised in that:
Described protective layer (4) uses SiO2、ZnS、SiN、Al2O3、Sc2O3、HfO2Or TiO2Insulating dielectric materials, its
Thickness is 0.1～1 μm；
Described passivation layer (7) uses ZnS, SiO2、SiN、Al2O3、HfO2Or TiO2Infra-red radiation insulating dielectric materials thoroughly,
Its thickness is 0.05～1 μm.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5479032A (en) * | 1994-07-21 | 1995-12-26 | Trustees Of Princeton University | Multiwavelength infrared focal plane array detector |
| US5580795A (en) * | 1993-08-10 | 1996-12-03 | Loral Vought Systems Corporation | Fabrication method for integrated structure such as photoconductive impedance-matched infrared detector with heterojunction blocking contacts |
| CN1949508A (en) * | 2006-11-08 | 2007-04-18 | 中国科学院上海技术物理研究所 | Infrared focal plane detector with antireflective convergence microlens and microlens preparing method |
| CN102201487A (en) * | 2011-03-16 | 2011-09-28 | 中国科学院上海技术物理研究所 | Method for optimizing light gathering ability of micro-lens array of back-illuminated infrared detector |
| CN102509728A (en) * | 2011-11-01 | 2012-06-20 | 北京大学 | Design and preparation method of non-refrigeration infrared detector |
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2014
- 2014-11-20 CN CN201410667776.9A patent/CN104409533B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5580795A (en) * | 1993-08-10 | 1996-12-03 | Loral Vought Systems Corporation | Fabrication method for integrated structure such as photoconductive impedance-matched infrared detector with heterojunction blocking contacts |
| US5479032A (en) * | 1994-07-21 | 1995-12-26 | Trustees Of Princeton University | Multiwavelength infrared focal plane array detector |
| CN1949508A (en) * | 2006-11-08 | 2007-04-18 | 中国科学院上海技术物理研究所 | Infrared focal plane detector with antireflective convergence microlens and microlens preparing method |
| CN102201487A (en) * | 2011-03-16 | 2011-09-28 | 中国科学院上海技术物理研究所 | Method for optimizing light gathering ability of micro-lens array of back-illuminated infrared detector |
| CN102509728A (en) * | 2011-11-01 | 2012-06-20 | 北京大学 | Design and preparation method of non-refrigeration infrared detector |
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