CN104467796A - Slew-rate-limited driver - Google Patents
Slew-rate-limited driver Download PDFInfo
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- CN104467796A CN104467796A CN201410624465.4A CN201410624465A CN104467796A CN 104467796 A CN104467796 A CN 104467796A CN 201410624465 A CN201410624465 A CN 201410624465A CN 104467796 A CN104467796 A CN 104467796A
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Abstract
The invention belongs to the field of micro-electronics, and particularly relates to a slew-rate-limited driver. Drive control is carried out on grid electrodes of a drive tube through two comparators, charging and discharging of a capacitor are carried out through a pull-up switch, a pull-down switch and a current source in a cooperative mode, the effect of controlling the output voltage slew rate is realized, and EMI and power source feed through problems can be effectively reduced. Meanwhile, the slew-rate-limited driver does not need a large resistor, and influence of the temperature excursion effect of the resistor on the output voltage slew rate is avoided. In addition, the slew-rate-limited driver is simple in circuit structure and easy to realize, output voltage in a wide temperature change range can still keep a stable slew rate, and the requirements for the speed and slew rate are also taken into account.
Description
Technical field
The invention belongs to microelectronic, particularly relate to a kind of limit Slew Rate driver.
Background technology
Serial interface circuit is morning time because it is born, easy to use, and with low cost, go for the many reasons such as extensive long range propagation, be widely used, especially at industrial automation, a large amount of equipment adopts various serial interface circuit to connect always.
Theory analysis and experimental result show, comparatively slow slew rate can effectively suppress transmission line impedance not mate the reflection caused, and can reduce the connecting line of bus to device to the impact of signal, simplify the connection of device.Therefore, when designing driver, under the prerequisite ensureing transmission rate, the slew rate of output signal should be slowed down as far as possible.
The method of common restriction output voltage slew rate produces certain time delay by cascade resistance and electric capacity, changes the slew rate of driving tube input signal, thus realize the slew rate changing driving tube output voltage.Fig. 1 is the typical circuit of the limit Slew Rate driver of prior art, input signal INPUT enters buffer stage 1 and buffer stage 2 respectively after current-limiting resistance R1 and gate circuit, the output signal of buffer stage 1 is through the RC time delay network that be made up of resistance R2, electric capacity C1 to drive PMD1 driving tube, and the RC time delay network that the output signal process of buffer stage 2 is made up of resistance R3, electric capacity C2 carrys out driving N MD1 driving tube.Changed the voltage Slew Rate of driving tube PMD1 and NMD1 input signal by RC time delay, realize the function changing driving tube output voltage slew rate.
Due to slew rate and RC time delay direct proportionality, namely Slew Rate is larger, and the resistance of requirement and electric capacity are also larger, in CMOS technology, make large resistance and electric capacity all needs to use very large chip area, therefore, the method is not suitable for the larger occasion of requirement slew rate.In addition, due to the temperature drift effect of resistance itself, when there is wider range of temperature, the change in resistance of resistance is comparatively large, can cause the instability of output voltage Slew Rate.
Summary of the invention
In view of this, namely object of the present invention is to provide a kind of limit Slew Rate driver, needs large resistance, electric capacity could realize larger Slew Rate with the driver solving prior art, and the problem of output voltage Slew Rate fluctuation in wide range of temperature.
Limit Slew Rate driver provided by the invention, comprising: the first comparator A, the second comparator B, switch S 1, switch S 2, switch S 3, switch S 4, first driving tube PMD and electric capacity Cp, the second driving tube NMD and electric capacity Cn, Single-to-differenticonversion conversion circuit and level shifting circuit;
The positive-negative input end input voltage of described first comparator A is respectively 3/4VPOS and VPOS, the output of described first comparator A connects the grid of described switch S 1, switch S 2 and described first driving tube PMD simultaneously, and described electric capacity Cp is serially connected between described switch S 2 and negative supply VNEG; The positive-negative input end input voltage of described second comparator B is respectively 3/4VNEG and VNEG, the output of described second comparator B connects the grid of described switch S 4, switch S 3 and described second driving tube NMD simultaneously, and described electric capacity Cn is serially connected between described switch S 3 and positive supply VPOS;
The input termination input signal INPUT of described Single-to-differenticonversion conversion circuit, level shifting circuit is transferred to after input signal INPUT being converted to contrary signal V+ and V-of two phase places, the output of described level shifting circuit connects described switch S 1, switch S 2, switch S 3 and switch S 4 simultaneously, and the action controlling described switch S 1 and switch S 3 is synchronous, the action of switch S 2 and switch S 4 is synchronous;
The source electrode of described first driving tube PMD meets VPOS, and the source electrode of described second driving tube NMD meets VNEG, the drain electrode of described first driving tube PMD and the drain electrode of described second driving tube NMD meet the signal output part OUTPUT held as described driver altogether;
Described positive supply VPOS and negative supply VNEG refers to respectively and is carried out changing by the single ended voltage VDD of input by charge pump and the malleation VPOS obtained and negative pressure VNEG.
According to limit Slew Rate driver provided by the invention, by two comparators, drived control is carried out to the grid of driving tube, coordinate pull-up, pull down switch and current source to the discharge and recharge of electric capacity, reach the effect controlling output voltage Slew Rate, EMI and power supply feedthrough problem can be effectively reduced.Meanwhile, because this limit Slew Rate driver is without the need to adopting large resistance, it also avoid the temperature drift effect of resistance to the impact of output voltage Slew Rate.Further, the circuit structure of this limit Slew Rate driver is simple, and be easy to realize, the output voltage in wide temperature excursion still can keep stable Slew Rate, can take into account the requirement of speed and Slew Rate simultaneously.
Accompanying drawing explanation
Fig. 1 is the typical circuit limitting Slew Rate driver in prior art
Fig. 2 is the structure principle chart of the limit Slew Rate driver that one embodiment of the invention provides;
Fig. 3 is the structural representation of the Single-to-differenticonversion conversion circuit that one embodiment of the invention provides;
Fig. 4 is the structural representation of the level shifting circuit that one embodiment of the invention provides;
Fig. 5 is the structural representation of the limit Slew Rate driver that another embodiment of the present invention provides;
Fig. 6 is the waveform schematic diagram in the Slew Rate of limit shown in Fig. 5 drive operation process.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Fig. 2 is the structure principle chart of the limit Slew Rate driver that one embodiment of the invention provides; For convenience of explanation, illustrate only part related to the present embodiment, as shown in the figure:
A kind of limit Slew Rate driver, comprising: the first comparator A, the second comparator B, switch S 1, switch S 2, switch S 3, switch S 4, first driving tube PMD and electric capacity Cp, the second driving tube NMD and electric capacity Cn, Single-to-differenticonversion conversion circuit 100 and level shifting circuit 200.
Concrete structure is see Fig. 2, the input voltage of the positive-negative input end of the first comparator A is respectively 3/4VPOS and VPOS, the output of the first comparator A connects the grid of switch S 1, switch S 2 and the first driving tube PMD simultaneously, and electric capacity Cp is serially connected between switch S 2 and negative supply VNEG; The input voltage of the positive-negative input end of the second comparator B is respectively 3/4VNEG and VNEG, and the output of the second comparator B connects the grid of switch S 4, switch S 3 and the second driving tube NMD simultaneously, and electric capacity Cn is serially connected between switch S 3 and positive supply VPOS;
The input termination input signal INPUT of Single-to-differenticonversion conversion circuit 100, is transferred to level shifting circuit 200 after input signal INPUT being converted to contrary signal V+ and V-of two phase places; The output of level shifting circuit 200 connects switch S 1, switch S 2, switch S 3 and switch S 4 simultaneously, controls to make that the action of switch S 1 and switch S 3 is synchronous, the action of switch S 2 and switch S 4 is synchronous by output signal V_shift; The source electrode of the first driving tube PMD meets positive supply VPOS, and the source electrode of the second driving tube NMD meets negative supply VNEG, the drain electrode of the first driving tube PMD and the drain electrode of the second driving tube NMD meet the signal output part OUTPUT held as this limit Slew Rate driver altogether.
When specific implementation, above-mentioned positive supply VPOS and negative supply VNEG can be respectively and be carried out changing by the single ended voltage VDD of input by the charge pump 300 in figure and the malleation VPOS obtained and negative pressure VNEG.
According to the above-mentioned limit Slew Rate driver that the embodiment of the present invention provides, by two comparators, drived control is carried out to the grid of driving tube, coordinate pull-up, pull down switch and current source to the discharge and recharge of electric capacity, reach the effect controlling output voltage Slew Rate, EMI and power supply feedthrough problem can be effectively reduced.Meanwhile, because this limit Slew Rate driver is without the need to adopting large resistance, it also avoid the temperature drift effect of resistance to the impact of output voltage Slew Rate.
As a preferred embodiment, limit Slew Rate driver can also comprise be serially connected in input signal INPUT and described Single-to-differenticonversion conversion circuit 100 input between the first flow-restriction 400.
Further, this limit Slew Rate driver can also comprise be serially connected in first driving tube PMD drain and the second driving tube NMD drain connect the second flow-restriction 500 held between signal output part OUTPUT altogether.
Continue see Fig. 2, described first flow-restriction 400 comprises resistance R1; This resistance R1 is just serially connected between the input of input signal INPUT and Single-to-differenticonversion conversion circuit 100.
Described second flow-restriction 500 comprises resistance R2; What the first termination first driving tube PMD drain electrode of this resistance R2 and the second driving tube NMD drained connects end, the second termination signal output OUTPUT of resistance R2 altogether.
In the specific implementation process of limit Slew Rate driver as shown in Figure 2, by charge pump 300, the single ended voltage VDD of input can be converted to malleation VPOS and negative pressure VNEG, malleation VPOS and negative pressure VNEG is respectively the power supplies such as level shifting circuit 200, first comparator A, the second comparator B, the first driving tube PMD and the second driving tube NMD as power supply.Input signal INPUT exports contrary signal V+ and V-of two phase places through the first flow-restriction 400 and Single-to-differenticonversion conversion circuit 100.Because Single-to-differenticonversion conversion circuit 100 is powered by power vd D, therefore the low and high level of V+ and V-is respectively VDD and GND, because the output level of the Slew Rate driver that is limited will be positive/negative-pressure, so V+ and V-also needs the V_shift (being malleation VPOS and negative pressure VNEG) being converted to positive/negative-pressure by level shifting circuit 200.After level shifting circuit 300 outputs signal V_shift, the break-make of V_shift difference control switch S1 ~ S4, the action of maintained switch S1 and switch S 3 is synchronous, and the action of switch S 2 and switch S 4 is synchronous.
Because the anode input voltage of the first comparator A, lower than negative terminal input voltage, does not consider the impact of external switch and electric capacity, the voltage PGD of the first comparator A output should be low level; Same, because the anode input voltage of the second comparator B is higher than negative terminal input voltage, when not considering the affecting of external switch and electric capacity, the voltage NGD of the second comparator B output should be high level.
Therefore, when input signal INPUT is high level, V_shift is low level, switch S 1 and switch S 3 conducting, switch S 2 and switch S 4 turn off, and the first comparator A output is quickly pulled up VPOS, and PGD is high level, second comparator B is charged to electric capacity Cn with constant current I2 by internal current source, and NGD slowly changes to high level.Now, the first driving tube PMD turns off, when NGD rise to make the value of NGD-VNEG be greater than the cut-in voltage Vtn of the second driving tube NMD time, the second driving tube NMD conducting, driver output signal OUTPUT slowly drops to low level.
In like manner, when input signal INPUT is low level, V_shift is high level, switch S 1 and switch S 3 turn off, switch S 2 and switch S 4 conducting, electric capacity Cp is discharged with constant current I1 by the first comparator A internal current source, and PGD slowly changes to low level, second comparator B output is pulled down to VNEG rapidly, and NGD is low level.Now the second driving tube NMD turns off, when PGD drops to the cut-in voltage making VPOS-PGD value be greater than the first driving tube PMD | and during Vtp|, the first driving tube PMD conducting, driver output signal OUTPUT slowly rises to high level.
When specific implementation, the structure of Single-to-differenticonversion conversion circuit 100 can be as shown in Figure 3.See Fig. 3, this Single-to-differenticonversion conversion circuit 100 comprises the first inverter F1, the second inverter F2 and the 3rd inverter F3; Wherein, the input of the first inverter F1 is the input of Single-to-differenticonversion conversion circuit 100, the output of the first inverter F1 be Single-to-differenticonversion conversion circuit 100 the first output, for outputing signal V+, the output of the first inverter F1 also connects the input of the second inverter F2 and the output of the 3rd inverter F3 simultaneously, the output of the second inverter F2 and the input of the 3rd inverter F3 connect the second output as described Single-to-differenticonversion conversion circuit 100 altogether, for outputing signal V-.
Fig. 4 again show the structural representation of the level shifting circuit 200 that one embodiment of the invention provides; For convenience of explanation, again illustrate only part related to the present embodiment, as shown in the figure:
Level shifting circuit 200 comprises: PMOS P1, PMOS P2, PMOS P3, PMOS P4, NMOS tube N1, NMOS tube N2, NMOS tube N3 and NMOS tube N4, wherein, the grid of NMOS tube N2 meets signal V-, the grid of NMOS tube N3 meets signal V+, the source electrode of NMOS tube N2 and the source electrode of NMOS tube N3 all ground connection, the drain electrode of NMOS tube N2 connects the drain electrode of PMOS P2 simultaneously, the grid of PMOS P3, the grid of PMOS P4, the drain electrode of NMOS tube N3 connects the drain electrode of PMOS P3 simultaneously, the grid of PMOS P1, the grid of PMOS P2, the source electrode of PMOS P1, the source electrode of PMOS P2, the source electrode of PMOS P3, the source electrode of PMOS P4 all meets VPOS, the drain electrode of PMOS P1 connects the drain electrode of NMOS tube N1 and the grid of NMOS tube N4 simultaneously, the source electrode of NMOS tube N1 and the source electrode of NMOS tube N4 meet VNEG simultaneously, the grid of NMOS tube N1, the drain electrode of NMOS tube N4 and the drain electrode of PMOS P4 connect the output into described level shifting circuit 200 altogether, output signal V_shift.
Particularly, the function of level shifting circuit 200 is that logic low and high level is converted to by VDD and GND the V_shift that low and high level is respectively VPOS and VNEG.When V+ be high level, V-be low level time, NMOS tube N3 conducting, NMOS tube N2 turn off, now, the drain electrode output low level of NMOS tube N3, the drain electrode of NMOS tube N2 exports high level; Because the drain electrode of NMOS tube N3 connects the grid of PMOS P1 and the grid of PMOS P2 simultaneously, the grid of PMOS P1 and the grid of PMOS P2 are also all low level, PMOS P1 and PMOS P2 also conducting; Now, the drain electrode of PMOS P1 is high level, NMOS tube N4 conducting; Because the drain electrode of NMOS tube N2 connects the grid of PMOS P3 and the grid of PMOS P4, the grid of PMOS P3 and the grid of PMOS P4 are high level, and PMOS P and PMOS P4 turns off, and the drain electrode of PMOS P4 is low level, and namely V_shift is low level VNEG.In like manner, when V+ be low level, V-be high level time, V_shift is high level VPOS.
Fig. 5 is the structural representation of the limit Slew Rate driver that another embodiment of the present invention provides; In the present embodiment, the internal structure composition of the first comparator A and the second comparator B is shown, see Fig. 5:
First comparator A is made up of NMOS tube N8, NMOS tube N9, PMOS P6, PMOS P7, PMOS P16 and current source I10 and I1, wherein NMOS tube N8, N9 and PMOS P6, P7 and current source I10 form the first order circuit of this first comparator A, and PMOS P16, switch S 2 and current source I1 form the second level circuit of this first comparator A; Second comparator B is made up of PMOS P12, PMOS P13, NMOS tube N14, NMOS tube N 15, NMOS tube N 17 and current source I20 and I2, wherein PMOS P12, P13 and NMOS tube N14, N15 and current source I20 form the first order circuit of this second comparator B, and NMOS tube N17, switch S 3 and current source I2 form the second level circuit of this second comparator B; Show the annexation of electric capacity Cp, electric capacity Cn and switch S 1, switch S 4 and the first driving tube PMD, the second driving tube NMD in addition.
As preferably, in the present embodiment, after the input of INPUT signal, before output OUTPUT, all add a current-limiting resistance as flow-restriction, it can ensure the stable and reliability that whole driver signal transmits.
On the other hand, in the present embodiment, switch S 1-S4 is the MOS switching tube selected.See Fig. 5, level shifting circuit 200 exports V_shift, connects the control end (i.e. the grid of MOS switching tube) of each MOS switching tube simultaneously.In fact, in specific implementation process, switch S 1-S4 also can adopt triode as switching tube, realizes identical function and efficacy.
Driver schematic diagram according to Fig. 5, when input signal INPUT is high level, V_shift is low level, switch S 1 and S3 conducting, switch S 2 and S4 turn off, and the first comparator A output is quickly pulled up VPOS, and PGD is high level, current source I2 charges to electric capacity Cn, and NGD slowly changes to high level.Now, the first driving tube PMD turns off, when NGD rise to make the value of NGD-VNEG be greater than the cut-in voltage Vtn of the second driving tube NMD time, the second driving tube NMD conducting, driver output signal OUTPUT slowly drops to low level.
In like manner, when input signal INPUT is low level, V_shift is high level, switch S 1 and S3 turn off, switch S 2 and S4 conducting, and electric capacity Cp is discharged by current source I1, PGD slowly changes to low level, and the output of the second comparator B is pulled down to VNEG rapidly, and NGD is low level.Now the second driving tube NMD turns off, when PGD drops to the cut-in voltage making VPOS-PGD value be greater than the first driving tube PMD | and during Vtp|, the first driving tube PMD conducting, driver output signal OUTPUT slowly rises to high level.
Parasitic gate electric capacity due to driving tube can be thought to fix, and the capacitance of electric capacity Cp and electric capacity Cn is all fixing, and from slew rate formula V/t=I/C, the current value size of current source determines the voltage Slew Rate of driving tube grid voltage NGD and PGD; Again because the voltage Slew Rate of driving tube grid voltage NGD and PGD determines the Slew Rate of output voltage, so export the size that Slew Rate is proportional to current source.
Fig. 6 is the waveform schematic diagram in the limit Slew Rate drive operation process shown in Fig. 5, and it can show the working method of this driver more intuitively.The waveform schematic diagram that curve sets forth input signal INPUT, exports to the grid voltage NGD of the second driving tube NMD, exports to the grid voltage PGD of the first driving tube PMD and output signal OUTPUT.
When input signal INPUT is by high step-down, switch S 1 and S3 turn off, switch S 2 and S4 conducting, and NGD is pulled down to low level rapidly, and the second driving tube NMD turns off, the electric current flowing through the second driving tube NMD close to zero, NGD Slew Rate curve as shown in 421; PGD discharges electric charge by electric capacity Cp, PGD Slew Rate as shown in curve 431, when PGD drops to the cut-in voltage making VPOS-PGD value be greater than the first driving tube PMD | during Vtp|, the first driving tube PMD conducting, output signal is for high, and output signal Slew Rate curve is as shown in curve 441.
When input signal INPUT is by low uprising, switch S 1 and S3 conducting, switch S 2 and S4 turn off, and PGD is quickly pulled up high level, and the first driving tube PMD turns off, the electric current flowing through the first driving tube PMD close to zero, PGD Slew Rate curve as shown in 432; NGD is charged by electric capacity Cn, NGD Slew Rate as shown in curve 422, when NGD rise to make the value of NGD-VNEG be greater than the cut-in voltage Vtn of the second driving tube NMD time, the second driving tube NMD conducting, outputs signal as low, and output signal Slew Rate curve is as shown in curve 442.
As can be seen from Figure 6, the trailing edge Slew Rate of NGD is greater than the trailing edge Slew Rate of PGD, and the rising edge Slew Rate of NGD is less than the rising edge Slew Rate of PGD, when signal overturns, there is not the situation of the second driving tube NMD and the first driving tube PMD conducting simultaneously, efficiently reduce power supply feedthrough problem especially.
According to limit Slew Rate driver provided by the invention, by two comparators, drived control is carried out to the grid of driving tube, coordinate pull-up, pull down switch and current source to the discharge and recharge of electric capacity, reach the effect controlling output voltage Slew Rate, EMI and power supply feedthrough problem can be effectively reduced.Meanwhile, because this limit Slew Rate driver is without the need to adopting large resistance, it also avoid the temperature drift effect of resistance to the impact of output voltage Slew Rate.Further, the circuit structure of this limit Slew Rate driver is simple, and be easy to realize, the output voltage in wide temperature excursion still can keep stable Slew Rate, can take into account the requirement of speed and Slew Rate simultaneously.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, although with reference to previous embodiment to invention has been comparatively detailed description, for a person skilled in the art, it still can be modified to the technical scheme described in foregoing embodiments or carry out equivalent replacement to wherein portion of techniques feature.All any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. limit a Slew Rate driver, it is characterized in that, described driver comprises:
First comparator A, the second comparator B, switch S 1, switch S 2, switch S 3, switch S 4, first driving tube PMD and electric capacity Cp, the second driving tube NMD and electric capacity Cn, Single-to-differenticonversion conversion circuit and level shifting circuit;
The positive-negative input end input voltage of described first comparator A is respectively 3/4VPOS and VPOS, the output of described first comparator A connects the grid of described switch S 1, switch S 2 and described first driving tube PMD simultaneously, and described electric capacity Cp is serially connected between described switch S 2 and negative supply VNEG; The positive-negative input end input voltage of described second comparator B is respectively 3/4VNEG and VNEG, the output of described second comparator B connects the grid of described switch S 4, switch S 3 and described second driving tube NMD simultaneously, and described electric capacity Cn is serially connected between described switch S 3 and positive supply VPOS;
The input termination input signal INPUT of described Single-to-differenticonversion conversion circuit, level shifting circuit is transferred to after input signal INPUT being converted to contrary signal V+ and V-of two phase places, the output of described level shifting circuit connects described switch S 1, switch S 2, switch S 3 and switch S 4 simultaneously, and the action controlling described switch S 1 and switch S 3 is synchronous, the action of switch S 2 and switch S 4 is synchronous;
The source electrode of described first driving tube PMD meets VPOS, and the source electrode of described second driving tube NMD meets VNEG, the drain electrode of described first driving tube PMD and the drain electrode of described second driving tube NMD meet the signal output part OUTPUT held as described driver altogether;
Described positive supply VPOS and negative supply VNEG refers to respectively and is carried out changing by the single ended voltage VDD of input by charge pump and the malleation VPOS obtained and negative pressure VNEG.
2. limit Slew Rate driver as claimed in claim 1, is characterized in that, described driver also comprise be serially connected in input signal INPUT and described Single-to-differenticonversion conversion circuit input between the first flow-restriction.
3. limit Slew Rate driver as claimed in claim 2, it is characterized in that, described first flow-restriction comprises resistance R1; Described resistance R1 is serially connected between the input of input signal INPUT and described Single-to-differenticonversion conversion circuit.
4. limit Slew Rate driver as claimed in claim 2, is characterized in that, described driver also comprises and is serially connected in described first driving tube PMD and drains and described second driving tube NMD drains connects the second flow-restriction held between signal output part OUTPUT altogether.
5. limit Slew Rate driver as claimed in claim 4, it is characterized in that, described second flow-restriction comprises resistance R2; What described in first termination of described resistance R2, the first driving tube PMD drain electrode drained with described second driving tube NMD connects end, the second termination signal output OUTPUT of described resistance R2 altogether.
6. the limit Slew Rate driver as described in any one of claim 1-5, is characterized in that, described Single-to-differenticonversion conversion circuit comprises the first inverter F1, the second inverter F2 and the 3rd inverter F3;
The input of described first inverter F1 is the input of described Single-to-differenticonversion conversion circuit, the output of described first inverter F1 be described Single-to-differenticonversion conversion circuit the first output, for outputing signal V+, the output of described first inverter F1 also connects the input of described second inverter F2 and the output of the 3rd inverter F3 simultaneously, and the output of described second inverter F2 and the input of the 3rd inverter F3 connect altogether as the second output of described Single-to-differenticonversion conversion circuit, for outputing signal V-.
7. limit Slew Rate driver as claimed in claim 6, it is characterized in that, described level shifting circuit comprises: PMOS P1, PMOS P2, PMOS P3, PMOS P4, NMOS tube N1, NMOS tube N2, NMOS tube N3 and NMOS tube N4;
The grid of described NMOS tube N2 meets signal V-, the grid of described NMOS tube N3 meets signal V+, the source electrode of described NMOS tube N2 and the source electrode of NMOS tube N3 all ground connection, the drain electrode of described NMOS tube N2 connects the drain electrode of described PMOS P2, the grid of described PMOS P3, the grid of described PMOS P4 simultaneously, the drain electrode of described NMOS tube N3 connects the drain electrode of described PMOS P3, the grid of described PMOS P1, the grid of described PMOS P2 simultaneously, the source electrode of described PMOS P1, the source electrode of PMOS P2, the source electrode of PMOS P3, the source electrode of PMOS P4 all meet VPOS
The drain electrode of described PMOS P1 connects the drain electrode of described NMOS tube N1 and the grid of NMOS tube N4 simultaneously, the source electrode of described NMOS tube N1 and the source electrode of NMOS tube N4 meet VNEG simultaneously, and the drain electrode of the grid of described NMOS tube N1, the drain electrode of NMOS tube N4 and PMOS P4 connects the output into described level shifting circuit altogether.
8. limit Slew Rate driver as claimed in claim 1, it is characterized in that, described switch S 1, switch S 2, switch S 3 and switch S 4 are MOS switching tube.
9. limit Slew Rate driver as claimed in claim 1, it is characterized in that, described switch S 1, switch S 2, switch S 3 and switch S 4 are triode.
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| CN107368441A (en) * | 2016-05-13 | 2017-11-21 | 赛普拉斯半导体公司 | Configurable and power optimization integrated grid driver and Type C SoC for USB transmissions of electricity |
| WO2018160204A1 (en) * | 2017-02-28 | 2018-09-07 | Linear Technology Llc | Methods and systems of reducing charge pump substrate noise |
| CN109039327A (en) * | 2018-10-18 | 2018-12-18 | 上海艾为电子技术股份有限公司 | A kind of level shifting circuit |
| CN111030726A (en) * | 2019-12-13 | 2020-04-17 | 展讯通信（上海）有限公司 | Radio frequency front end control circuit and control method thereof, radio frequency front end control chip, system, storage medium and terminal |
| CN112187199A (en) * | 2020-10-27 | 2021-01-05 | 广东工业大学 | Operational transconductance amplifier |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4622482A (en) * | 1985-08-30 | 1986-11-11 | Motorola, Inc. | Slew rate limited driver circuit which minimizes crossover distortion |
| JPH11317653A (en) * | 1998-05-01 | 1999-11-16 | Nec Corp | Slew rate control method and circuit including prevention of through-current |
| CN1913370A (en) * | 2005-07-14 | 2007-02-14 | 阿尔特拉公司 | Apparatus and methods for programmable slew rate control in transmitter circuits |
| CN101814912A (en) * | 2009-02-25 | 2010-08-25 | 北京芯技佳易微电子科技有限公司 | Negative voltage level conversion circuit |
| CN103066988A (en) * | 2012-12-18 | 2013-04-24 | 深圳国微技术有限公司 | Interface circuit and achievement method for limiting output port voltage slew rate |
| CN103856206A (en) * | 2012-12-06 | 2014-06-11 | 上海华虹集成电路有限责任公司 | Low-to-high logic level conversion circuit |
-
2014
- 2014-11-07 CN CN201410624465.4A patent/CN104467796B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4622482A (en) * | 1985-08-30 | 1986-11-11 | Motorola, Inc. | Slew rate limited driver circuit which minimizes crossover distortion |
| JPH11317653A (en) * | 1998-05-01 | 1999-11-16 | Nec Corp | Slew rate control method and circuit including prevention of through-current |
| CN1913370A (en) * | 2005-07-14 | 2007-02-14 | 阿尔特拉公司 | Apparatus and methods for programmable slew rate control in transmitter circuits |
| CN101814912A (en) * | 2009-02-25 | 2010-08-25 | 北京芯技佳易微电子科技有限公司 | Negative voltage level conversion circuit |
| CN103856206A (en) * | 2012-12-06 | 2014-06-11 | 上海华虹集成电路有限责任公司 | Low-to-high logic level conversion circuit |
| CN103066988A (en) * | 2012-12-18 | 2013-04-24 | 深圳国微技术有限公司 | Interface circuit and achievement method for limiting output port voltage slew rate |
Non-Patent Citations (1)
| Title |
|---|
| 刘正，游轶雄，王健，许继衡: "CMOS线驱动器输出信号压摆率控制的研究", 《微电子学》 * |
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| CN107368441A (en) * | 2016-05-13 | 2017-11-21 | 赛普拉斯半导体公司 | Configurable and power optimization integrated grid driver and Type C SoC for USB transmissions of electricity |
| US10254820B2 (en) | 2016-05-13 | 2019-04-09 | Cypress Semiconductor Corporation | Configurable and power-optimized integrated gate-driver for USB power-delivery and type-C SoCs |
| CN107368441B (en) * | 2016-05-13 | 2019-08-16 | 赛普拉斯半导体公司 | Configurable and power optimization integrated grid driver and Type-C SoC for USB transmission of electricity |
| US10802571B2 (en) | 2016-05-13 | 2020-10-13 | Cypress Semiconductor Corporation | Configurable and power-optimized integrated gate-driver for USB power-delivery and type-C SoCs |
| WO2018160204A1 (en) * | 2017-02-28 | 2018-09-07 | Linear Technology Llc | Methods and systems of reducing charge pump substrate noise |
| US10749429B2 (en) | 2017-02-28 | 2020-08-18 | Linear Technology Llc | Methods and systems of reducing charge pump substrate noise |
| CN109039327A (en) * | 2018-10-18 | 2018-12-18 | 上海艾为电子技术股份有限公司 | A kind of level shifting circuit |
| CN111030726A (en) * | 2019-12-13 | 2020-04-17 | 展讯通信（上海）有限公司 | Radio frequency front end control circuit and control method thereof, radio frequency front end control chip, system, storage medium and terminal |
| CN111030726B (en) * | 2019-12-13 | 2022-02-25 | 展讯通信（上海）有限公司 | Radio frequency front end control circuit and control method thereof, radio frequency front end control chip, system, storage medium and terminal |
| CN112187199A (en) * | 2020-10-27 | 2021-01-05 | 广东工业大学 | Operational transconductance amplifier |
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