CN104467909A

CN104467909A - Receiving and sending circuit of configurable PCI bus based on FPGA technology

Info

Publication number: CN104467909A
Application number: CN201410807931.2A
Authority: CN
Inventors: 张宇; 常涛; 谢建庭; 苏红; 宋光伟
Original assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Current assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Priority date: 2014-12-23
Filing date: 2014-12-23
Publication date: 2015-03-25
Anticipated expiration: 2034-12-23
Also published as: CN104467909B

Abstract

The invention relates to a receiving and sending circuit of a configurable PCI bus based on the FPGA technology. The circuit comprises an FPGA device, a PCI top-layer module is arranged in the FPGA device and comprises an instantiated ALTERA PCI IP core, a rear-end matching circuit, a peripheral circuit control module and a storage circuit control module, and all the modules are packaged into a whole through the PCI top-layer module. The function of a dedicated chip is transferred into the FPGA device, the area of a board card is saved, and cost is lowered. High transportability is achieved, the device and a pin can be modified according to the actual needs of the board card, and a peripheral circuit and a memorizer can be expanded conveniently. The receiving and sending circuit is achieved through a programmable logic device, and is simple in structure, fast in operation and high in reliability.

Description

A kind of transmission circuit of the configurable pci bus based on FPGA technology

Technical field

The present invention relates to digital communication system, particularly a kind of transmission circuit of the configurable pci bus based on FPGA technology.

Background technology

PCI is the abbreviation of Peripheral Component Interconnect (Peripheral Component Interconnect standard), and the main purpose of formulation pci bus standard is the high-speed communication in order to realize peripheral equipment and processor.Pci bus slot is current most popular interface, can easily for various functional cards expanded by computer.Realize pci bus transmission traditionally based on special chip, such as chip PCI9054 etc.This transmission means exists that chip area footprints is comparatively large, cost is higher, portability is strong and the application comparatively defect such as inconvenience.

Summary of the invention

The defect existed in view of prior art and deficiency, the invention provides a kind of transmission circuit of the configurable pci bus based on FPGA technology.

The technical scheme that the present invention takes is: a kind of transmission circuit of the configurable pci bus based on FPGA technology, it is characterized in that: this transmission circuit comprises FPGA device, FPGA device inside comprises PCI top-level module, PCI top-level module comprises the ALTERA PCI IP kernel of instantiation, rear end match circuit, peripheral circuit control module and memory circuitry control module, and the ALTERA PCI IP kernel of wherein instantiation is connected with rear end match circuit; Rear end match circuit is connected with peripheral circuit control module and memory circuitry control module respectively; The ALTERA PCI IP kernel of instantiation is connected with golden finger by pci bus; Peripheral circuit control module is connected with the peripheral circuit on board; Memory circuitry control module is connected with the peripheral memory on board; Whole module is as a whole by the encapsulation of PCI top-level module.

Peripheral circuit control module of the present invention comprises LCDs and controls submodule, toggle switch control submodule, LED light control submodule and temperature sensor control submodule; LCDs control module, toggle switch control submodule, LED light controls submodule and is connected with the rear end match circuit in PCI top-level module respectively with temperature sensor control submodule, and the pci clock signal in pci bus signal and reset signal access LCDs control submodule respectively, toggle switch controls submodule, LED light controls submodule and temperature sensor controls submodule.

Feature of the present invention and beneficial effect are: 1, move in FPGA device by the function that special chip realizes, save board area, reduce costs.2, portable strong, can modify to device and pin according to the actual needs of board, and facilitate the expansion of peripheral circuit and memory; 3, adopt programmable logic device to realize, structure is simple, and computing is rapid, and reliability is high.

Accompanying drawing explanation

Fig. 1 is integrated circuit theory diagram;

Fig. 2 is the PCI IP kernel module map after instantiation;

Fig. 3 be in Fig. 1 rear end match circuit by finite state machine status transition diagram;

Fig. 4 is peripheral circuit module theory diagram;

Fig. 5 is memory circuitry control module theory diagram.

Embodiment

Below in conjunction with accompanying drawing, the invention will be further described:

As shown in Figure 1, a kind of transmission circuit of configurable pci bus of FPGA technology comprises FPGA(Field Programmable Gate Array) device, FPGA device inside comprises PCI top-level module, PCI top-level module comprises the ALTERA PCI IP kernel of instantiation, rear end match circuit, peripheral circuit control module and memory circuitry control module, and the ALTERA PCI IP kernel of wherein instantiation is connected with rear end match circuit; Rear end match circuit is connected with peripheral circuit control module and memory circuitry control module respectively; The ALTERA PCI IP kernel of instantiation is connected with golden finger by pci bus; Peripheral circuit control module is connected with the peripheral circuit on board; Memory circuitry control module is connected with the peripheral memory on board; Whole module is as a whole by the encapsulation of PCI top-level module.

The ALTERA PCI IP kernel of instantiation has two parts of signals, pci bus holding wire is connected with the golden finger of board by the relevant I/O mouth of FPGA, as the medium with compunication, PCI IP kernel is connected with rear end match circuit after pci bus signal is converted to local side bus signals.Rear end match circuit is by the interpretation to local bus signal, determine the working method of this communication transaction, and the sensing position of address space, when pointing to IO space, rear module transmits control command and data by the holding wire be connected with peripheral circuit control module, and carries out relevant action by the peripheral circuit on the I/O port Control card of FPGA; And the data that peripheral circuit is replied can be fed back to IP kernel by 32 bidirectional data signal line of local side.When pointing to storage space, rear end match circuit transmits control command and data by the holding wire be connected with memory control module, carries out two-way communication with the extended menory on board.Above all functions module encapsulates with PCI top-level module.

As shown in Figure 2, ALTERA PCI MegaCore of the present invention is an IP kernel meeting PCI specification, through strict timing optimization, can carry out parameter configuration as requested, for completing the mutual conversion between pci bus agreement and local side bus.According to the master-slave role of FPGA in pci bus and the data bit width of transmission, this IP kernel can support four kinds of patterns: pci_mt64, pci_t64, pci_mt32, pci_t32.This transmission circuit between computer and PCI board, transmits 32 bit data by pci interface, the driving generated by windriver and upper computer software carry out Control card work, operating frequency 33MHz, so IP kernel is set to 32 from pattern pci_t32, PCI agreement supports IO space, storage space and configuration space three kinds of address spaces, configuration space comprises some intrinsic informations of PCI equipment, the value arranging related register can be set in interface at IP kernel, arrange as follows, Device ID=0x0082, Vendor ID=0x1172, Revision_ID=0x01, all the other keep default setting.Arrange interface at base address register, BAR0 is set to storage space, capacity 128KB, BAR1 are set to IO space, and capacity 16B, BAR2 ~ BAR5 do not use, and all the other keep default setting, complete the configuration of IP kernel.

As shown in Figure 3, rear end of the present invention match circuit is according to control command interpretation mode of operation, by realizing in the mode of finite state machine the interpretation of order, 6 kinds of mode of operations supported altogether by this rear end match circuit, be respectively monocycle memory read mode, monocycle memory WriteMode, IO read mode, IO WriteMode, burst memory read mode and burst memory WriteMode, its read-write sequence flow process is: the initial condition of the finite state machine of rear end match circuit is idle condition idle, detect that local side signal lt_framen is dragged down at the 5th rising edge clock of pci_clk, finite state machine starts action, jump to decoded state decode, according to the decode results to local side control signal, finite state machine carries out the selection of mode of operation, when for reading transaction, finite state machine is according to result, directly jump to three kinds of read states at the 6th rising edge clock, be respectively memory monocycle read states single_rd, memory burst read states burst_rd, IO read states io_rd, when for write operation, to jump at the 6th rising edge clock and write wait state wait_1clk, postpone a pci_clk clock cycle, at the 7th rising edge clock again according to decode results, jump to corresponding three kinds and write state, be respectively that the memory monocycle writes state single_wr, memory burst writes state burst_wr, IO writes state io_wr, after memory burst writes state, last address write operation state last_wr to be jumped to according to timing requirements, after completing read-write operation, two wait states to be jumped to: local wait state 1 local_wait1 and local wait state 2 local_wait2 detects concerned control command in these two states according to timing requirements, when meeting the requirements, get back to idle condition idle, complete and this time once read and write transaction.

As shown in Figure 4, peripheral circuit control module of the present invention comprises LCDs control submodule, toggle switch controls submodule, LED light controls submodule and temperature sensor controls submodule; LCDs control module, toggle switch control submodule, LED light controls submodule and is connected with the rear end match circuit in PCI top-level module respectively with temperature sensor control submodule, and the pci clock signal in pci bus signal and reset signal access LCDs control submodule respectively, toggle switch controls submodule, LED light controls submodule and temperature sensor controls submodule.

The reset of each submodule and clock signal all adopt clock and the reset signal of pci bus, each submodule address is controlled by the l_adro of PCI local side bus, according to the related command of pci bus, rear end match circuit enters IO read-write state, read-write sequence provides in the match circuit of rear end, each submodule that peripheral circuit controls is under read-write sequence controls, by the address of l_daro, receive the data from rear end match circuit and order, be translated into the control signal of relevant sub-module, and the data that oneself state or needs collect are turned back to rear end match circuit, finally upper computer software is turned back to by relevant treatment by back-end circuit.

As shown in Figure 5, memory circuitry control module of the present invention extends out SRAM on Control card, and model is IS61LV25616.Its operation principle and peripheral circuit control module similar, it resets and clock signal is also provided by pci bus, to keep synchronous, according to the related command of pci bus, rear end match circuit enters memory read/write state, the order that rear end match circuit transmits is converted into the various enable signals of the peripheral memory on Control card by memory control module, the peripheral memory work on Control card; According to the sequential in the match circuit of rear end, on board, SRAM write enters data or read number from SRAM board.The read-write sequence of SRAM meets the timing requirements in chip datasheet, realizes with finite state machine.

Claims

1. the transmission circuit based on the configurable pci bus of FPGA technology, it is characterized in that: this transmission circuit comprises FPGA device, FPGA device inside comprises PCI top-level module, PCI top-level module comprises the ALTERA PCI IP kernel of instantiation, rear end match circuit, peripheral circuit control module and memory circuitry control module, and the ALTERA PCI IP kernel of wherein instantiation is connected with rear end match circuit; Rear end match circuit is connected with peripheral circuit control module and memory circuitry control module respectively; The ALTERA PCI IP kernel of instantiation is connected with golden finger by pci bus; Peripheral circuit control module is connected with the peripheral circuit on board; Memory circuitry control module is connected with the peripheral memory on board; Whole module is as a whole by the encapsulation of PCI top-level module.

2. the transmission circuit of a kind of configurable pci bus based on FPGA technology according to claim 1, it is characterized in that: described rear end match circuit is according to control command interpretation mode of operation, by realizing in the mode of finite state machine the interpretation of order, its read-write sequence flow process is: the initial condition of the finite state machine of rear end match circuit is idle condition idle, detect that local side signal lt_framen is dragged down at the 5th rising edge clock of pci_clk, finite state machine starts action, jumps to decoded state decode; According to the decode results to local side control signal, finite state machine carries out the selection of mode of operation, when for reading transaction, finite state machine is according to result, directly jump to three kinds of read states at the 6th rising edge clock, be respectively memory monocycle read states single_rd, memory burst read states burst_rd, IO read states io_rd; When for write operation, to jump at the 6th rising edge clock and write wait state wait_1clock, postpone a pci_clk clock cycle, at the 7th rising edge clock again according to decode results, jump to corresponding three kinds and write state, be respectively that the memory monocycle writes state single_wr, memory burst writes state burst_wr, IO writes state io_wr; After memory burst writes state, last address write operation state last_wr to be jumped to according to timing requirements, after completing read-write operation, two wait states to be jumped to: local wait state 1 local_wait1 and local wait state 2 local_wait2 detects concerned control command in these two states according to timing requirements, when meeting the requirements, get back to idle condition idle, complete and this time once read and write transaction.

3. the transmission circuit of a kind of configurable pci bus based on FPGA technology according to claim 1, is characterized in that: described peripheral circuit control module comprises LCDs and controls submodule, toggle switch control submodule, LED light control submodule and temperature sensor control submodule; LCDs control module, toggle switch control submodule, LED light controls submodule and is connected with the rear end match circuit in PCI top-level module respectively with temperature sensor control submodule, and the pci clock signal in pci bus signal and reset signal access LCDs control submodule respectively, toggle switch controls submodule, LED light controls submodule and temperature sensor controls submodule.