CN104573228A

CN104573228A - Microprocessor silicone-fed verification device and method for compatibility design

Info

Publication number: CN104573228A
Application number: CN201510004794.3A
Authority: CN
Inventors: 郭阳; 刘畅; 扈啸; 陈书明; 陈跃跃; 孙永节; 鲁建壮; 刘宗林
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2015-01-06
Filing date: 2015-01-06
Publication date: 2015-04-29
Anticipated expiration: 2035-01-06
Also published as: CN104573228B

Abstract

The invention discloses microprocessor silicone-fed verification device and method for compatibility design, and aims at solving the problems of slow test excitation generation, low verification result examination and complex control in the existing microprocessor silicone-fed function compatibility verification technology. The device is of a main-secondary double-chip structure, comprising a debugging host, a development board, a main control chip and a secondary control chip; a main control program and a secondary control program are set in the debugging host; the main control chip and the secondary control chip respectively load and operate the main control program and the secondary control program to generate and operate test excitation, then the operation results of the main control chip and the secondary control chip to the test excitation programs are compared through the main control program, and finally the verification result is displayed through the debugging host. With the adoption of the device, the verification process is free of artificial interference; a hardware platform is simple to control; the silicone-fed verification accuracy and verification efficiency can be effectively increased.

Description

Demo plant and verification method after the microprocessor silicon of compatible design

Technical field

The present invention relates to functional verification field after microprocessor silicon, the apparatus and method of particularly functional verification after a kind of compatible chip instruction set computer silicon.

Background technology

Military microprocessor (comprising CPU and DSP) is widely used in the fields such as guided missile, satellite, aircraft, naval vessels, radar, tank and military secret communication.Due to a large amount of import foreign chip, face the hidden danger of embargo and threat out of stock, safety and reliability, the compatible military microprocessor of independent development, to realize production domesticization alternative significant.

The compatibility of indication of the present invention, mainly refers to independent development microprocessor, realizes using the pluggable replacement of external microprocessor, requires in many aspects such as profile and encapsulation, function, performance, electric parameters consistent with external product.For convenience of description, the external microprocessor intending development is called objective chip by the present invention, and the microprocessor of the compatibility of our independent development is called compatible chip.

In armament systems, the production domesticization of microprocessor is replaced and is required with the instruction of external mainstream microprocessor, encapsulation, interface sequence completely compatible, and compatible checking faces huge challenge.The present invention is mainly for the checking of function compatibility, and its implication refers to that compatible chip is compared objective chip and had following characteristics: the visible hardware resource of programmer is consistent with objective chip; Correctly, cpu instruction complete or collected works are as one man realized; The result that code performs and Observable state consistency; External components function is consistent with using method; Hardware configuration method and start-up mode arrange consistent.

Two stages of checking (namely verifying after silicon) after the checking of function compatibility can be included in the checking before throwing sheet and throw sheet.The means that before tradition throws sheet, checking uses have two, and one is the simplation verification based on software, and two is the simulation hardwares based on emulator.Simplation verification flexibility ratio is high, observability is strong, with low cost, but speed is slow, proving period is long, is suitable for verifying functional part.Register stage design code downloads in hardware emulator by simulation hardware, adopt hardware to perform test and excitation, its speed is fast, observability strong, but with high costs, build hardware simulation platform for complicated multi core chip and need multiple emulator collaborative work, difficult in maintenance.No matter software simulation or simulation hardware, test and excitation is all the bottleneck of checking, and for simplation verification, a large amount of test and excitations will increase the proving period time, in order to control time minimizing test and excitation then means the reduction of function coverage; For simulation hardware, tradition produces the mode of excitation, and its speed can not meet the needs of emulator speed far away, and this is great waste for acceleration platform.

After silicon, verifying speed is fast, and the functional verification that can carry out in all directions to chip within a short period of time, ensures higher coverage rate.After traditional silicon the checking of function compatibility usually adopt manpower comparing compared with method, the result that Qualify Phase runs compatible chip after silicon and objective chip operation result carry out manpower comparing comparatively, its difficult point is the situation being difficult to exhaustive various boundary treatment, be difficult to ensure checking coverage rate, verification efficiency is very low, and proving period is very long.And, the same with simulation hardware, verify the bottleneck being faced with test and excitation formation speed equally after silicon, desirable test and excitation generation method should speed fast, coverage rate is high, redundance is low.After major part silicon, checking needs hardware accelerator to provide a large amount of test and excitation to input, the hardware accelerator that different test templates is corresponding different, and for ensureing excitation generation speed, hardware accelerator can not be too complicated.The shortcoming of this method is that the bandwidth between hardware accelerator and processor chips can become system bottleneck, on the other hand, when test template is more, needs a large amount of hardware accelerator, and the control of intermodule and scheduling become complicated.Also having certain methods to imply the execution result of processor when generating test and excitation, this simplify the work of result comparison, but it is higher to generate protocols call to test and excitation, and range of application is wideless.Whether more conventional method designs arithmetic logic separately, the excitation being loaded into processor is also loaded on arithmetic logic, and the result that the result of generation and processor produce made comparisons, perform correct with this decision processor.The problem of this method is that arithmetic logic as a reference may be very complicated, or time overhead is very large, affects verifying speed.

Summary of the invention

The technical problem to be solved in the present invention is: for realizing, the test and excitation formation speed that the compatible verification technique of function after microprocessor silicon exists is slow, the result checking efficiency is low and control the problems such as complicated, propose a kind of accurately, the apparatus and method of efficient verification microprocessor function compatibility, when solving compatible chip checking, test and excitation generates slowly, the low and hardware platform of the result checking efficiency controls the problems such as complicated, improve verification quality, shorten proving period.

Concrete technical scheme is:

The present invention is " MS master-slave " double-chip structure towards demo plant after the microprocessor silicon of compatible design, by debug host, development board, main control chip with form from control chip.

Debug host runs development environment and controls main control chip and the computing machine from the behavior of control chip, is connected with from controlling chip with main control chip.Debug host and main control chip are connected by the first joint test working group (JiontTestActionGroup, JTAG) JTAG1, and debug host is connected by the second joint test working group JTAG2 with from control chip.Debug host is provided with business software--code debugging device (CodeComposerStudio, CCS) Integrated Development Environment.Debug host has the two cover softwares utilizing CCS Integrated Development Environment to develop: primary control program and from control program, primary control program be responsible for generating main control chip test and excitation, control main control chip perform test and excitation, comparison main control chip with from the software controlled chip and perform test and excitation result and process from controlling chip execution result mistake; Be responsible for generating from control chip testing excitation, control to perform the software of test and excitation from control chip from control program.

Development board is the general development board being equipped with multiple interfaces and bus, and can dispose multiple processor chips, chip chamber is connected by data bus, and each chip has the stand-alone interface communicated with debug host.Main control chip, from control chip be inserted into development board.

Main control chip is objective chip, and main control chip is connected with HPI bus and host interface (HostPortInterface) bus with debug host.Main control chip is connected with debug host by JTAG1, is communicated with other resource on development board by HPI bus.Main control chip is downloaded from debug host and is run primary control program.

Primary control program flow process is:

The first step, the responsive point set in definition proof procedure, responsive point set is made up of sensitive spot, and sensitive spot is affect larger particular values to operation result precision and accuracy in floating-point operation, comprises positive negative zero, positive minus infinity and invalid number; Sensitive spot is made to concentrate sensitive spot number to be KpNum (KpNum is positive integer); The storage space that to define with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 and ADDR12 respectively in main control chip address space be start address, for depositing data and the code of primary control program interim generation in follow-up implementation, because primary control program generates multistage first test and excitation program in test process, main control chip will take a slice storage space, definition RADDR2 equals ADDR2, and the value of RADDR2 is the start address that described multistage first test and excitation program stores in main control chip;

Second step, defined instruction model and test and excitation template; Treat brake instruction by Object--oriented method and carry out abstract modeling, defined instruction model, process is as follows: instruction is divided into some fields by the effect according to different instruction position, instruction inside, as opcode field, operand field, conditional execute bit field, parallel bit field etc., each field is the stochastic variable of a Prescribed Properties, and constraint condition defines the ratio of the type of stochastic variable field, span and stochastic distribution; Different demand models is set up in instruction for different types of structure, comprise double operand instruction, single-operand instruction and no operand instruction, the number of instruction operands is made to be that (OpNum of double operand instruction equals 2 to OpNum, the OpNum of single-operand instruction equals 1, the OpNum of no operand instruction equals 0), make demand model number be InsNum (the value and instruction collection of InsNum is relevant); On the basis of demand model, for test and excitation template is set up in the instruction of computing class and the instruction of control class respectively; Computing class instruction testing excitation template comprise three parts: concurrently OpNum operand is moved in OpNum register, execution instruction, result is write back to storage space; Control class instruction testing excitation template and comprise three parts: status register value after storage current status register value, execution instruction, storage perform; Need the status register preserved according to the type selecting of execution control class instruction, control class command function and comprise: reprogramming execution sequence, change pipeline state, change perform authority and change buffer status;

3rd step, definition primary control program loop variable LoopNum1=0, LoopNum1 controls the circulation pass of primary control program stochastic generation test data in proof procedure, (MAXLOOP1 is positive integer to the predetermined cycle index MAXLOOP1 of define program, MAXLOOP1 gets the empirical value that checking can be made to reach target coverage rate, usual coverage rate target is set to 1% of computational space), definition temporary variable j=0, definition primary control program synchronous mark position MFlag, represents when MFlag is 1 that main control chip has been in wait-receiving mode sends the second test and excitation program state from control chip;

4th step, reset primary control program synchronous mark position, namely MFlag sets to 0;

5th step, generate the first test data, form the first test data set DataSet1, method is: each sensitive spot that primary control program is concentrated sensitive spot, utilize normal distribution random number generating function generate KN (KN is positive integer, and KN gets 100 ~ 1000 usually) individual centered by sensitive spot, fixed value (fixed value can get the arbitrary value in sensitive spot floating point representation in mantissa's variation range) is variance, meets the first test data of normal distribution; Normal distribution random number generating function comprises two steps: the first step utilizes random number generator generation in C language built-in function to meet equally distributed random number; Does second step use classical BoxMuller algorithm (see baike.baidu.com/view/1710258.htm? fr=aladdin) these equally distributed random numbers are converted to the random number meeting normal distribution; KpNum*KN the first test data that sensitive spot concentrates KpNum sensitive spot to generate forms the first test data set DataSet1, and it take ADDR1 as the storage space of start address that DataSet1 leaves in main control chip; DataSet1 generative process is as follows:

5.1 defining variable i=0;

I-th sensitive spot that the 5.2 pairs of sensitive spots are concentrated, generate KN centered by sensitive spot, fixed value is variance, meets the test data of normal distribution, add in DataSet1 by the test data of generation, i increases 1;

If 5.3 i<KpNum, turn 5.2; If i >=KpNum, perform the 6th step;

6th step, according to demand model stochastic generation IN (IN is positive integer, IN>KpNum*KN/2) the bar instruction to be tested of second step definition; For the instruction to be tested of every bar, according to the test and excitation template stochastic generation first test and excitation program of second step definition; Be that the instruction to be tested of IN bar generates IN section first test and excitation program serially, the process generating the first test and excitation program for the instruction to be tested of every bar is identical, includes following steps:

If 6.1 instructions to be tested are the instruction of computing class, a first Stochastic choice OpNum operand from DataSet1; Then generate before instruction to be tested and move instruction, move instruction and act as operand is moved in the register of correspondence; After instruction to be tested, generate first store instruction, the first storage instruction act as is stored into operation result the storage space that main control chip address is ADDR4; Finally the first test and excitation program is stored into the storage space that main control chip address is ADDR2; Turn 6.3;

If 6.2 instructions to be tested are for controlling class instruction, before instruction to be tested, first generate second store instruction, the second storage instruction act as is stored into current status register value the storage space that main control chip address is ADDR4; Then after instruction to be tested, generate the 3rd store instruction, the 3rd storage instruction act as is stored into status register value after execution the storage space that main control chip address is ADDR4; Finally the first test and excitation program is stored into the storage space that main control chip address is ADDR2; Turn 6.3;

6.3ADDR2 increase an address bit (address bit=machine work is wide/8, address bit is wide relevant to machine work, an address bit as 32 machines is 4, an address bit of 64 machines is 8), ADDR4 increases an address bit, j increases 1, if j<InsNum, represent that described instruction to be tested still has demand model not generate the first test and excitation program, turn the 6th step, if j >=InsNum, represent primary control program for all demand models of this instruction to be tested generate the first test and excitation program, if be that the instruction to be tested of IN bar generates IN section first test and excitation program, turn the 7th step, otherwise, turn the 6th step, for next instruction to be tested generates the first test and excitation program,

7th step, detect from control Program Synchronization zone bit SFlag, if SFlag=1, represent from control program and be in waiting status, it is the storage space of ADDR8 that IN the first test and excitation program the 6th step generated all is sent to from control chip address, turns the 8th step; If SFlag=0, represent from control program and be in busy condition, turn the 7th step;

8th step, MFlag is set to 1, represents that main control chip enters waiting status;

9th step, receiving IN the second test and excitation program sent from control program, is the storage space of ADDR3 stored in main control chip address;

Tenth step, primary control program is according to the value of RADDR2 heavy duty address AD DR2 and jump to address AD DR2, order performs IN the first test and excitation program that primary control program generates, then address AD DR3 is jumped to, order performs IN the second test and excitation program from control Program Generating, first test and excitation program execution result is recorded in the storage space that start address is ADDR4, and the second test and excitation program execution result is recorded in the storage space that start address is ADDR5;

11 step, primary control program detects from control program execution result Returning mark position ResultFlag, if ResultFlag=1, represent from control program and IN the first test and excitation program performed from control chip and IN the second test and excitation program execution result are returned to main control chip, turn the 12 step; If ResultFlag=0, represent from control program and also IN the first test and excitation program performed from control chip and IN the second test and excitation program execution result are not returned to main control chip, turn the 11 step;

12 step, contrast main control chip and perform the result of IN the first test and excitation program and IN the second test and excitation program from control chip respectively, as execution result is different, turns the 13 step; Otherwise, LoopNum1 increases 1, if LoopNum1<MAXLOOP1, represent that primary control program not yet reaches the predetermined cycle index of program, turn the 4th step, if LoopNum1 >=MAXLOOP1, represent that primary control program has reached the predetermined cycle index of program, return settling signal to debug host, turn the 14 step;

13 step, records the first test and excitation program or the second test and excitation program and main control chip that make a mistake and the result performing the first test and excitation program or the second test and excitation program from control chip, and record content is passed to debug host by JTAG1;

14 step, primary control program terminates.

From control chip be compatible chip to be verified, from control chip be connected with HPI bus with debug host.Be connected with debug host by JTAG2 from control chip, communicated with other resource on development board by HPI bus.Download from control chip from debug host and run from control program.

From control program circuit be:

1. identical with the first step of primary control program, define responsive point set; At the storage space that to define with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 be respectively start address from control chip address space, for depositing the data and code that produce follow-up implementation from control program temporarily, because generate multistage second test and excitation program from control program test process, a slice storage space will taken from control chip, definition RADDR7 equals ADDR7, the value of RADDR7 be described multistage second test and excitation program in the start address stored from control chip, for carrying out heavy duty to address ADDR7;

2. identical with the second step of primary control program, defined instruction model and test and excitation template;

3. define program loop variable LoopNum2=0, LoopNum2 controls the circulation pass from control program stochastic generation test data in proof procedure, defines the predetermined cycle index MAXLOOP2 (namely MAXLOOP2 equal MAXLOOP1) identical with primary control program; Definition temporary variable k=0; Define from control Program Synchronization zone bit SFlag, represent when SFlag is 1 from control chip and be in the state that wait-receiving mode main control chip sends the first test and excitation program; Define and to represent when Returning mark position ResultFlag, ResultFlag are 1 from control program from control program execution result and the first test and excitation program and the second test and excitation program execution result are write back to main control chip storage space;

4. reset from control Program Synchronization zone bit, namely SFlag sets to 0, and ResultFlag sets to 0;

5. identical with the 5th step of primary control program, generate the second test data, form the second test data set DataSet2, it take ADDR6 as the storage space of start address that DataSet2 leaves in from control chip;

6. according to instruction template stochastic generation IN (IN is positive integer, IN>KpNum*KN/2) the bar instruction to be tested that step 2 defines, for the instruction to be tested of every bar, according to test and excitation template stochastic generation second test and excitation program; Be that the instruction to be tested of IN bar generates IN section second test and excitation program serially, the process generating the second test and excitation program for the instruction to be tested of every bar is identical, includes following steps:

If the 6.1 ' instruction to be tested is the instruction of computing class, a first Stochastic choice OpNum operand from DataSet2; Then generate before instruction and move instruction, move instruction and act as operand is moved in the register of correspondence, after instruction, generate the 4th store instruction, the 4th store instruction act as operation result is stored into from control chip address be the storage space of ADDR10; Finally the second test and excitation program being stored into from controlling chip address is the storage space of ADDR7; Turn 6.3 ';

If the 6.2 ' instruction to be tested is for controlling class instruction, before instruction, first generates the 5th store instruction, the 5th store instruction act as current status register value is stored into from control chip address be the storage space of ADDR10; Then after instruction, generation the 6th stores instruction, and it is the storage space of ADDR10 that the 6th storage instruction act as after execution, status register value is stored into from controlling chip address; Finally the second test and excitation program being stored into from controlling chip address is the storage space of ADDR7; Turn 6.3 ';

6.3 ' ADDR7 increases an address bit, and ADDR10 increases an address bit, and k increases 1, if k<InsNum, represents that described instruction to be tested still has demand model not generate the second test and excitation program, goes to step 6; If k >=InsNum, represent from control program for all demand models of this instruction to be tested generate the second test and excitation program, if be that the instruction to be tested of IN bar generates IN section second test and excitation program, go to step 7; Otherwise, go to step 6, for next instruction to be tested generates the second test and excitation program;

7. put 1 from control Program Synchronization zone bit SFlag, represent from control chip and be in the state that wait-receiving mode main control chip sends the first test and excitation program;

8. receive IN the first test and excitation program that primary control program sends, stored in being the storage space of ADDR8 from control chip start address;

9. detect primary control program synchronous mark position MFlag, if MFlag=1, namely primary control program is in waiting status, IN the second test and excitation program from control Program Generating is sent to the storage space that main control chip start address is ADDR3, goes to step 10; Otherwise, go to step 9;

10. from control program according to RADDR7 heavy duty address AD DR7 initial value and jump to address AD DR7, order performs IN the second test and excitation program from control Program Generating, then address AD DR8 is jumped to, order performs IN the first test and excitation program that primary control program generates, and the first test and excitation execution result and the second test and excitation program execution result are recorded in the storage space that start address is ADDR9 and ADDR10 respectively;

First test and excitation execution result is sent to the storage space that main control chip address is ADDR11 by 11., second test and excitation program execution result is sent to the storage space that main control chip address is ADDR12, and will put 1 from control program execution result Returning mark position ResultFlag;

12.LoopNum2 increases 1, if LoopNum2<MAXLOOP2, represents from control program and not yet reaches the predetermined cycle index of program, go to step 4; If LoopNum2 >=MAXLOOP2, represent from control program and reached the predetermined cycle index of program, from control EOP (end of program).

The method adopting the present invention to carry out functional verification towards the compatible chip that demo plant after the microprocessor silicon of compatible design treats checking is:

Step one, debug host by CCS Integrated Development Environment by compiled primary control program and from control program respectively by JTAG1 and JTAG2 download to main control chip and from control chip.And start and respectively perform primary control program and from control program;

Step 2, main control chip runs primary control program, run from control program from control chip simultaneously, primary control program is responsible for generating main control chip test and excitation, is controlled main control chip execution test and excitation, comparison main control chip and perform test and excitation result from controlling chip and process from controlling chip execution result mistake, is responsible for generating from control chip testing excitation from control program, controls to perform test and excitation from controlling chip:

2.1) primary control program and simultaneously define respective responsive point set respectively from control program, definition sensitive spot concentrates sensitive spot number to be KpNum; The storage space that to define with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 and ADDR12 respectively in main control chip address space be start address, for depositing data and the code of primary control program interim generation in follow-up implementation, definition RADDR2 equals ADDR2, for carrying out heavy duty to address ADDR2; At the storage space that to define with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 be respectively start address from control chip address space, for depositing the data and code that produce follow-up implementation from control program temporarily, definition RADDR7 equals ADDR7, for carrying out heavy duty to address ADDR7;

2.2) primary control program and simultaneously define respective demand model and test and excitation template respectively from control program; Primary control program is identical with from the process of control application definition demand model, treat brake instruction by Object--oriented method and carry out abstract modeling, defined instruction model, process is as follows: instruction is divided into some fields by the effect according to different instruction position, instruction inside, as opcode field, operand field, conditional execute bit field, parallel bit field etc., each field is the stochastic variable of a Prescribed Properties, and constraint condition defines the ratio of the type of stochastic variable field, span and stochastic distribution; Different demand models is set up in instruction for different types of structure, comprise double operand instruction, single-operand instruction and no operand instruction, the number of instruction operands is made to be that (OpNum of double operand instruction equals 2 to OpNum, the OpNum of single-operand instruction equals 1, the OpNum of no operand instruction equals 0), demand model number is made to be InsNum (InsNum is positive integer, and its value and instruction collection is relevant); Primary control program and from control program simultaneously respectively on the basis of demand model, for the instruction of computing class with control class instruction and set up test and excitation template respectively, primary control program is identical with from the test and excitation template of control program; Computing class instruction testing excitation template comprise three parts: beamhouse operation number: concurrently OpNum operand is moved in OpNum register, execution instruction, result is write back to storage space; Control class instruction testing excitation template and comprise three parts, status register value after storage current status register value, execution instruction, storage perform; Need the status register preserved according to the type selecting of execution control class instruction, control class command function and comprise: reprogramming execution sequence, change pipeline state, change perform authority and change buffer status;

2.3) primary control program define program loop variable LoopNum1=0, LoopNum1 controls the circulation pass of primary control program stochastic generation test data in proof procedure, the predetermined cycle index MAXLOOP1 of definition primary control program, primary control program definition temporary variable j=0, definition primary control program synchronous mark position MFlag; Simultaneously from control application definition program loop variables L oopNum2=0, LoopNum2 controls the circulation pass from control program stochastic generation test data in proof procedure, define from the control predetermined cycle index MAXLOOP2 of program (MAXLOOP2=MAXLOOP1), from control application definition temporary variable k=0, define from control Program Synchronization zone bit SFlag, from control application definition execution result Returning mark position ResultFlag;

2.4) primary control program reset primary control program synchronous mark position, namely MFlag sets to 0; From control Program reset from control Program Synchronization zone bit, namely SFlag sets to 0, and ResultFlag sets to 0;

2.5) primary control program and simultaneously generate the first test data and the second test data from control program, form test and excitation sensitivity volume, method is as follows: primary control program is identical with from the process of control Program Generating test data, utilize normal distribution random number generating function generate KN ((KN is positive integer, and KN gets 100 ~ 1000 usually) individual centered by sensitive spot, fixed value (fixed value can get the arbitrary value in sensitive spot floating point representation in mantissa's variation range) is variance, the test data meeting normal distribution; Normal distribution random number generating function comprises two steps: the first step utilizes random number generator generation in C language built-in function to meet equally distributed random number; Second step uses BoxMuller method, and these equally distributed random numbers are converted to the random number meeting normal distribution; KpNum*KN the first test data that primary control program sensitive spot concentrates KpNum sensitive spot to generate; From KpNum*KN the second test data that control program sensitive spot concentrates KpNum sensitive spot to generate; The first test data that primary control program generates forms the first test data set DataSet1, it take ADDR1 as the storage space of start address that DataSet1 leaves in main control chip, form the second test data set DataSet2 from the second test data of control Program Generating, it take ADDR6 as the storage space of start address that DataSet2 leaves in from control chip;

2.6) primary control program and from control program simultaneously respectively according to 2.2) demand model that defines generates the instruction to be tested of IN bar; Primary control program turns 2.6.1), generate IN the first test and excitation program; Meanwhile, turn 2.6.1 ' from control program), generate IN the second test and excitation program;

2.6.1) primary control program is that the instruction to be tested of IN bar generates IN the first test and excitation program serially, and the process generating the first test and excitation program for the instruction to be measured of every bar is all identical, includes following steps:

2.6.1.1) if instruction to be tested is the instruction of computing class, a first Stochastic choice OpNum operand from test data set DataSet1; Then generate before instruction to be tested and move instruction, move instruction and act as operand is moved in the register of correspondence; After instruction to be tested, generate first store instruction, the first storage instruction act as is stored into operation result the storage space that main control chip address is ADDR4; Finally the first test and excitation program is stored into the storage space that main control chip address is ADDR2, turns 2.6.1.3);

2.6.1.2) if instruction to be tested is for controlling class instruction, before instruction to be tested, first generating second store instruction, the second storage instruction act as is stored into current status register value the storage space that main control chip address is ADDR4; Then after instruction to be tested, generate the 3rd store instruction, the 3rd storage instruction act as is stored into status register value after execution the storage space that main control chip address is ADDR4; Finally the first test and excitation program is stored into the storage space that main control chip address is ADDR2, turns 2.6.1.3);

2.6.1.3) ADDR2 increases an address bit, ADDR4 increases an address bit, j increases 1, if j<InsNum, represent that described instruction to be tested still has demand model not generate the first test and excitation program, primary control program turns 2.6.1), if j >=InsNum, represent primary control program for all demand models of this instruction to be tested generate the first test and excitation program, if be that the instruction to be tested of IN bar generates IN section first test and excitation program, turn 2.7), otherwise, primary control program turns 2.6.1), primary control program generates the first test and excitation program for next instruction to be tested,

2.6.2) be that the instruction to be tested of IN bar generates the individual second test and excitation program of IN serially from control program, the process generating the second test and excitation program for the instruction to be measured of every bar is all identical, includes following steps:

2.6.2.1) if instruction to be tested is the instruction of computing class, a first Stochastic choice OpNum operand from DataSet2; Then generate before instruction to be tested and move instruction, move instruction and act as operand is moved in the register of correspondence; After instruction to be tested, generate the 4th store instruction, the 4th store instruction act as operation result is stored into from control chip address be the storage space of ADDR10; Finally the second test and excitation program being stored into from control chip address is the storage space of ADDR7, turns 2.6.2.3);

2.6.2.2) if instruction to be tested is for controlling class instruction, before instruction to be tested, first generating the 5th store instruction, the 5th store instruction act as current status register value is stored into from control chip address be the storage space of ADDR10; Then after instruction to be tested, generation the 6th stores instruction, and it is the storage space of ADDR10 that the 6th storage instruction act as after execution, status register value is stored into from controlling chip address; Finally the second test and excitation program being stored into from control chip address is the storage space of ADDR7, turns 2.6.2.3);

2.6.2.3) ADDR7 increases an address bit, ADDR10 increases an address bit, k increases 1, if k<InsNum, represent that described instruction to be tested still has demand model not generate the second test and excitation program, turn 2.6.2 from control program), if k >=InsNum, represent from control program for all demand models of this instruction to be tested generate the second test and excitation program, if be that the instruction to be tested of IN bar generates IN section second test and excitation program, turn 2.7); Otherwise, turn 2.6.2 from control program), for next instruction to be tested generates the second test and excitation program;

2.7) from control program, synchronous mark position SFlag is put 1, represent from control chip and be in the state that wait-receiving mode main control chip sends IN the first test and excitation program, turn 2.8); Simultaneously, primary control program detects from control Program Synchronization zone bit SFlag, if SFlag=1, represents from control program and is in waiting status, it is the storage space of ADDR8 that the IN of generation the first test and excitation program is all sent to from control chip address by primary control program, and primary control program turns 2.8); Otherwise primary control program turns 2.7);

2.8) MFlag is put 1 by primary control program, and represent that main control chip enters waiting status, primary control program turns 2.9); Simultaneously from control Programmable detection primary control program synchronous mark position MFlag, if MFlag=1, namely primary control program is in waiting status, turns 2.9 from control program); Otherwise, turn 2.8 from control program);

2.9) from control program, the IN of generation the second test and excitation program is sent to the storage space that main control chip start address is ADDR3, primary control program receives IN the second test and excitation program sent from control program simultaneously;

2.10) primary control program according to RADDR2 heavy duty address AD DR2 initial value and jump to address AD DR2, order performs IN the first test and excitation program that primary control program generates, then address AD DR3 is jumped to, order performs IN the second test and excitation program from control Program Generating, first test and excitation program execution result is recorded in the storage space that start address is ADDR4, and the second test and excitation program execution result is recorded in the storage space that start address is ADDR5; Simultaneously jump to address AD DR7 from control program according to the initial value of RADDR7 heavy duty address AD DR7, order performs IN the second test and excitation program from control Program Generating, then address AD DR8 is jumped to, order performs IN the first test and excitation program that primary control program generates, and the first test and excitation execution result and the second test and excitation program execution result are recorded in the storage space that start address is ADDR9 and ADDR10 respectively;

2.11) from control program, the first test and excitation execution result is sent to the storage space that main control chip address is ADDR11, second test and excitation program execution result is sent to the storage space that main control chip address is ADDR12, and 1 will be put from control program execution result Returning mark position ResultFlag, turn 2.12 from control program); Primary control program detects from control program execution result Returning mark position ResultFlag simultaneously, if ResultFlag=1, represent from control program and will return to main control chip from control chip execution IN the first test and excitation program and IN the second test and excitation program execution result, primary control program turns 2.12); If ResultFlag=0, represent from control program and also will not return to main control chip from control chip execution IN the first test and excitation program and IN the second test and excitation program execution result, primary control program turns 2.11);

2.12) primary control program contrast main control chip and perform the result of IN the first test and excitation program and IN the second test and excitation program from control chip respectively, as execution result is different, turns 2.13); Otherwise LoopNum1 increases 1, LoopNum2 and increases 1, and primary control program turns 2.12.1), turn 2.12.2 from control program) simultaneously;

2.12.1) primary control program compares the size of LoopNum1 and MAXLOOP1, if LoopNum1<MAXLOOP1, represent that primary control program not yet reaches the predetermined cycle index of program, primary control program turns 2.4); If LoopNum1 >=MAXLOOP1, represent that primary control program has reached the predetermined cycle index of program, return settling signal to debug host, primary control program turns 2.14);

2.12.2) compare the size of LoopNum2 and MAXLOOP2 from control program, if LoopNum2<MAXLOOP2, represent from control program and not yet reach the predetermined cycle index of program, turn 2.4 from control program); If LoopNum2 >=MAXLOOP2, represent from control program and reached the predetermined cycle index of program, terminate from control program;

2.13) the first test and excitation program of making a mistake of primary control program record or the second test and excitation program and main control chip and perform the result of the first test and excitation program or the second test and excitation program from control chip, and record content is passed to debug host by JTAG1;

2.14) terminate primary control program, go to step three;

Step 3, if debug host receives the settling signal that main control chip is passed back by JTAG1, proof procedure terminates; If debug host receives main control chip and passes the first test and excitation program or the second test and excitation program and main control chip that make a mistake and the result performing the first test and excitation program or the second test and excitation program from control chip back by JTAG1, debug host shows the first test and excitation program or the second test and excitation program and main control chip that make a mistake and the result performing the first test and excitation program or the second test and excitation program from control chip, and proof procedure terminates.

Compared with the compatible demo plant of function after existing microprocessor silicon, the present invention has the following advantages:

1. run CCS Integrated Development Environment by debug host, exploitation primary control program and overlap software from control program two, controls main control chip and from the behavior of control chip, and shows the result in debug host, without the need to artificial interference proof procedure, hardware platform controls simple;

2. primary control program and simultaneously generate IN the first test and excitation program and IN the second test and excitation program from control program, then IN the first test and excitation program is sent to from control chip by primary control program, is sent to main control chip from control program by IN the second test and excitation program; Such primary control program and only need each self-generating IN the first test and excitation test procedure or the second test and excitation program from control program, but can carry out testing authentication to IN the first test and excitation program and IN the second test and excitation program, the verification efficiency of demo plant is high simultaneously;

3. by " MS master-slave " dual chip demo plant, main control chip and from control chip respectively by operation primary control program and from control program, at main control chip with from oneself generation control chip, testing results excitation, and be responsible for comparing by main control chip with from the operation result of control chip to test and excitation program by primary control program, without the need to being loaded into test and excitation program by debug host, decrease debug host and main control chip and from the data transmission delay controlled between chip, avoid manual compiling test and excitation program to make mistakes, accuracy and the verification efficiency of demo plant are high;

4. by primary control program with define from control program in proof procedure floating-point operation result precision and the larger responsive point set of accuracy impact, defined instruction model and test and excitation template, the random device of employing belt restraining generates centered by sensitive spot, fixed value is variance, meets the test data of normal distribution, and based on test data according to demand model and test and excitation template generation test and excitation program, the mistake may introduced when avoiding manual compiling test and excitation, the test and excitation coverage rate of demo plant and reliability high;

5. by primary control program with control test and excitation memory location and control program pointer redirect opportunity from control program, when can ensure chip executive routine to greatest extent, instruction and data is all in the local storage space of chip, reduce main control chip and the data transmission from control chip chamber, effective alleviation main control chip and the bottleneck problem from control chip chamber bandwidth, after silicon, the verification efficiency of demo plant is high.

Compared with function compatibility method after existing microprocessor silicon, the present invention has the following advantages:

1. run CCS Integrated Development Environment by debug host, develop primary control program and overlap software from control program two, control main control chip and from control chip behavior, checked to main control chip with from the test and excitation execution result of control chip by primary control program, and in debug host, show the result, without the need to manual compiling test and excitation program, result comparison, avoid the error that manual operation may be introduced, verification method accuracy is high;

2. primary control program and simultaneously generate IN the first test and excitation program and IN the second test and excitation program from control program, then IN the first test and excitation program is sent to from control chip by primary control program, is sent to main control chip from control program by IN the second test and excitation program; Such primary control program and only need each self-generating IN the first test and excitation test procedure or the second test and excitation program from control program, but can carry out testing authentication to IN the first test and excitation program and IN the second test and excitation program, verification method efficiency is high simultaneously;

3. by primary control program with define from control program in proof procedure floating-point operation result precision and the larger responsive point set of accuracy impact, defined instruction model and test and excitation template, the random device of employing belt restraining generates centered by sensitive spot, fixed value is variance, meets the test data of normal distribution, and based on test data according to demand model and test and excitation template generation test and excitation program, the mistake may introduced when avoiding manual compiling test and excitation, improves test and excitation coverage rate and the reliability of verification method;

4. by primary control program with control test and excitation memory location and control program pointer redirect opportunity from control program, when can ensure chip executive routine to greatest extent, instruction and data is all in the local storage space of chip, reduce main control chip and the data transmission from control chip chamber, effective alleviation main control chip and the bottleneck problem from control chip chamber bandwidth, improve the verification efficiency of verification method after silicon.

Accompanying drawing explanation

Fig. 1 is the present invention towards demo plant structural drawing after the microprocessor silicon of compatible design.

Fig. 2 is primary control program of the present invention and from control program execution flow figure.

Fig. 3 is that the present invention verifies method flow diagram after the microprocessor silicon of compatible design.

Fig. 4 is the instruction of computing class and controls class instruction testing excitation template.

Fig. 5 is main control chip and from control chip-stored spatial data flowing schematic diagram.

Embodiment

Below with reference to Figure of description and specific embodiment, the present invention is described in further details.

Fig. 1 is the present invention's " MS master-slave " dual chip demo plant structural drawing.In the present invention " MS master-slave " dual chip demo plant mainly comprise debug host, development board, main control chip and from control chip.

Debug host is with main control chip, be connected from controlling chip.Debug host is connected by JTAG1 with main control chip, is connected by JTAG2 with from control chip.Debug host is run master control/from control chip development environment, editor, compiling and be loaded into main control chip and the executable program from control chip, in main control chip and real-time reception chip returns from control chip runs data, and the executing state of control chip.

Main control chip is that main control chip is connected with HPI bus with debug host by chip or the objective chip of checking.Main control chip is connected with debug host by JTAG1, is undertaken communicating and access other resource on development board by HPI bus.Main control chip downloads primary control program from debug host, run primary control program, primary control program generates the first test and excitation program, control that main control chip performs test and excitation, comparison main control chip performs test and excitation result and carrying out result inspection with from controlling chip, processing from controlling chip execution result mistake.And check result or mistake are passed to debug host by JTAG1.Composition graphs 2, primary control program flow process is:

S101 defines the responsive point set in proof procedure, and responsive point set is made up of sensitive spot, and sensitive spot is affect larger particular values to operation result precision and accuracy in floating-point operation, comprises positive negative zero, positive minus infinity and invalid number; Sensitive spot is made to concentrate sensitive spot number to be KpNum (KpNum is positive integer); The storage space that to define with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 and ADDR12 respectively in main control chip address space be start address, for depositing data and the code of primary control program interim generation in follow-up implementation, because primary control program generates multistage first test and excitation program in test process, main control chip will take a slice storage space, definition RADDR2 equals ADDR2, and the value of RADDR2 is the start address that described multistage first test and excitation program stores in main control chip;

S102 defined instruction model and test and excitation template; Treat brake instruction by Object--oriented method and carry out abstract modeling, defined instruction model, process is as follows: instruction is divided into some fields by the effect according to different instruction position, instruction inside, as opcode field, operand field, conditional execute bit field, parallel bit field etc., each field is the stochastic variable of a Prescribed Properties, and constraint condition defines the ratio of the type of stochastic variable field, span and stochastic distribution; Different demand models is set up in instruction for different types of structure, comprise double operand instruction, single-operand instruction and no operand instruction, the number of instruction operands is made to be that (OpNum of double operand instruction equals 2 to OpNum, the OpNum of single-operand instruction equals 1, the OpNum of no operand instruction equals 0), make demand model number be InsNum (the value and instruction collection of InsNum is relevant); On the basis of demand model, for test and excitation template is set up in the instruction of computing class and the instruction of control class respectively; Computing class instruction testing excitation template comprise three parts: concurrently OpNum operand is moved in OpNum register, execution instruction, result is write back to storage space; Control class instruction testing excitation template and comprise three parts: status register value after storage current status register value, execution instruction, storage perform; Need the status register preserved according to the type selecting of execution control class instruction, control class command function and comprise: reprogramming execution sequence, change pipeline state, change perform authority and change buffer status;

S103 defines primary control program loop variable LoopNum1=0, LoopNum1 controls the circulation pass of primary control program stochastic generation test data in proof procedure, (MAXLOOP1 is positive integer to the predetermined cycle index MAXLOOP1 of define program, MAXLOOP1 gets the empirical value that checking can be made to reach target coverage rate, usual coverage rate target is set to 1% of computational space), definition temporary variable j=0, definition primary control program synchronous mark position MFlag, represents when MFlag is 1 that main control chip has been in wait-receiving mode sends the second test and excitation program state from control chip;

S104 reset primary control program synchronous mark position, namely MFlag sets to 0;

S105 generates the first test data, form the first test data set DataSet1, method is: each sensitive spot that primary control program is concentrated sensitive spot, utilize normal distribution random number generating function generate KN (KN is positive integer, and KN gets 100 ~ 1000 usually) individual centered by sensitive spot, fixed value (fixed value can get the arbitrary value in sensitive spot floating point representation in mantissa's variation range) is variance, meets the first test data of normal distribution; Normal distribution random number generating function comprises two steps: the first step utilizes random number generator generation in C language built-in function to meet equally distributed random number; Second step uses classical BoxMuller algorithm that these equally distributed random numbers are converted to the random number meeting normal distribution; KpNum*KN the first test data that sensitive spot concentrates KpNum sensitive spot to generate forms the first test data set DataSet1, and it take ADDR1 as the storage space of start address that DataSet1 leaves in main control chip;

Demand model stochastic generation IN (IN>KpNum*KN/2) the bar instruction to be tested that S106 defines according to S102; For the instruction to be tested of every bar, according to the test and excitation template stochastic generation first test and excitation program of S102 definition; Be that the instruction to be tested of IN bar generates IN section first test and excitation program serially, the process generating the first test and excitation program for the instruction to be tested of every bar is identical, includes following steps:

If S106.1 instruction to be tested is the instruction of computing class, a first Stochastic choice OpNum operand from DataSet1; Then generate before instruction to be tested and move instruction, move instruction and act as operand is moved in the register of correspondence; After instruction to be tested, generate first store instruction, the first storage instruction act as is stored into operation result the storage space that main control chip address is ADDR4; Finally the first test and excitation program is stored into the storage space that main control chip address is ADDR2; Turn S106.3;

If S106.2 instruction to be tested is for controlling class instruction, before instruction to be tested, first generates second store instruction, the second storage instruction act as is stored into current status register value the storage space that main control chip address is ADDR4; Then after instruction to be tested, generate the 3rd store instruction, the 3rd storage instruction act as is stored into status register value after execution the storage space that main control chip address is ADDR4; Finally the first test and excitation program is stored into the storage space that main control chip address is ADDR2; Turn S106.3;

S106.3ADDR2 increases an address bit, and (address bit is wide relevant to machine work, an address bit as 32 machines is 4, an address bit of 64 machines is 8), ADDR4 increases an address bit, j increases 1, if j<InsNum, represent that described instruction to be tested still has demand model not generate the first test and excitation program, turn S106, if j >=InsNum, represent primary control program for all demand models of this instruction to be tested generate the first test and excitation program, if be that the instruction to be tested of IN bar generates IN section first test and excitation program, turn S107, otherwise, turn S106, for next instruction to be tested generates the first test and excitation program,

S107 detects from control Program Synchronization zone bit SFlag, if SFlag=1, is namely in waiting status from control program, and it is the storage space of ADDR8 that IN the first test and excitation program generated by S106 is sent to from control chip address, turns S108; If SFlag=0, represent from control program and be in busy condition, turn S107;

S108MFlag is set to 1, represents that main control chip enters waiting status;

S109 receives IN the second test and excitation program sent from control program, is the storage space of ADDR3 stored in main control chip address;

S110 primary control program is according to the value of RADDR2 heavy duty address AD DR2 and jump to address AD DR2, order performs IN the first test and excitation program that primary control program generates, then address AD DR3 is jumped to, order performs IN the second test and excitation program from control Program Generating, first test and excitation program execution result is recorded in the storage space that start address is ADDR4, and the second test and excitation program execution result is recorded in the storage space that start address is ADDR5;

S111 primary control program detects from control program execution result Returning mark position ResultFlag, if ResultFlag=1, represent from control program and IN the first test and excitation program performed from control chip and IN the second test and excitation program execution result are returned to main control chip, turn S112; If ResultFlag=0, represent from control program and also IN the first test and excitation program performed from control chip and IN the second test and excitation program execution result are not returned to main control chip, turn S111;

S112 contrasts main control chip and performs the result of IN the first test and excitation program and IN the second test and excitation program from control chip respectively, as execution result is different, turns S113; Otherwise LoopNum1 increases 1, if LoopNum1<MAXLOOP1, turns S104, if LoopNum1 >=MAXLOOP1, returns settling signal to debug host, turn S114;

S113 records the first test and excitation program or the second test and excitation program and main control chip that make a mistake and the result performing the first test and excitation program or the second test and excitation program from control chip, and record content is passed to debug host by JTAG1;

S114 terminates primary control program;

From control chip be compatible chip to be verified, from control chip be connected with HPI bus with debug host.Be connected with debug host by JTAG2 from control chip, communicated with other resource on development board by HPI bus.Download from control program from control chip from debug host, run from control program, be responsible for generating from control program test excitation---the second test and excitation program, run the first test and excitation program and the second test and excitation program.Composition graphs 2, from control program circuit is:

S101 ' is identical with the S101 of primary control program, defines responsive point set; At the storage space that to define with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 be respectively start address from control chip address space, for depositing the data and code that produce follow-up implementation from control program temporarily, because primary control program generates multistage second test and excitation program in test process, main control chip will take a slice storage space, definition RADDR7 equals ADDR7, the value of RADDR7 be described multistage second test and excitation program in the start address stored from control chip, for carrying out heavy duty to address ADDR7;

S102 ' is identical with the S102 of primary control program, defined instruction model and test and excitation template;

S103 ' define program loop variable LoopNum2=0, LoopNum2 controls the circulation pass from control program stochastic generation test data in proof procedure, defines the predetermined cycle index MAXLOOP2 (namely MAXLOOP2 equal MAXLOOP1) identical with primary control program; Definition temporary variable k=0; Define from control Program Synchronization zone bit SFlag, represent when SFlag is 1 from control chip and be in the state that wait-receiving mode main control chip sends the first test and excitation program; Define and to represent when Returning mark position ResultFlag, ResultFlag are 1 from control program from control program execution result and the first test and excitation program and the second test and excitation program execution result are write back to main control chip storage space;

S104 ' resets from control Program Synchronization zone bit, and namely SFlag sets to 0, and ResultFlag sets to 0;

S105 ' is identical with the S105 of primary control program, generates the second test data, forms the second test data set DataSet2, and it take ADDR6 as the storage space of start address that DataSet2 leaves in from control chip;

S106 ' according to instruction template stochastic generation IN (IN>KpNum*KN/2) the bar instruction to be tested of S102 ' definition, for the instruction to be tested of every bar, according to test and excitation template stochastic generation second test and excitation program; Be that the instruction to be tested of IN bar generates IN section second test and excitation program serially, the process generating the second test and excitation program for the instruction to be tested of every bar is identical, includes following steps:

If S106.1 ' instruction to be tested is the instruction of computing class, a first Stochastic choice OpNum operand from test data set DataSet2; Then generate before instruction and move instruction, move instruction and act as operand is moved in the register of correspondence, after instruction, generate the 4th store instruction, the 4th store instruction act as operation result is stored into from control chip address be the storage space of ADDR10; Finally the second test and excitation program being stored into from controlling chip address is the storage space of ADDR7; Turn S106.3 ';

If S106.2 ' instruction to be tested is for controlling class instruction, before instruction, first generates the 5th store instruction, the 5th store instruction act as current status register value is stored into from control chip address be the storage space of ADDR10; Then after instruction, generation the 6th stores instruction, and it is the storage space of ADDR10 that the 6th storage instruction act as after execution, status register value is stored into from controlling chip address; Finally the second test and excitation program being stored into from controlling chip address is the storage space of ADDR7; Turn S106.3 ';

S106.3 ' ADDR7 increases an address bit, ADDR10 increases an address bit, k increases 1, if k<InsNum, represent that described instruction to be tested still has demand model not generate the second test and excitation program, turn S106 ', if k >=InsNum, represent from control program for all demand models of this instruction to be tested generate the second test and excitation program, if be that the instruction to be tested of IN bar generates IN section second test and excitation program, turn S107 '; Otherwise, turn S106 ', for next instruction to be tested generates the second test and excitation program;

S107 ' puts 1 from control Program Synchronization zone bit SFlag, represents from control chip and has been in the state that wait-receiving mode main control chip sends the first test and excitation program;

IN the first test and excitation program that S108 ' reception primary control program sends, stored in being the storage space of ADDR8 from control chip start address;

S109 ' detection primary control program synchronous mark position MFlag, if MFlag=1, namely primary control program is in waiting status, IN the second test and excitation program from control Program Generating is sent to the storage space that main control chip start address is ADDR3, turns S110 '; Otherwise, turn S109 ';

S110 ' from control program according to RADDR7 heavy duty address AD DR7 initial value and jump to address AD DR7, order performs IN the second test and excitation program from control Program Generating, then address AD DR8 is jumped to, order performs IN the first test and excitation program that primary control program generates, and the first test and excitation execution result and the second test and excitation program execution result are recorded in the storage space that start address is ADDR9 and ADDR10 respectively;

First test and excitation execution result is sent to the storage space that main control chip address is ADDR11 by S111 ', second test and excitation program execution result is sent to the storage space that main control chip address is ADDR12, and will put 1 from control program execution result Returning mark position ResultFlag;

S112 ' LoopNum2 increases 1, if LoopNum2<MAXLOOP2, represents from control program and not yet reaches the predetermined cycle index of program, turn S104 '; If LoopNum2 >=MAXLOOP2, represent from control program and reached the predetermined cycle index of program, from control EOP (end of program).

S301 debug host by CCS Integrated Development Environment by compiled primary control program and from control program respectively by JTAG1 and JTAG2 download to main control chip and from control chip; And start and respectively perform primary control program and from control program;

S302 main control chip runs primary control program, run from control program from control chip simultaneously, primary control program is responsible for generating main control chip test and excitation, is controlled main control chip execution test and excitation, comparison main control chip and perform test and excitation result from controlling chip and process from controlling chip execution result mistake, is responsible for generating from control chip testing excitation from control program, controls to perform test and excitation from controlling chip:

S302.1 primary control program and simultaneously define respective responsive point set respectively from control program, definition sensitive spot concentrates sensitive spot number to be KpNum; The storage space that to define with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 and ADDR12 respectively in main control chip address space be start address, for depositing data and the code of primary control program interim generation in follow-up implementation, definition RADDR2 equals ADDR2, for carrying out heavy duty to address ADDR2; At the storage space that to define with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 be respectively start address from control chip address space, for depositing the data and code that produce follow-up implementation from control program temporarily, definition RADDR7 equals ADDR7, for carrying out heavy duty to address ADDR7;

S302.2 primary control program and simultaneously define respective demand model and test and excitation template respectively from control program; Primary control program is identical with from the process of control application definition demand model, treat brake instruction by Object--oriented method and carry out abstract modeling, defined instruction model, process is as follows: instruction is divided into some fields by the effect according to different instruction position, instruction inside, as opcode field, operand field, conditional execute bit field, parallel bit field etc., each field is the stochastic variable of a Prescribed Properties, and constraint condition defines the ratio of the type of stochastic variable field, span and stochastic distribution; Different demand models is set up in instruction for different types of structure, comprise double operand instruction, single-operand instruction and no operand instruction, the number of instruction operands is made to be that (OpNum of double operand instruction equals 2 to OpNum, the OpNum of single-operand instruction equals 1, the OpNum of no operand instruction equals 0), make demand model number be InsNum (the value and instruction collection of InsNum is relevant); Primary control program and from control program simultaneously respectively on the basis of demand model, for the instruction of computing class with control class instruction and set up test and excitation template respectively, primary control program is identical with from the test and excitation template of control program; Computing class instruction testing excitation template comprise three parts: beamhouse operation number: concurrently OpNum operand is moved in OpNum register, execution instruction, result is write back to storage space; Control class instruction testing excitation template and comprise three parts, status register value after storage current status register value, execution instruction, storage perform; Need the status register preserved according to the type selecting of execution control class instruction, control class command function and comprise: reprogramming execution sequence, change pipeline state, change perform authority and change buffer status;

S302.3 primary control program define program loop variable LoopNum1=0, LoopNum1 controls the circulation pass of primary control program stochastic generation test data in proof procedure, the predetermined cycle index MAXLOOP1 of definition primary control program, primary control program definition temporary variable j=0, definition primary control program synchronous mark position MFlag; Simultaneously from control application definition program loop variables L oopNum2=0, LoopNum2 controls the circulation pass from control program stochastic generation test data in proof procedure, define from the control predetermined cycle index MAXLOOP2 of program (MAXLOOP2=MAXLOOP1), from control application definition temporary variable k=0, define from control Program Synchronization zone bit SFlag, from control application definition execution result Returning mark position ResultFlag;

S302.4 primary control program reset primary control program synchronous mark position, namely MFlag sets to 0; From control Program reset from control Program Synchronization zone bit, namely SFlag sets to 0, and ResultFlag sets to 0;

S302.5 primary control program and simultaneously generate the first test data and the second test data from control program, form test and excitation sensitivity volume, method is as follows: primary control program is identical with from the process of control Program Generating test data, utilize normal distribution random number generating function generate KN (KN gets 100 ~ 1000 usually) individual centered by sensitive spot, fixed value (fixed value can get the arbitrary value in sensitive spot floating point representation in mantissa's variation range) is variance, the test data meeting normal distribution; Normal distribution random number generating function comprises two steps: the first step utilizes random number generator generation in C language built-in function to meet equally distributed random number; Second step uses BoxMuller method, and these equally distributed random numbers are converted to the random number meeting normal distribution; KpNum*KN the first test data that primary control program sensitive spot concentrates KpNum sensitive spot to generate; From KpNum*KN the second test data that control program sensitive spot concentrates KpNum sensitive spot to generate; The first test data that primary control program generates forms the first test data set DataSet1, it take ADDR1 as the storage space of start address that DataSet1 leaves in main control chip, form the second test data set DataSet2 from the second test data of control Program Generating, it take ADDR6 as the storage space of start address that DataSet2 leaves in from control chip;

S302.6 primary control program and simultaneously generate IN bar instruction to be tested according to the demand model of S302.2 definition respectively from control program; Primary control program turns S302.6.1, generates IN the first test and excitation program; Meanwhile, turn S302.6.1 ' from control program, generate IN the second test and excitation program;

S302.6.1 primary control program is that the instruction to be tested of IN bar generates IN the first test and excitation program serially, and the method generating the first test and excitation program for the instruction to be measured of every bar is all identical, and process is as follows:

If S302.6.1.1 instruction to be tested is the instruction of computing class, a first Stochastic choice OpNum operand from test data set DataSet1; Then generate before instruction to be tested and move instruction, move instruction and act as operand is moved in the register of correspondence; After instruction to be tested, generate first store instruction, the first storage instruction act as is stored into operation result the storage space that main control chip address is ADDR4; Finally the first test and excitation program is stored into the storage space that main control chip address is ADDR2, turns S302.6.1.3;

If S302.6.1.2 instruction to be tested is for controlling class instruction, before instruction to be tested, first generates second store instruction, the second storage instruction act as is stored into current status register value the storage space that main control chip address is ADDR4; Then after instruction to be tested, generate the 3rd store instruction, the 3rd storage instruction act as is stored into status register value after execution the storage space that main control chip address is ADDR4; Finally the first test and excitation program is stored into the storage space that main control chip address is ADDR2, turns S302.6.1.3;

S302.6.1.3ADDR2 increases an address bit, ADDR4 increases an address bit, j increases 1, if j<InsNum, represent that described instruction to be tested still has demand model not generate the first test and excitation program, primary control program turns S302.6.1, if j >=InsNum, represent primary control program for all demand models of this instruction to be tested generate the first test and excitation program, if be that the instruction to be tested of IN bar generates IN section first test and excitation program, primary control program turns S302.7, otherwise, primary control program turns S302.6.1), primary control program generates the first test and excitation program for next instruction to be tested,

S302.6.2 is that the instruction to be tested of IN bar generates IN the second test and excitation program from control program serially, and the process generating the second test and excitation program for the instruction to be measured of every bar is all identical, includes following steps:

If S302.6.2.1 instruction to be tested is the instruction of computing class, a first Stochastic choice OpNum operand from DataSet2; Then generate before instruction to be tested and move instruction, move instruction and act as operand is moved in the register of correspondence; After instruction to be tested, generate the 4th store instruction, the 4th store instruction act as operation result is stored into from control chip address be the storage space of ADDR10; Finally the second test and excitation program being stored into from control chip address is the storage space of ADDR7, turns S302.6.2.3;

If S302.6.2.2 instruction to be tested is for controlling class instruction, before instruction to be tested, first generates the 5th store instruction, the 5th store instruction act as current status register value is stored into from control chip address be the storage space of ADDR10; Then after instruction to be tested, generation the 6th stores instruction, and it is the storage space of ADDR10 that the 6th storage instruction act as after execution, status register value is stored into from controlling chip address; Finally the second test and excitation program being stored into from control chip address is the storage space of ADDR7, turns S302.6.2.3;

S302.6.2.3ADDR7 increases an address bit, ADDR10 increases an address bit, k increases 1, if k<InsNum, represent that described instruction to be tested still has demand model not generate the second test and excitation program, turn S302.6.2 from control program, if k >=InsNum, represent from control program for all demand models of this instruction to be tested generate the second test and excitation program, if be that the instruction to be tested of IN bar generates IN section second test and excitation program, turn S302.7 from control program; Otherwise, turn S302.6.2 from control program, for next instruction to be tested generates the second test and excitation program;

Synchronous mark position SFlag is put 1 from control program by S302.7, represents from control chip and has been in the state that wait-receiving mode main control chip sends IN the first test and excitation program, turn S302.8; Simultaneously, primary control program detects from control Program Synchronization zone bit SFlag, if SFlag=1, represents from control program and is in waiting status, it is the storage space of ADDR8 that the IN of generation the first test and excitation program is all sent to from control chip address by primary control program, turns S302.8; Otherwise, turn S302.7;

MFlag is put 1 by S302.8 primary control program, and represent that main control chip enters waiting status, primary control program turns S302.9; Simultaneously from control Programmable detection primary control program synchronous mark position MFlag, if MFlag=1, namely primary control program is in waiting status, turns S302.9 from control program; Otherwise, turn S302.8 from control program;

The IN of generation the second test and excitation program is sent to the storage space that main control chip start address is ADDR3 from control program by S302.9, and primary control program receives IN the second test and excitation program sent from control program simultaneously;

S302.10 primary control program according to RADDR2 heavy duty address AD DR2 initial value and jump to address AD DR2, order performs IN the first test and excitation program that primary control program generates, then address AD DR3 is jumped to, order performs IN the second test and excitation program from control Program Generating, first test and excitation program execution result is recorded in the storage space that start address is ADDR4, and the second test and excitation program execution result is recorded in the storage space that start address is ADDR5; Simultaneously jump to address AD DR7 from control program according to the initial value of RADDR7 heavy duty address AD DR7, order performs IN the second test and excitation program from control Program Generating, then address AD DR8 is jumped to, order performs IN the first test and excitation program that primary control program generates, and the first test and excitation execution result and the second test and excitation program execution result are recorded in the storage space that start address is ADDR9 and ADDR10 respectively;

First test and excitation execution result is sent to the storage space that main control chip address is ADDR11 from control program by S302.11, second test and excitation program execution result is sent to the storage space that main control chip address is ADDR12, and 1 will be put from control program execution result Returning mark position ResultFlag, turn S302.12 from control program; Primary control program detects from control program execution result Returning mark position ResultFlag simultaneously, if ResultFlag=1, represent from control program and will return to main control chip from control chip execution IN the first test and excitation program and IN the second test and excitation program execution result, primary control program turns S302.12; If ResultFlag=0, represent from control program and also will not return to main control chip from control chip execution IN the first test and excitation program and IN the second test and excitation program execution result, primary control program turns S302.11;

S302.12 primary control program contrasts main control chip and performs the result of IN the first test and excitation program and IN the second test and excitation program from control chip respectively, as execution result is different, turns S302.13; Otherwise LoopNum1 increases 1, LoopNum2 and increases 1, and primary control program turns S302.12.1, turn S302.12.2 from control program simultaneously;

S302.12.1 primary control program compares the size of LoopNum1 and MAXLOOP1, if LoopNum1<MAXLOOP1, primary control program turns S302.4; If LoopNum1 >=MAXLOOP1, primary control program returns settling signal to debug host, and primary control program turns S302.14;

S302.12.2 compares the size of LoopNum2 and MAXLOOP2 from control program, if LoopNum2<MAXLOOP2, turns S302.4 from control program; If LoopNum2 >=MAXLOOP2, terminate from control program;

The first test and excitation program that S302.13 primary control program record makes a mistake or the second test and excitation program and main control chip and perform the result of the first test and excitation program or the second test and excitation program from control chip, and record content is passed to debug host by JTAG1;

S302.14 terminates primary control program, turns S303;

If S303 debug host receives the settling signal that primary control program is passed back by JTAG1, proof procedure terminates; If debug host receives primary control program and passes the first test and excitation program or the second test and excitation program and main control chip that make a mistake and the result performing the first test and excitation program or the second test and excitation program from control chip back by JTAG1, debug host shows the first test and excitation program or the second test and excitation program and main control chip that make a mistake and the result performing the first test and excitation program or the second test and excitation program from control chip, and proof procedure terminates.

Fig. 4 is that the test and excitation of the instruction of computing class and the instruction of control class in the present invention generates template.Computing class instruction testing excitation template comprise three parts: concurrently OpNum operand is moved in OpNum register, execution instruction, result is write back to storage space.Control class instruction testing excitation template and comprise three parts, status register value after storage current status register value, execution instruction, storage perform.Need the status register preserved according to the type selecting of execution control class instruction, control class command function and comprise: reprogramming execution sequence, change pipeline state, change perform authority and change buffer status.

Fig. 5 is main control chip and from control chip-stored spatial data flowing schematic diagram.Main control chip and from control chip carry out data transmission by HPI bus, message transmission rate easily becomes bottleneck, and the data that therefore can as far as possible make program use are stored in the address space of chip oneself.The storage space that to define with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 and ADDR12 respectively in main control chip address space be start address, for depositing the primary control program interim data that produce and code in follow-up implementation.At the storage space that to define with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 be respectively start address from control chip address space, for depositing from control the program interim data that produce and code follow-up implementation.Primary control program generates the first test data and the first test and excitation program in the process of implementation, is stored in the storage space that main control chip start address is ADDR1 and ADDR2 respectively.Generate the second test data and the second test and excitation program in the process of implementation from control program, being stored in from controlling chip start address is respectively the storage space of ADDR6 and ADDR7.First test and excitation program is moved to being the storage space of ADDR8 from control chip start address by HPI data bus by primary control program, from control program by HPI data bus the second test and excitation program moved to main control chip start address be the storage space of ADDR3.After primary control program executes the first test and excitation program and the second test and excitation program, first test and excitation program execution result is recorded in the storage space that main control chip start address is ADDR4, and the second test and excitation program execution result is recorded in the storage space that main control chip start address is ADDR5.After executing the first test and excitation program and the second test and excitation program from control program, first test and excitation execution result and the second test and excitation program execution result are recorded in respectively from control chip start address be the storage space of ADDR9 and ADDR10, and execution result is moved to main control chip start address be the storage space of ADDR11 and ADDR12.Like this, when can ensure executive routine to greatest extent, instruction and data is all in the local storage space of chip.

When main control chip runs primary control program, primary control program generates the storage space that the first test and excitation program is stored in ADDR2, from control program the second test and excitation program moved to main control chip start address be the storage space of ADDR3, primary control program according to RADDR2 heavy duty address AD DR2 initial value and jump to address AD DR2, order performs IN the first test and excitation program that primary control program generates, then address AD DR3 is jumped to, order performs IN the second test and excitation program from control Program Generating, first test and excitation program execution result is recorded in the storage space that start address is ADDR4, second test and excitation program execution result is recorded in the storage space that start address is ADDR5.By HPI bus, the first test and excitation execution result is sent to the storage space that main control chip address is ADDR11 from control program, the second test and excitation program execution result is sent to the storage space that main control chip address is ADDR12.Primary control program contrasts main control chip and performs the result of IN the first test and excitation program and IN the second test and excitation program from control chip respectively, and execution result compares.

When running from control program from control chip, the storage space of ADDR7 is stored in from control Program Generating second test and excitation program, first test and excitation program is moved to being the storage space of ADDR8 from control chip start address by primary control program, from control program according to RADDR7 heavy duty address AD DR7 initial value and jump to address AD DR7, order performs IN the second test and excitation program from control Program Generating, then address AD DR8 is jumped to, order performs IN the first test and excitation program that primary control program generates, first test and excitation program execution result and the second test and excitation program execution result are recorded in the storage space that start address is ADDR9 and ADDR10 respectively, then by HPI bus, the first test and excitation execution result is sent to the storage space that main control chip address is ADDR11, second test and excitation program execution result is sent to the storage space that main control chip address is ADDR12.

Claims

1., towards a demo plant after the microprocessor silicon of compatible design, to it is characterized in that after the microprocessor silicon of compatible design demo plant is by debug host, development board, main control chip with form from control chip:

Debug host is with main control chip, be connected from controlling chip; Debug host is connected by the first joint test working group JTAG1 with main control chip, is connected by the second joint test working group JTAG2 with from control chip; Debug host has the two cover softwares utilizing CCS Integrated Development Environment to develop: primary control program and from control program, primary control program be responsible for generating main control chip test and excitation, control main control chip perform test and excitation, comparison main control chip with from the software controlled chip and perform test and excitation result and process from controlling chip execution result mistake; Be responsible for generating from control chip testing excitation, control to perform the software of test and excitation from control chip from control program;

Development board is the general development board being equipped with multiple interfaces and bus, and can dispose multiple processor chips, chip chamber is connected by data bus, and each chip has the stand-alone interface communicated with debug host; Main control chip, from control chip be inserted into development board;

Main control chip is that main control chip is connected with HPI bus with debug host by chip or the objective chip of checking; Main control chip is connected with debug host by JTAG1, is undertaken communicating and access other resource on development board by HPI bus; Main control chip downloads primary control program from debug host, run primary control program, be responsible for generating main control chip test and excitation, control main control chip execution test and excitation, comparison main control chip and perform test and excitation result from controlling chip and process from controlling chip execution result mistake, check result passes to debug host by JTAG1 again;

From control chip be compatible chip to be verified, from control chip be connected with HPI bus with debug host; Be connected with debug host by JTAG2 from control chip, undertaken communicating and access other resource on development board by HPI bus; From control chip from debug host download from control program, run from control program, be responsible for excitation and generate, encourage and run.

2., as claimed in claim 1 towards demo plant after the microprocessor silicon of compatible design, it is characterized in that,

Described primary control program flow process is:

The first step, the responsive point set in definition proof procedure, responsive point set is made up of sensitive spot, and sensitive spot is affect larger particular values to operation result precision and accuracy in floating-point operation, comprises positive negative zero, positive minus infinity and invalid number; Making sensitive spot concentrate sensitive spot number to be KpNum, KpNum is positive integer; The storage space that to define with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 and ADDR12 respectively in main control chip address space be start address, definition RADDR2 equals ADDR2, and the value of RADDR2 is the start address that multistage first test and excitation program stores in main control chip;

Second step, defined instruction model and test and excitation template;

3rd step, definition primary control program loop variable LoopNum1=0, the predetermined cycle index MAXLOOP1 of define program, MAXLOOP1 is positive integer, definition temporary variable j=0, definition primary control program synchronous mark position MFlag, represents when MFlag is 1 that main control chip has been in wait-receiving mode sends the second test and excitation program state from control chip;

5th step, generate the first test data, form the first test data set DataSet1, method is: each sensitive spot that primary control program is concentrated sensitive spot, utilize normal distribution random number generating function generate KN centered by sensitive spot, fixed value is variance, meets the first test data of normal distribution, KN is positive integer; KpNum*KN the first test data that sensitive spot concentrates KpNum sensitive spot to generate forms the first test data set DataSet1, and it take ADDR1 as the storage space of start address that DataSet1 leaves in main control chip;

6th step, according to the demand model stochastic generation IN bar instruction to be tested of second step definition, IN is positive integer, IN>KpNum*KN/2; For the instruction to be tested of every bar, according to the test and excitation template stochastic generation first test and excitation program of second step definition; Be that the instruction to be tested of IN bar generates IN section first test and excitation program serially, the process generating the first test and excitation program for the instruction to be tested of every bar is identical, includes following steps:

6.3ADDR2 increases an address bit, address bit=machine work is wide/and 8, ADDR4 increases an address bit, j increases 1, if j<InsNum, represent that described instruction to be tested still has demand model not generate the first test and excitation program, turn the 6th step, if j >=InsNum, represent primary control program for all demand models of this instruction to be tested generate the first test and excitation program, if be that the instruction to be tested of IN bar generates IN section first test and excitation program, turn the 7th step, otherwise, turn the 6th step;

14 step, primary control program terminates;

Described from control program circuit be:

Step 1. is identical with the first step of primary control program, defines responsive point set; At the storage space that to define with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 be respectively start address from control chip address space, for depositing the data and code that produce follow-up implementation from control program temporarily, definition RADDR7 equals ADDR7, the value of RADDR7 be multistage second test and excitation program in the start address stored from control chip, for carrying out heavy duty to address ADDR7;

Step 2. defined instruction model and test and excitation template;

Step 3. define program loop variable LoopNum2=0, LoopNum2 control the circulation pass from control program stochastic generation test data in proof procedure, define predetermined cycle index MAXLOOP2, the MAXLOOP2 identical with primary control program and equal MAXLOOP1; Definition temporary variable k=0; Define from control Program Synchronization zone bit SFlag, represent when SFlag is 1 from control chip and be in the state that wait-receiving mode main control chip sends the first test and excitation program; Define and to represent when Returning mark position ResultFlag, ResultFlag are 1 from control program from control program execution result and the first test and excitation program and the second test and excitation program execution result are write back to main control chip storage space;

Step 4. resets from control Program Synchronization zone bit, and namely SFlag sets to 0, and ResultFlag sets to 0;

Step 5. is identical with the 5th step of primary control program, generates the second test data, forms the second test data set DataSet2, and it take ADDR6 as the storage space of start address that DataSet2 leaves in from control chip;

The instruction template stochastic generation IN bar instruction to be tested that step 6. defines according to step 2, for the instruction to be tested of every bar, according to test and excitation template stochastic generation second test and excitation program; Be that the instruction to be tested of IN bar generates IN section second test and excitation program serially, the process generating the second test and excitation program for the instruction to be tested of every bar is identical, includes following steps:

Step 7. puts 1 from control Program Synchronization zone bit SFlag, represents from control chip and has been in the state that wait-receiving mode main control chip sends the first test and excitation program;

Step 8. receives IN the first test and excitation program that primary control program sends, stored in being the storage space of ADDR8 from control chip start address;

Step 9. detects primary control program synchronous mark position MFlag, if MFlag=1, namely primary control program is in waiting status, IN the second test and excitation program from control Program Generating is sent to the storage space that main control chip start address is ADDR3, goes to step 10; Otherwise, go to step 9;

Step 10. from control program according to RADDR7 heavy duty address AD DR7 initial value and jump to address AD DR7, order performs IN the second test and excitation program from control Program Generating, then address AD DR8 is jumped to, order performs IN the first test and excitation program that primary control program generates, and the first test and excitation execution result and the second test and excitation program execution result are recorded in the storage space that start address is ADDR9 and ADDR10 respectively;

First test and excitation execution result is sent to the storage space that main control chip address is ADDR11 by step 11., second test and excitation program execution result is sent to the storage space that main control chip address is ADDR12, and will put 1 from control program execution result Returning mark position ResultFlag;

Step 12.LoopNum2 increases 1, if LoopNum2<MAXLOOP2, represents from control program and not yet reaches the predetermined cycle index of program, go to step 4; If LoopNum2 >=MAXLOOP2, represent from control program and reached the predetermined cycle index of program, from control EOP (end of program).

3., as claimed in claim 2 towards demo plant after the microprocessor silicon of compatible design, it is characterized in that, described KN span is 100 ~ 1000, and described fixed value gets the arbitrary value in sensitive spot floating point representation in mantissa's variation range.

4. as claimed in claim 2 towards demo plant after the microprocessor silicon of compatible design, it is characterized in that, described normal distribution random number generating function comprises two steps: the first step utilizes random number generator generation in C language built-in function to meet equally distributed random number; Second step uses classical BoxMuller algorithm that these equally distributed random numbers are converted to the random number meeting normal distribution.

5. as claimed in claim 2 towards demo plant after the microprocessor silicon of compatible design, it is characterized in that, described primary control program and from control program the method for defined instruction model and test and excitation template be: treat brake instruction by Object--oriented method and carry out abstract modeling, defined instruction model, process is: instruction is divided into some fields by the effect according to different instruction position, instruction inside, comprise opcode field, operand field, conditional execute bit field, parallel bit field, each field is the stochastic variable of a Prescribed Properties, constraint condition defines the type of stochastic variable field, the ratio of span and stochastic distribution, different demand models is set up in instruction for different types of structure, comprise double operand instruction, single-operand instruction and no operand instruction, the number of instruction operands is made to be OpNum, the OpNum of double operand instruction equals 2, the OpNum of single-operand instruction equals 1, the OpNum of no operand instruction equals 0, and making demand model number be InsNum, InsNum is positive integer, on the basis of demand model, for test and excitation template is set up in the instruction of computing class and the instruction of control class respectively, computing class instruction testing excitation template comprise three parts: concurrently OpNum operand is moved in OpNum register, execution instruction, result is write back to storage space, control class instruction testing excitation template and comprise three parts: status register value after storage current status register value, execution instruction, storage perform, need the status register preserved according to the type selecting of execution control class instruction, control class command function and comprise: reprogramming execution sequence, change pipeline state, change perform authority and change buffer status.

6., as claimed in claim 2 towards demo plant after the microprocessor silicon of compatible design, it is characterized in that, described MAXLOOP1 and MAXLOOP2 is set to 1% of computational space.

7., as claimed in claim 2 towards demo plant after the microprocessor silicon of compatible design, it is characterized in that, described primary control program or from control program the first test data set DataSet1 or the second test data set DataSet2 generative process as follows:

7.1 defining variable i=0;

I-th sensitive spot that the 7.2 pairs of sensitive spots are concentrated, generate KN centered by sensitive spot, fixed value is variance, meets the test data of normal distribution, add in DataSet1 or DataSet2 by the test data of generation, i increases 1;

If 7.3 i<KpNum, turn 7.2; If i >=KpNum, DataSet1 or DataSet2 generate end.

8. the compatible chip that after adopting the microprocessor silicon in claim 1 ~ 7 described in arbitrary claim, demo plant treats checking carries out a method for functional verification, it is characterized in that comprising the following steps:

Step one, debug host by CCS Integrated Development Environment by compiled primary control program and from control program respectively by JTAG1 and JTAG2 download to main control chip and from control chip, and start and respectively perform primary control program and from control program;

2.2) primary control program and simultaneously define respective demand model and test and excitation template respectively from control program;

2.3) primary control program define program loop variable LoopNum1=0, LoopNum1 controls the circulation pass of primary control program stochastic generation test data in proof procedure, the predetermined cycle index MAXLOOP1 of definition primary control program, primary control program definition temporary variable j=0, definition primary control program synchronous mark position MFlag; Simultaneously from control application definition program loop variables L oopNum2=0, LoopNum2 controls the circulation pass from control program stochastic generation test data in proof procedure, define from the predetermined cycle index MAXLOOP2 of control program, MAXLOOP2=MAXLOOP1, from control application definition temporary variable k=0, define from control Program Synchronization zone bit SFlag, from control application definition execution result Returning mark position ResultFlag;

2.5) primary control program and simultaneously generate the first test data and the second test data from control program, form test and excitation sensitivity volume, method is as follows: primary control program is identical with from the process of control Program Generating test data, utilize normal distribution random number generating function generate KN centered by sensitive spot, fixed value is variance, meets the test data of normal distribution; KpNum*KN the first test data that primary control program sensitive spot concentrates KpNum sensitive spot to generate; From KpNum*KN the second test data that control program sensitive spot concentrates KpNum sensitive spot to generate; The first test data that primary control program generates forms the first test data set DataSet1, it take ADDR1 as the storage space of start address that DataSet1 leaves in main control chip, form the second test data set DataSet2 from the second test data of control Program Generating, it take ADDR6 as the storage space of start address that DataSet2 leaves in from control chip;

2.14) terminate primary control program, go to step three;