CN104573228B - Towards the microprocessor silicon posteriority card device and verification method of compatible design - Google Patents

Abstract

The invention discloses a kind of microprocessor silicon posteriority card device and verification method towards compatible design, it is therefore an objective to solve that the test and excitation formation speed that function compatibility verification technique after existing microprocessor silicon is present is slow, the result checks the problems such as low efficiency and complicated control.The present invention be " MS master-slave " double-chip structure, by debugging main frame, development board, main control chip and from control chip constitute.There is primary control program and from control program on debugging main frame, main control chip and by downloading and run primary control program and from control program respectively from control chip, encouraged in main control chip and from generation, testing results on control chip, and be responsible for comparing the operation result of test and excitation program by main control chip and from control chip by primary control program, finally show the result on debugging main frame.The present invention is without artificial interference verification process, and hardware platform control is simple, can effectively improve the accuracy and verification efficiency verified after silicon.

Description

Towards the microprocessor silicon posteriority card device and verification method of compatible design

Technical field

The present invention relates to functional verification field after microprocessor silicon, more particularly to a kind of compatible chip instruction set computer silicon Apparatus and method of functional verification afterwards.

Background technology

Military microprocessor (including CPU and DSP) is widely used in guided missile, satellite, aircraft, naval vessels, radar, tank and army With fields such as secret communications.Due to a large amount of import foreign chips, face embargo and threat out of stock, security and reliability it is hidden Suffer from, the compatible military microprocessor of independent development, realization production domesticization substitute significant.

Signified compatibility of the invention, is primarily referred to as independent development microprocessor, realizes to the pluggable of external microprocessor It is replaced, it is desirable to consistent with external product in many aspects such as profile and encapsulation, function, performance, electric parameter.For description side Just, the external microprocessor for intending developing is referred to as objective chip by the present invention, and our the compatible microprocessors of independent development are claimed It is compatible chip.

Instruction, encapsulation, the interface required with external mainstream microprocessor are replaced in the production domesticization of microprocessor in armament systems Sequential is completely compatible, and the checking of compatibility faces huge challenge.Present invention is generally directed to the compatible checking of function, its implication refers to simultaneous Hold chip has following characteristics compared to objective chip：The visible hardware resource of programmer is consistent with objective chip；Correctly, as one man Realize cpu instruction complete or collected works；The result that code is performed and Observable state consistency；External components function is consistent with application method；Firmly Part collocation method is consistent with start-up mode setting.

The compatible checking of function may be embodied in the checking before throwing piece and throw two stages of the checking after piece (being verified i.e. after silicon). Tradition verifies that the means for using have two before throwing piece, and one is the simplation verification based on software, and two is that the hardware based on emulator is imitated Very.Simplation verification flexibility ratio is high, observability is strong, with low cost, but speed is slow, proving period is long, is suitable to functional part Verified.Simulation hardware downloads to register stage design code in hardware emulator, and test and excitation is performed using hardware, its Speed is fast, observability is strong, but with high costs, is that complicated multi core chip builds the multiple emulators associations of hardware simulation platform needs It is difficult in maintenance with work.No matter software is simulated or simulation hardware, and test and excitation is all the bottleneck of checking, for simplation verification For, substantial amounts of test and excitation will increase the proving period time, and then mean function in order to control time reduces test and excitation The reduction of coverage rate；For simulation hardware, the mode of tradition generation excitation, its speed far can not meet emulator speed The need for, this is greatly to waste for accelerating platform.

Verifying speed is fast after silicon, can carry out functional verification in all directions to chip within a short period of time, it is ensured that higher covers Lid rate.After traditional silicon the compatible checking of function generally using manpower comparing compared with method, Qualify Phase transports compatible chip after silicon Capable result and objective chip operation result carry out manpower comparing compared with, its difficult point is the situation for being difficult to exhaustive various BORDER PROCESSINGs, Checking coverage rate is difficult to ensure that, verification efficiency is very low, and proving period is very long.And, verify same as simulation hardware, after silicon The bottleneck of test and excitation formation speed is faced with, preferable test and excitation generation method should speed be fast, coverage rate is high, redundancy It is low.Checking needs hardware accelerator to provide a large amount of test and excitations inputs after most of silicon, and different test template correspondences is different Hardware accelerator, be to ensure that excitation produces speed, hardware accelerator can not be excessively complicated.The shortcoming of this method is Bandwidth between hardware accelerator and processor chips can turn into system bottleneck, on the other hand, when test template is more, it is necessary to A large amount of hardware accelerators, the control and scheduling of intermodule become complicated.Also have certain methods generate test and excitation when The implementing result of processor is implied, this simplifies the work that result is compared, but it is higher to test and excitation generation scheme requirement, And range of application is not wide.Method more often is individually designed arithmetic logic, and the excitation that will be loaded into processor is also loaded into fortune Calculate in logic, and the result that the result of generation is produced with processor is made comparisons, whether correct performed with this decision processor.This The problem of the method for kind is may be very complicated as the arithmetic logic of reference, or time overhead is very big, influences verifying speed.

The content of the invention

The technical problem to be solved in the present invention is：For the survey for realizing that function compatibility verification technique is present after microprocessor silicon Examination excitation formation speed is slow, the result checks the problems such as low efficiency and complicated control, proposes a kind of accurate, micro- place of efficient verification The compatible apparatus and method of reason device function, solve test and excitation during compatible chip checking and generate slow, the result inspection effect The problems such as rate is low complicated with hardware platform control, improves verification quality, shortens proving period.

Concrete technical scheme is：

The present invention is " MS master-slave " double-chip structure towards the microprocessor silicon posteriority card device of compatible design, is led by debugging Machine, development board, main control chip and from control chip composition.

Debugging main frame is to run development environment and control main control chip and the computer from control chip behavior, with main control chip It is connected with from control chip.Debugging main frame and main control chip by the first joint test working group (JiontTestActionGroup, JTAG) JTAG1 is connected, and debugging main frame is connected with from control chip by the second joint test working group JTAG2.Pacify on debugging main frame Equipped with business software -- code debugging device (CodeComposerStudio, CCS) IDE.There is utilization on debugging main frame Two sets of softwares of CCS IDEs exploitation：Primary control program and from control program, primary control program be responsible for generation main control chip survey Examination excitation, control main control chip perform test and excitation, comparison main control chip and perform test and excitation result and treatment with from control chip From the software of control chip implementing result mistake；Generation is responsible for from control program to be held from control chip from control chip testing excitation, control The software of row test and excitation.

Development board has been equipped with the general development board of multiple interfaces and bus, can dispose multiple processor chips, chip Between by data/address bus connect, each chip possess and debug main-machine communication stand-alone interface.Main control chip, from control chip be inserted into out On hair plate.

Main control chip is objective chip, and main control chip is HPI with debugging main frame and HPI buses (HostPortInterface) bus is connected.Main control chip is connected by JTAG1 with debugging main frame, by HPI buses and exploitation Other resources are communicated on plate.Main control chip is downloaded and runs primary control program from debugging main frame.

Primary control program flow is：

The first step, defines the sensitive point set in verification process, and sensitive point set is made up of sensitive spot, and sensitive spot is floating-point operation In larger particular values, including positive negative zero, positive minus infinity and invalid number are influenceed on operation result precision and the degree of accuracy；Order It is KpNum that sensitive spot concentrates sensitive spot number (KpNum is positive integer)；Defined respectively in main control chip address space with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 and ADDR12 are the memory space of initial address, for depositing master control The program interim data for producing and code during subsequent execution, because primary control program generates multistage first in test process Test and excitation program, will take a piece of memory space on main control chip, define RADDR2 and be equal to ADDR2, the value of RADDR2 For the initial address that the multistage the first test and excitation program is stored in main control chip；

Second step, defines demand model and test and excitation template；By Object--oriented method treat brake instruct into Row abstract modeling, defines demand model, and process is as follows：Be divided into for instruction some by the effect according to instruction internal different instruction position Field, such as opcode field, operand field, condition perform bit field, parallel bit field, and each field is one to be had about The stochastic variable of beam condition, constraints defines the ratio of type, span and the random distribution of stochastic variable field；For Different demand models, including double operand instruction, single-operand instruction and no-operand are set up in the instruction of different types of structure Instruction, (OpNum of double operand instruction is equal to 2, OpNum of single-operand instruction etc. for OpNum to make the number of instruction operands In 1,0) OpNum of no operand instruction is equal to, and (value of InsNum has with instruction set for InsNum to make demand model number Close)；It is that test and excitation template is set up in the instruction of computing class and control class instruction respectively on the basis of demand model；Computing class refers to Test and excitation template is made to include three parts：Concurrently OpNum operand is moved into OpNum register, execute instruction, Result back into memory space；Control class instruction testing excitation template includes three parts：Store current status register value, hold Status register value after row instruction, storage execution；According to the Status register for performing the type selecting needs preservation that control class is instructed Device, control class command function includes：Reprogramming execution sequence, change pipeline state, change perform authority and change caching State；

3rd step, defines primary control program in primary control program cyclic variable LoopNum1=0, LoopNum1 control verification process The circulation pass of random generation test data, the predetermined cycle-index MAXLOOP1 of definition program (MAXLOOP1 is positive integer, MAXLOOP1 takes the empirical value that checking can be made to reach target coverage rate, usual coverage rate target be set to computational space 1%), Temporary variable j=0 is defined, primary control program synchronous mark position MFlag, MFlag is defined and is represented that main control chip has been in when being 1 The state that the second test and excitation program is sent from control chip to be received；

4th step, reset primary control program synchronous mark position, i.e., MFlag sets to 0；

5th step, generates the first test data, constitutes the first test data set DataSet1, and method is：Primary control program pair Each sensitive spot that sensitive spot is concentrated, using normal distribution random number generating function generation KN, (KN is positive integer, and KN generally takes 100~1000) it is individual centered on sensitive spot, (fixed value can take in sensitive spot floating point representation in mantissa's excursion fixed value Arbitrary value) for variance, meet the first test data of normal distribution；Normal distribution random number generating function includes two steps：The One step meets equally distributed random number using random number generator generation in C language built-in function；Second step uses classics BoxMuller algorithms are (see baike.baidu.com/view/1710258.htmFr=aladdin it is) that these are equally distributed Random number is converted to the random number for meeting normal distribution；Sensitive spot concentrates the KpNum*KN that KpNum sensitive spot is generated individual the One test data constitutes the first test data set DataSet1, and DataSet1 is stored in main control chip with ADDR1 as starting point The memory space of location；DataSet1 generating process is as follows：

5.1 defined variable i=0；

I-th sensitive spot that the 5.2 pairs of sensitive spots are concentrated, generation KN is centered on sensitive spot, fixed value as variance, meet The test data of normal distribution, the test data of generation is added in DataSet1, and i increases 1；

If 5.3 i<KpNum, turns 5.2；If i >=KpNum, the 6th step is performed；

6th step, the demand model defined according to second step generates IN at random, and (IN is positive integer, IN>KpNum*KN/2) bar Instruction to be tested；For every instruction to be tested, according to the test and excitation template that second step is defined, the test of generation first swashs at random Encourage program；It is serially IN bars IN section the first test and excitation program of instruction generation to be tested, is that every instruction to be tested generates the The process of one test and excitation program is identical, comprises the following steps：

If 6.1 instructions to be tested are instructed for computing class, OpNum operand is randomly choosed first from DataSet1；So Afterwards in instruction previous existence to be tested into instruction is moved, move during instruction act as operand moving corresponding register；Treating The first store instruction is generated after test instruction, the first store instruction act as storing operation result and is to main control chip address The memory space of ADDR4；It is finally the memory space of ADDR2 by the first test and excitation program storage to main control chip address；Turn 6.3；

If 6.2 instructions to be tested are control class instruction, first in instruction previous existence to be tested into the second store instruction, second deposits It is the memory space of ADDR4 that storage instruction is act as current status register value storage to main control chip address；Then to be measured The 3rd store instruction is generated after examination instruction, the 3rd store instruction is act as status register value storage after execution to main control chip Address is the memory space of ADDR4；Finally by the first test and excitation program storage to main control chip address for the storage of ADDR2 is empty Between；Turn 6.3；

6.3ADDR2 increase address bit (address bit=machine work is wide/8, address bit is wide to machine work related, such as 32 One address bit of machine is 4,64 address bits of machine for 8), ADDR4 increases an address bit, and j increases 1, if j< InsNum, represents that the instruction to be tested still has demand model not generate the first test and excitation program, turns the 6th step, if j >= InsNum, represents that all demand models that primary control program has been the instruction to be tested generate the first test and excitation program, if Through being IN bars IN sections of the first test and excitation program of instruction generation to be tested, turn the 7th step, otherwise, turn the 6th step, be next and treat Test instruction the first test and excitation program of generation；

7th step, from control Program Synchronization flag bit SFlag, if SFlag=1, expression is in from control program and waits for detection State, the IN that the 6th step is generated a first test and excitation program is all sent to from control chip address as the storage of ADDR8 is empty Between, turn the 8th step；If SFlag=0, represent from control program and be in busy condition, turn the 7th step；

8th step, MFlag is set to 1, represents that main control chip enters wait state；

9th step, receives IN the second test and excitation program sent from control program, is stored in main control chip address for ADDR3 Memory space；

Tenth step, primary control program is according to the value heavy duty address AD DR2 of RADDR2 and jumps to address AD DR2, and order is performed IN the first test and excitation program of primary control program generation, then branches to address AD DR3, and order is performed from control Program Generating IN the second test and excitation program, the first test and excitation program implementing result record is the memory space of ADDR4 in initial address, Second test and excitation program implementing result record is the memory space of ADDR5 in initial address；

11st step, primary control program detection from control program implementing result Returning mark position ResultFlag, if ResultFlag=1, represents from control program by IN the first test and excitation program performed from control chip and IN second Test and excitation program implementing result returns to main control chip, turns the 12nd step；If ResultFlag=0, represent from control program also IN the first test and excitation program and IN the second test and excitation program implementing result that will not performed from control chip return to master Control chip, turns the 11st step；

12nd step, contrasts main control chip and performs IN the first test and excitation program and IN second respectively from control chip The result of test and excitation program, such as implementing result are different, turn the 13rd step；Otherwise, LoopNum1 increases 1, if LoopNum1< MAXLOOP1, represents that primary control program not yet reaches the predetermined cycle-index of program, turns the 4th step, if LoopNum1 >= MAXLOOP1, represents that primary control program has reached the predetermined cycle-index of program, is returned to debugging main frame and completes signal, turns the tenth Four steps；

13rd step, the first test and excitation program or the second test and excitation program and main control chip that record makes a mistake With the result that the first test and excitation program or the second test and excitation program are performed from control chip, and record content is passed through into JTAG1 It is transmitted to debugging main frame；

14th step, primary control program terminates.

It is compatible chip to be verified from control chip, is connected with debugging main frame and HPI buses from control chip.Lead to from control chip Cross JTAG2 to be connected with debugging main frame, communicated with other resources on development board by HPI buses.Led from debugging from control chip Machine is downloaded and run from control program.

It is from control program circuit：

1. the first step with primary control program is identical, the sensitive point set of definition；Defined respectively from control chip address space with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 are the memory space of initial address, are subsequently being held from control program for depositing The interim data for producing and code during row, because generating multistage the second test and excitation journey in test process from control program Sequence, a piece of memory space will be being taken from control chip, defined RADDR7 and be equal to ADDR7, and the value of RADDR7 is the multistage Second test and excitation program from control chip in store initial address, for carrying out heavy duty to address ADDR7；

2. the second step with primary control program is identical, defines demand model and test and excitation template；

3. generated at random from control program in definition program cyclic variable LoopNum2=0, LoopNum2 controls verification process The circulation pass of test data, (i.e. MAXLOOP2 is equal to define cycle-index MAXLOOP2 predetermined with primary control program identical MAXLOOP1)；Define temporary variable k=0；From control Program Synchronization flag bit SFlag, SFlag is represented from control chip when being 1 for definition The state that main control chip to be received sends the first test and excitation program such as it has been in；Definition has been returned from control program implementing result Flag bit ResultFlag, ResultFlag are represented when being 1 and are tested the first test and excitation program and second from control program Incentive programme implementing result writes back to main control chip memory space；

4. reset and set to 0 from control Program Synchronization flag bit, i.e. SFlag, ResultFlag sets to 0；

5. the 5th step with primary control program is identical, generates the second test data, constitutes the second test data set DataSet2, DataSet2 is stored in the memory space with ADDR6 as initial address from control chip；

6. the instruction template for being defined according to step 2 generates IN at random, and (IN is positive integer, IN>KpNum*KN/2) bar is to be tested Instruction, for every instruction to be tested, the second test and excitation program is generated according to test and excitation template at random；It is serially IN bars IN sections of the second test and excitation program of instruction generation to be tested, is every process of second test and excitation program of instruction generation to be tested It is identical, comprise the following steps：

If 6.1 ' instructions to be tested are instructed for computing class, OpNum operand is randomly choosed first from DataSet2；So Afterwards in instruction previous existence into instruction is moved, move during instruction act as operand moving corresponding register, given birth to after instruction Into the 4th store instruction, the 4th store instruction act as arriving operation result storage from control chip address as the storage of ADDR10 is empty Between；Finally by the second test and excitation program storage to from control chip address for ADDR7 memory space；Turn 6.3 '；

If 6.2 ' instructions to be tested are control class instruction, first in instruction previous existence into the 5th store instruction, the 5th storage refers to It is the memory space of ADDR10 that order act as arriving the storage of current status register value from control chip address；Then it is raw after instruction Into the 6th store instruction, the 6th store instruction act as storing status register value after execution to from control chip address and is The memory space of ADDR10；Finally by the second test and excitation program storage to from control chip address for ADDR7 memory space；Turn 6.3′；

6.3 ' ADDR7 increase an address bit, and ADDR10 increases an address bit, and k increases 1, if k<InsNum, represents described Instruction to be tested still has demand model not generate the second test and excitation program, goes to step 6；If k >=InsNum, represent from control journey Sequence has been that all demand models of the instruction to be tested generate the second test and excitation program, if being the instruction to be tested of IN bars IN sections of the second test and excitation program of generation, goes to step 7；Otherwise, 6 are gone to step, is that next instruction generation second to be tested is tested Incentive programme；

7. put 1 from control Program Synchronization flag bit SFlag, represent from control chip and the main control chip transmission to be received such as be in The state of the first test and excitation program；

8. IN the first test and excitation program that primary control program sends is received, and it is ADDR8 to be stored in from control chip initial address Memory space；

9. primary control program synchronous mark position MFlag is detected, if MFlag=1, i.e. primary control program is waited for, will The memory space that main control chip initial address is ADDR3 is sent to from IN the second test and excitation program of control Program Generating, is turned Step 10；Otherwise, 9 are gone to step；

10., from control program is according to the initial value of RADDR7 heavy duty address ADs DR7 and jumps to address AD DR7, order is performed From IN the second test and excitation program of control Program Generating, address AD DR8 is then branched to, order performs primary control program generation IN the first test and excitation program, the first test and excitation implementing result and the second test and excitation program implementing result are separately recorded in Initial address is the memory space of ADDR9 and ADDR10；

11. first test and excitation implementing result is sent to the memory space that main control chip address is ADDR11, and second surveys Examination incentive programme implementing result is sent to the memory space that main control chip address is ADDR12, and will be from control program implementing result Returning mark position ResultFlag puts 1；

12.LoopNum2 increases 1, if LoopNum2<MAXLOOP2, expression not yet reaches the predetermined circulation of program from control program Number of times, goes to step 4；If LoopNum2 >=MAXLOOP2, expression has reached the predetermined cycle-index of program from control program, from control EP (end of program).

Compatible chip to be verified is carried out towards the microprocessor silicon posteriority card device of compatible design using the present invention The method of functional verification is：

Step one, debugging main frame is led to respectively by CCS IDEs by compiled primary control program and from control program Cross JTAG1 and JTAG2 download to main control chip and from control chip.And start and respectively perform primary control program and from control program；

Step 2, main control chip operation primary control program, while from the operation of control chip from control program, primary control program is responsible for generation Main control chip test and excitation, control main control chip perform test and excitation, compare main control chip and perform test and excitation from control chip Result and treatment are responsible for generating from control chip testing excitation from control program, are controlled from control chip from control chip implementing result mistake Perform test and excitation：

2.1) primary control program and define respective sensitive point set respectively simultaneously from control program, define sensitive spot and concentrate sensitive spot Number is KpNum；Defined respectively in main control chip address space with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 and ADDR12 is the memory space of initial address, for depositing primary control program interim generation during subsequent execution Data and code, define RADDR2 and are equal to ADDR2, for carrying out heavy duty to address ADDR2；Divide from control chip address space The memory space with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 as initial address is not defined, for depositing from control program The interim data for producing and code during subsequent execution, define RADDR7 and are equal to ADDR7, for being carried out to address ADDR7 Heavy duty；

2.2) primary control program and from control program simultaneously define respective demand model and test and excitation template respectively；Master control journey Sequence is identical with the process from control application definition demand model, and treating brake instruction by Object--oriented method carries out abstract building Mould, defines demand model, and process is as follows：Instruction is divided into some fields by the effect according to instruction internal different instruction position, such as Opcode field, operand field, condition perform bit field, parallel bit field etc., and each field is a Prescribed Properties Stochastic variable, constraints defines the ratio of type, span and the random distribution of stochastic variable field；It is different knots Different demand models, including double operand instruction, single-operand instruction and no operand instruction are set up in the instruction of structure type, order The number of instruction operands is that (OpNum of double operand instruction is equal to 2 to OpNum, and the OpNum of single-operand instruction is equal to 1, nothing 0) OpNum of operand instruction is equal to, and (InsNum is positive integer, its value and instruction set for InsNum to make demand model number It is relevant)；Primary control program and from control program simultaneously respectively on the basis of demand model, be the instruction of computing class and control class instruction point Test and excitation template is not set up, and primary control program is identical with the test and excitation template from control program；Computing class instruction testing excited modes Plate includes three parts：Prepare operand：Concurrently OpNum operand is moved into OpNum register, execute instruction, Result back into memory space；Control class instruction testing excitation template includes three parts, stores current status register value, holds Status register value after row instruction, storage execution；According to the Status register for performing the type selecting needs preservation that control class is instructed Device, control class command function includes：Reprogramming execution sequence, change pipeline state, change perform authority and change caching State；

2.3) primary control program defines master control journey in program cyclic variable LoopNum1=0, LoopNum1 control verification process Sequence generates the circulation pass of test data at random, defines the predetermined cycle-index MAXLOOP1 of primary control program, and primary control program definition is faced Variations per hour j=0, defines primary control program synchronous mark position MFlag；Simultaneously from control application definition program cyclic variable LoopNum2= Generate the circulation pass of test data in 0, LoopNum2 control verification process at random from control program, definition is followed from control program is predetermined Ring number of times MAXLOOP2 (MAXLOOP2=MAXLOOP1), from control application definition temporary variable k=0, defines from control Program Synchronization Flag bit SFlag, from control application definition implementing result Returning mark position ResultFlag；

2.4) primary control program reset primary control program synchronous mark position, i.e., MFlag sets to 0；It is same from control program from control Program reset Step flag bit, i.e. SFlag set to 0, and ResultFlag sets to 0；

2.5) primary control program and from control program simultaneously generate the first test data and the second test data, constitute test and excitation Sensitivity volume, method is as follows：Primary control program is identical with the process from control Program Generating test data, using normal distribution random number Generating function generation KN ((KN is positive integer, KN generally takes 100~1000) it is individual centered on sensitive spot, (fixed value can for fixed value To take the arbitrary value in sensitive spot floating point representation in mantissa's excursion) for variance, meet the test data of normal distribution；Normal state Distribution random numbers generating function includes two steps：The first step meets uniform point using random number generator generation in C language built-in function The random number of cloth；Second step uses BoxMuller methods, these equally distributed random numbers is converted to and meets normal distribution Random number；Primary control program sensitive spot concentrates KpNum*KN the first test data that KpNum sensitive spot is generated；From control program Sensitive spot concentrates KpNum*KN the second test data that KpNum sensitive spot is generated；First test of primary control program generation Data constitute the first test data set DataSet1, DataSet1 and are stored in main control chip depositing with ADDR1 as initial address Storage space, the second test data set DataSet2 is constituted from the second test data of control Program Generating, DataSet2 be stored in from Memory space in control chip with ADDR6 as initial address；

2.6) primary control program and from control program simultaneously respectively according to 2.2) definition demand model generate IN bars finger to be tested Order；Primary control program turns 2.6.1), IN the first test and excitation program of generation；Meanwhile, turn 2.6.2 from control program), generation IN the Two test and excitation programs；

2.6.1) primary control program is serially IN bars IN the first test and excitation program of instruction generation to be tested, is every and treats The process all same of instruction the first test and excitation program of generation is surveyed, is comprised the following steps：

2.6.1.1) if instruction to be tested is instructed for computing class, randomly choosed first from test data set DataSet1 OpNum operand；Then in instruction previous existence to be tested into instruction is moved, move instruction and act as operand moving correspondence Register in；The first store instruction is generated after instruction to be tested, the first store instruction act as arriving operation result storage Main control chip address is the memory space of ADDR4；It is finally ADDR2 by the first test and excitation program storage to main control chip address Memory space, turn 2.6.1.3)；

2.6.1.2) if instruction to be tested is control class instruction, first in instruction previous existence to be tested into the second store instruction, It is the memory space of ADDR4 that second store instruction is act as current status register value storage to main control chip address；Then The 3rd store instruction is generated after instruction to be tested, the 3rd store instruction is act as status register value storage after execution to master Control chip address is the memory space of ADDR4；It is finally ADDR2's by the first test and excitation program storage to main control chip address Memory space, turns 2.6.1.3)；

2.6.1.3) ADDR2 increases an address bit, and ADDR4 increases an address bit, and j increases 1, if j<InsNum, represents The instruction to be tested still has demand model not generate the first test and excitation program, and primary control program turns 2.6.1), if j >= InsNum, represents that all demand models that primary control program has been the instruction to be tested generate the first test and excitation program, if Through being IN bars IN sections of the first test and excitation program of instruction generation to be tested, turn 2.7), otherwise, primary control program turns 2.6.1), master control Program is next first test and excitation program of instruction generation to be tested；

2.6.2 it is serially) IN bars IN the second test and excitation program of instruction generation to be tested from control program, is every and treats The process all same of instruction the second test and excitation program of generation is surveyed, is comprised the following steps：

2.6.2.1) if instruction to be tested is instructed for computing class, OpNum operation is randomly choosed first from DataSet2 Number；Then in instruction previous existence to be tested into instruction is moved, move during instruction act as operand moving corresponding register； The 4th store instruction is generated after instruction to be tested, the 4th store instruction act as arriving operation result storage from control chip address It is the memory space of ADDR10；Finally by the second test and excitation program storage to from control chip address for ADDR7 memory space, Turn 2.6.2.3)；

2.6.2.2) if instruction to be tested is control class instruction, first in instruction previous existence to be tested into the 5th store instruction, It is the memory space of ADDR10 that 5th store instruction act as arriving the storage of current status register value from control chip address；Then The 6th store instruction is generated after instruction to be tested, the 6th store instruction act as arriving status register value storage after execution It is the memory space of ADDR10 from control chip address；It is to from control chip address by the second test and excitation program storage finally The memory space of ADDR7, turns 2.6.2.3)；

2.6.2.3) ADDR7 increases an address bit, and ADDR10 increases an address bit, and k increases 1, if k<InsNum, represents The instruction to be tested still has demand model not generate the second test and excitation program, and 2.6.2 is turned from control program), if k >= InsNum, represents from all demand models that control program has been the instruction to be tested and generates the second test and excitation program, if Through being IN bars IN sections of the second test and excitation program of instruction generation to be tested, turn 2.7)；Otherwise, 2.6.2 is turned from control program), under One second test and excitation program of instruction generation to be tested；

2.7) synchronous mark position SFlag is put 1 from control program, represents from control chip and the main control chip to be received such as be in The IN state of the first test and excitation program is sent, is turned 2.8)；Meanwhile, primary control program is detected from control Program Synchronization flag bit SFlag, if SFlag=1, expression is waited for from control program, IN the first test and excitation that primary control program will be generated It is the memory space of ADDR8 that program is all sent to from control chip address, and 2.8) primary control program turns；Otherwise, primary control program turns 2.7)；

2.8) MFlag is put 1 by primary control program, represents that main control chip enters wait state, and 2.9) primary control program turns；While from Control Programmable detection primary control program synchronous mark position MFlag, if MFlag=1, i.e. primary control program is waited for, from control journey 2.9) sequence turns；Otherwise, turn 2.8) from control program；

2.9) IN of generation the second test and excitation program is sent to main control chip initial address for ADDR3 from control program Memory space, while primary control program receives IN the second test and excitation program sent from control program；

2.10) primary control program is according to the initial value of RADDR2 heavy duties address AD DR2 and jumps to address AD DR2, sequentially holds IN the first test and excitation program of row primary control program generation, then branches to address AD DR3, and order is performed from control Program Generating IN the second test and excitation programs, the first test and excitation program implementing result record is in initial address for the storage of ADDR4 is empty Between, the second test and excitation program implementing result record is the memory space of ADDR5 in initial address；Simultaneously from control program according to The initial value of RADDR7 heavy duty address ADs DR7 simultaneously jumps to address AD DR7, and order is performed to be surveyed from IN second of control Program Generating Examination incentive programme, then branches to address AD DR8, and order performs IN the first test and excitation program of primary control program generation, the One test and excitation implementing result and the second test and excitation program implementing result are separately recorded in initial address for ADDR9 and ADDR10 Memory space；

2.11) the first test and excitation implementing result is sent to the storage sky that main control chip address is ADDR11 from control program Between, the second test and excitation program implementing result is sent to the memory space that main control chip address is ADDR12, and will be from control journey Returning mark position ResultFlag puts 1 to sequence implementing result, turns 2.12) from control program；Primary control program is detected from control program simultaneously Implementing result Returning mark position ResultFlag, if ResultFlag=1, represent from control program will from control chip perform IN the first test and excitation program and IN the second test and excitation program implementing result return to main control chip, and primary control program turns 2.12)；If ResultFlag=0, represent from control program also will not perform IN the first test and excitation program and IN from control chip Individual second test and excitation program implementing result returns to main control chip, and 2.11) primary control program turns；

2.12) primary control program contrasts main control chip and performs IN the first test and excitation program and IN respectively from control chip The result of the second test and excitation program, such as implementing result are different, turn 2.13)；Otherwise, LoopNum1 increases 1, LoopNum2 and increases 1, master Control program turns 2.12.1), while turning 2.12.2 from control program)；

2.12.1) primary control program compares the size of LoopNum1 and MAXLOOP1, if LoopNum1<MAXLOOP1, represents Primary control program not yet reaches the predetermined cycle-index of program, and 2.4) primary control program turns；If LoopNum1 >=MAXLOOP1, master is represented Control program has reached the predetermined cycle-index of program, is returned to debugging main frame and completes signal, and 2.14) primary control program turns；

2.12.2 the size of LoopNum2 and MAXLOOP2) is compared from control program, if LoopNum2<MAXLOOP2, represents The predetermined cycle-index of program is not yet reached from control program, is turned 2.4) from control program；If LoopNum2 >=MAXLOOP2, represent from Control program has reached the predetermined cycle-index of program, terminates from control program；

2.13) primary control program record makes a mistake the first test and excitation program or the second test and excitation program and master control Chip and the result of the first test and excitation program or the second test and excitation program is performed from control chip, and record content is passed through JTAG1 is transmitted to debugging main frame；

2.14) terminate primary control program, go to step three；

Step 3, if debugging main frame receives the completion signal that main control chip is passed back by JTAG1, verification process knot Beam；If debugging main frame is received main control chip and is passed back the first test and excitation program or the second test for making a mistake by JTAG1 Incentive programme and main control chip and the result of the first test and excitation program or the second test and excitation program is performed from control chip, adjusted Examination main frame show the first test and excitation program or the second test and excitation program and main control chip that make a mistake and from controlling chip The result of the first test and excitation program or the second test and excitation program is performed, verification process terminates.

Compared with the compatible checking device of function after existing microprocessor silicon, the present invention has advantages below：

1. CCS IDEs are run by debugging main frame, develop primary control program and from control two sets of softwares of program, controlled Main control chip and from control chip behavior, and debugging main frame on show the result, without artificial interference verification process, hardware Platform courses are simple；

2. primary control program and IN the first test and excitation programs and IN the second test and excitation journey are generated simultaneously from control program Sequence, then primary control program IN the first test and excitation programs are sent to from control chip, from control program by IN second test Incentive programme is sent in main control chip；So primary control program and each self-generating IN the first test and excitations are only needed to survey from control program Examination program or the second test and excitation program, but can simultaneously to IN the first test and excitation program and IN the second test and excitation journey Sequence carries out test checking, verifies that the verification efficiency of device is high；

3. by " MS master-slave " dual chip verify device, main control chip and from control chip respectively by run primary control program and From control program, in main control chip and from control chip, oneself generation, testing results are encouraged, and are responsible for master control core by primary control program Piece and from control chip the operation result of test and excitation program is compared, without by debugging main frame be loaded into test and excitation program, Reduce debugging main frame and main control chip and the data transfer time delay between controlling chip, it is to avoid manual compiling test and excitation program Error, verifies that the accuracy and verification efficiency of device are high；

4. by primary control program and from verification process defined in control program to floating-point operation result precision and the degree of accuracy The larger sensitive point set of influence, defines demand model and test and excitation template, uses the random device of belt restraining to generate with sensitivity Centered on point, fixed value be variance, meet the test data of normal distribution, and based on test data according to demand model and test Excitation template generation test and excitation program, it is to avoid the mistake that may be introduced during manual compiling test and excitation, verifies the survey of device Examination excitation coverage rate and reliability are high；

5. when by controlling test and excitation storage location and control program pointer to redirect in primary control program and from control program Machine, can to greatest extent ensure that instruction and data is all in the local storage space of chip during chip configuration processor, reduce master Control chip and the data transfer from control chip chamber, effectively alleviate main control chip and the bottleneck problem from control inter-chip bandwidth, after silicon Verify that the verification efficiency of device is high.

Compared with function compatibility method after existing microprocessor silicon, the present invention has advantages below：

1. CCS IDEs are run by debugging main frame, develop primary control program and from control two sets of softwares of program, controlled Main control chip and from control chip behavior, by primary control program to main control chip and from control chip test and excitation implementing result carry out Check, and the result is shown on debugging main frame, compared without manual compiling test and excitation program, result, it is to avoid artificial The error that operation may be introduced, verification method accuracy is high；

2. primary control program and IN the first test and excitation programs and IN the second test and excitation journey are generated simultaneously from control program Sequence, then primary control program IN the first test and excitation programs are sent to from control chip, from control program by IN second test Incentive programme is sent in main control chip；So primary control program and each self-generating IN the first test and excitations are only needed to survey from control program Examination program or the second test and excitation program, but can simultaneously to IN the first test and excitation program and IN the second test and excitation journey Sequence carries out test checking, verification method efficiency high；

3. by primary control program and from verification process defined in control program to floating-point operation result precision and the degree of accuracy The larger sensitive point set of influence, defines demand model and test and excitation template, uses the random device of belt restraining to generate with sensitivity Centered on point, fixed value be variance, meet the test data of normal distribution, and based on test data according to demand model and test Excitation template generation test and excitation program, it is to avoid the mistake that may be introduced during manual compiling test and excitation, improves authentication The test and excitation coverage rate and reliability of method；

4. when by controlling test and excitation storage location and control program pointer to redirect in primary control program and from control program Machine, can to greatest extent ensure that instruction and data is all in the local storage space of chip during chip configuration processor, reduce master Control chip and the data transfer from control chip chamber, effectively alleviate main control chip and the bottleneck problem from control inter-chip bandwidth, improve The verification efficiency of verification method after silicon.

Brief description of the drawings

Fig. 1 is microprocessor silicon posteriority card device structure chart of the present invention towards compatible design.

Fig. 2 be primary control program of the present invention and from control program execution flow figure.

Fig. 3 is the present invention towards verifying method flow diagram after the microprocessor silicon of compatible design.

Fig. 4 is that computing class is instructed and control class instruction testing excitation template.

Fig. 5 is main control chip and flows schematic diagram from control chip-stored spatial data.

Specific embodiment

The present invention is described in further details below with reference to Figure of description and specific embodiment.

Fig. 1 is " MS master-slave " dual chip checking structure drawing of device of the invention." MS master-slave " dual chip checking device in the present invention It is main to include debugging main frame, development board, main control chip and from control chip.

Debugging main frame is connected with main control chip, from control chip.Debugging main frame is connected with main control chip by JTAG1, and from Control chip is connected by JTAG2.Debugging main frame on run master control/from control chip development environment, editor, compiling and be loaded into master control core Piece and the executable program from control chip, in main control chip and from the data for controlling real-time reception chip return during chip runs, and The execution state of control chip.

Development board has been equipped with the general development board of multiple interfaces and bus, can dispose multiple processor chips, chip Between by data/address bus connect, each chip possess and debug main-machine communication stand-alone interface.Main control chip, from control chip be inserted into out On hair plate.

Main control chip is the chip or objective chip for having passed through checking, and main control chip is connected with debugging main frame and HPI buses. Main control chip is connected by JTAG1 with debugging main frame, and other resources on development board are communicated and accessed by HPI buses.It is main Control chip downloads primary control program from debugging main frame, runs primary control program, and primary control program generates the first test and excitation program, control master Control chip perform test and excitation, compare main control chip with from control chip perform test and excitation result carry out result inspection, treatment from Control chip implementing result mistake.And inspection result or mistake are transmitted to debugging main frame by JTAG1.With reference to Fig. 2, primary control program stream Cheng Wei：

S101 defines the sensitive point set in verification process, and sensitive point set is made up of sensitive spot, and sensitive spot is in floating-point operation Larger particular values, including positive negative zero, positive minus infinity and invalid number are influenceed on operation result precision and the degree of accuracy；Make quick It is KpNum that sense point concentrates sensitive spot number (KpNum is positive integer)；Defined respectively in main control chip address space with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 and ADDR12 are the memory space of initial address, are existed for depositing primary control program The interim data for producing and code during subsequent execution, because primary control program generates multistage first in test process, test swashs Program is encouraged, a piece of memory space will be taken on main control chip, defined RADDR2 and be equal to ADDR2, the value of RADDR2 is described The initial address that multistage the first test and excitation program is stored in main control chip；

S102 defines demand model and test and excitation template；Brake instruction is treated by Object--oriented method to be taken out As modeling, demand model is defined, process is as follows：Instruction is divided into some words by the effect according to instruction internal different instruction position Section, such as opcode field, operand field, condition perform bit field, parallel bit field, and each field is a Constrained The stochastic variable of condition, constraints defines the ratio of type, span and the random distribution of stochastic variable field；For not Different demand models are set up with the instruction of structure type, including double operand instruction, single-operand instruction and no-operand refer to Order, (OpNum of double operand instruction is equal to 2, and the OpNum of single-operand instruction is equal to for OpNum to make the number of instruction operands 1,0) OpNum of no operand instruction is equal to, and it is InsNum to make demand model number (value of InsNum is relevant with instruction set)； It is that test and excitation template is set up in the instruction of computing class and control class instruction respectively on the basis of demand model；The instruction of computing class is surveyed Examination excitation template includes three parts：Concurrently OpNum operand is moved into OpNum register, execute instruction, will knot Fruit writes back to memory space；Control class instruction testing excitation template includes three parts：Storage current status register value, execution refer to Make, store status register value after execution；According to the status register for performing the type selecting needs preservation that control class is instructed, control Class command function processed includes：Reprogramming execution sequence, change pipeline state, change perform authority and change buffer status；

S103 defines primary control program cyclic variable LoopNum1=0, in LoopNum1 control verification process primary control program with The circulation pass of machine generation test data, the predetermined cycle-index MAXLOOP1 of definition program (MAXLOOP1 is positive integer, MAXLOOP1 takes the empirical value that checking can be made to reach target coverage rate, usual coverage rate target be set to computational space 1%), Temporary variable j=0 is defined, primary control program synchronous mark position MFlag, MFlag is defined and is represented that main control chip has been in when being 1 The state that the second test and excitation program is sent from control chip to be received；

S104 reset primary control programs synchronous mark position, i.e., MFlag sets to 0；

S105 generates the first test data, constitutes the first test data set DataSet1, and method is：Primary control program is to sensitivity Each sensitive spot that point is concentrated, using normal distribution random number generating function generation KN, (KN is positive integer, and KN generally takes 100 ~1000) it is individual centered on sensitive spot, (fixed value can take appointing in mantissa's excursion in sensitive spot floating point representation to fixed value Meaning value) it is variance, meets the first test data of normal distribution；Normal distribution random number generating function includes two steps：The first step Meet equally distributed random number using random number generator generation in C language built-in function；Second step uses classics These equally distributed random numbers are converted to BoxMuller algorithms the random number for meeting normal distribution；Sensitive spot concentrates KpNum KpNum*KN the first test data that individual sensitive spot is generated constitutes the first test data set DataSet1, DataSet1 storage Memory space in main control chip with ADDR1 as initial address；

S106 generates IN (IN at random according to the demand model that S102 is defined>KpNum*KN/2) bar instruction to be tested；For Every instruction to be tested, the test and excitation template defined according to S102 generates the first test and excitation program at random；It is serially IN Bar IN sections of the first test and excitation program of instruction generation to be tested, is every mistake of first test and excitation program of instruction generation to be tested Cheng Xiangtong, comprises the following steps：

If S106.1 instructions to be tested are instructed for computing class, OpNum operand is randomly choosed first from DataSet1； Then in instruction previous existence to be tested into instruction is moved, move during instruction act as operand moving corresponding register； The first store instruction is generated after instruction to be tested, the first store instruction act as storing operation result and is to main control chip address The memory space of ADDR4；It is finally the memory space of ADDR2 by the first test and excitation program storage to main control chip address；Turn S106.3；

If S106.2 instructions to be tested are control class instruction, first in instruction previous existence to be tested into the second store instruction, the It is the memory space of ADDR4 that two store instructions are act as current status register value storage to main control chip address；Then exist The 3rd store instruction is generated after instruction to be tested, the 3rd store instruction is act as status register value storage after execution to master control Chip address is the memory space of ADDR4；It is finally depositing for ADDR2 by the first test and excitation program storage to main control chip address Storage space；Turn S106.3；

S106.3 ADDR2 increase an address bit, and (address bit is wide to machine work related, such as 32 addresses of machine Position is 4,64 address bits of machine for 8), ADDR4 increases an address bit, and j increases 1, if j<InsNum, represent described in treat Test instruction still has demand model not generate the first test and excitation program, turns S106, if j >=InsNum, represents primary control program All demand models first test and excitation program of generation of the instruction to be tested has been it, if being the instruction life to be tested of IN bars Into IN sections of the first test and excitation program, turn S107, otherwise, turn S106, be next first test and excitation of instruction generation to be tested Program；

S107 detections if SFlag=1, i.e., are waited for from control Program Synchronization flag bit SFlag from control program, It is the memory space of ADDR8 that IN the first test and excitation program that S106 is generated is sent to from control chip address, turns S108；Such as Fruit SFlag=0, represents from control program and is in busy condition, turns S107；

S108 MFlag are set to 1, represent that main control chip enters wait state；

S109 receives IN the second test and excitation program sent from control program, and it is ADDR3's to be stored in main control chip address Memory space；

S110 primary control programs are according to the value heavy duty address AD DR2 of RADDR2 and jump to address AD DR2, and order performs master control IN the first test and excitation program of Program Generating, then branches to address AD DR3, and order performs IN from control Program Generating Second test and excitation program, the first test and excitation program implementing result record is the memory space of ADDR4, second in initial address Test and excitation program implementing result record is the memory space of ADDR5 in initial address；

The detection of S111 primary control programs from control program implementing result Returning mark position ResultFlag, if ResultFlag= 1, represent IN the first test and excitation program and IN the second test and excitation program that will have been performed from control chip from control program Implementing result returns to main control chip, turns S112；If ResultFlag=0, representing will not perform also from control program from control chip IN the first test and excitation programs and IN the second test and excitation program implementing result return to main control chip, turn S111；

S112 contrasts main control chip and performs IN the first test and excitation program and IN second test respectively from control chip The result of incentive programme, such as implementing result are different, turn S113；Otherwise, LoopNum1 increases 1, if LoopNum1<MAXLOOP1, turns S104, if LoopNum1 >=MAXLOOP1, returns to debugging main frame and completes signal, turns S114；

S113 the first test and excitation programs for making a mistake of record or the second test and excitation program and main control chip and from Control chip performs the result of the first test and excitation program or the second test and excitation program, and record content is transmitted to by JTAG1 Debugging main frame；

S114 terminates primary control program；

It is compatible chip to be verified from control chip, is connected with debugging main frame and HPI buses from control chip.Lead to from control chip Cross JTAG2 to be connected with debugging main frame, communicated with other resources on development board by HPI buses.Led from debugging from control chip Machine is downloaded from control program, and operation is responsible for generation from control program test excitation from control program --- the second test and excitation program, operation First test and excitation program and the second test and excitation program.With reference to Fig. 2, it is from control program circuit：

S101 ' is identical with the S101 of primary control program, the sensitive point set of definition；Defined respectively from control chip address space with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 are the memory space of initial address, are subsequently being held from control program for depositing The interim data for producing and code during row, because primary control program generates multistage the second test and excitation journey in test process Sequence, will take a piece of memory space on main control chip, define RADDR7 and be equal to ADDR7, and the value of RADDR7 is the multistage Second test and excitation program from control chip in store initial address, for carrying out heavy duty to address ADDR7；

S102 ' is identical with the S102 of primary control program, defines demand model and test and excitation template；

S103 ' gives birth at random in defining program cyclic variable LoopNum2=0, LoopNum2 control verification process from control program Into the circulation pass of test data, (i.e. MAXLOOP2 is equal to define cycle-index MAXLOOP2 predetermined with primary control program identical MAXLOOP1)；Define temporary variable k=0；From control Program Synchronization flag bit SFlag, SFlag is represented from control chip when being 1 for definition The state that main control chip to be received sends the first test and excitation program such as it has been in；Definition has been returned from control program implementing result Flag bit ResultFlag, ResultFlag are represented when being 1 and are tested the first test and excitation program and second from control program Incentive programme implementing result writes back to main control chip memory space；

S104 ' resets and is set to 0 from control Program Synchronization flag bit, i.e. SFlag, and ResultFlag sets to 0；

S105 ' is identical with the S105 of primary control program, generates the second test data, constitutes the second test data set DataSet2, DataSet2 are stored in the memory space with ADDR6 as initial address from control chip；

S106 ' generates IN (IN at random according to the instruction template that S102 ' is defined>KpNum*KN/2) bar instruction to be tested, right In every instruction to be tested, the second test and excitation program is generated according to test and excitation template at random；Serially for IN bars are to be tested Instruction IN sections of the second test and excitation program of generation, is that the process of every second test and excitation program of instruction generation to be tested is identical, Comprise the following steps：

If S106.1 ' instructions to be tested are instructed for computing class, randomly choosed first from test data set DataSet2 OpNum operand；Then moved instruction and act as operand moving corresponding deposit into instruction is moved in instruction previous existence In device, the 4th store instruction is generated after instruction, the 4th store instruction act as arriving operation result storage from control chip address It is the memory space of ADDR10；Finally by the second test and excitation program storage to from control chip address for ADDR7 memory space； Turn S106.3 '；

If S106.2 ' instructions to be tested are control class instruction, first in instruction previous existence into the 5th store instruction, the 5th storage It is the memory space of ADDR10 that instruction act as arriving the storage of current status register value from control chip address；Then after instruction The 6th store instruction is generated, the 6th store instruction act as storing status register value after execution to from control chip address and is The memory space of ADDR10；Finally by the second test and excitation program storage to from control chip address for ADDR7 memory space；Turn S106.3′；

S106.3 ' ADDR7 increase an address bit, and ADDR10 increases an address bit, and k increases 1, if k<InsNum, represents It is described it is to be tested instruction still there is demand model not generate the second test and excitation program, turn S106 ', if k >=InsNum, represent from Control program has been that all demand models of the instruction to be tested generate the second test and excitation program, if being that IN bars are to be tested Instruction IN sections of the second test and excitation program of generation, turns S107 '；Otherwise, turn S106 ', be next instruction generation second to be tested Test and excitation program；

S107 ' puts 1 from control Program Synchronization flag bit SFlag, represents from control chip and the main control chip to be received such as has been in Send the state of the first test and excitation program；

S108 ' receives IN the first test and excitation programs that primary control program sends, and is stored in from control chip initial address and is The memory space of ADDR8；

S109 ' detection primary control program synchronous mark position MFlag, if MFlag=1, i.e. primary control program is waited for, The memory space that main control chip initial address is ADDR3 will be sent to from IN the second test and excitation program of control Program Generating, Turn S110 '；Otherwise, S109 ' is turned；

S110 ' sequentially holds from control program is according to the initial value of RADDR7 heavy duty address ADs DR7 and jumps to address AD DR7 Row then branches to address AD DR8 from IN the second test and excitation program of control Program Generating, and order performs primary control program generation IN the first test and excitation programs, the first test and excitation implementing result and the second test and excitation program implementing result are recorded respectively It is the memory space of ADDR9 and ADDR10 in initial address；

First test and excitation implementing result is sent to S111 ' memory space that main control chip address is ADDR11, second Test and excitation program implementing result is sent to the memory space that main control chip address is ADDR12, and will be from control program implementing result Returning mark position ResultFlag puts 1；

S112 ' LoopNum2 increase 1, if LoopNum2<MAXLOOP2, expression not yet reaches that program is predetermined to be followed from control program Ring number of times, turns S104 '；If LoopNum2 >=MAXLOOP2, expression has reached the predetermined cycle-index of program from control program, from Control EP (end of program).

Fig. 3 is the present invention towards verifying method flow diagram after the microprocessor silicon of compatible design.

S301 debugging main frames are passed through respectively by CCS IDEs by compiled primary control program and from control program JTAG1 and JTAG2 download to main control chip and from control chip；And start and respectively perform primary control program and from control program；

S302 main control chips run primary control program, while from the operation of control chip from control program, primary control program is responsible for generation master Control chip testing excitation, control main control chip perform test and excitation, comparison main control chip and perform test and excitation knot with from control chip Fruit and treatment are responsible for generating from control chip testing excitation from control program, control to be held from control chip from control chip implementing result mistake Row test and excitation：

S302.1 primary control programs and define respective sensitive point set respectively simultaneously from control program, define sensitive spot and concentrate sensitive Point number is KpNum；Defined respectively in main control chip address space with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 and ADDR12 is the memory space of initial address, for depositing primary control program interim generation during subsequent execution Data and code, define RADDR2 and are equal to ADDR2, for carrying out heavy duty to address ADDR2；Divide from control chip address space The memory space with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 as initial address is not defined, for depositing from control program The interim data for producing and code during subsequent execution, define RADDR7 and are equal to ADDR7, for being carried out to address ADDR7 Heavy duty；

S302.2 primary control programs and from control program simultaneously define respective demand model and test and excitation template respectively；Master control Program with from control application definition demand model process it is identical, by Object--oriented method treat brake instruct carry out it is abstract Modeling, defines demand model, and process is as follows：Instruction is divided into some fields by the effect according to instruction internal different instruction position, Such as opcode field, operand field, condition perform bit field, parallel bit field, and each field is a Constrained bar The stochastic variable of part, constraints defines the ratio of type, span and the random distribution of stochastic variable field；It is difference Different demand models, including double operand instruction, single-operand instruction and no operand instruction are set up in the instruction of structure type, Make the number of instruction operands for OpNum (OpNum of double operand instruction is equal to 2, and the OpNum of single-operand instruction is equal to 1, 0) OpNum of no operand instruction is equal to, and it is InsNum to make demand model number (value of InsNum is relevant with instruction set)；It is main Control program and from control program simultaneously respectively on the basis of demand model, be that the instruction of computing class and control class instruction are set up survey respectively Examination excitation template, primary control program is identical with the test and excitation template from control program；Computing class instruction testing excitation template includes three Part：Prepare operand：Concurrently OpNum operand is moved into OpNum register, execute instruction, is write result Return to memory space；Control class instruction testing excitation template includes three parts, storage current status register value, execute instruction, Status register value after storage execution；According to the status register for performing the type selecting needs preservation that control class is instructed, control Class command function includes：Reprogramming execution sequence, change pipeline state, change perform authority and change buffer status；

S302.3 primary control programs define master control in program cyclic variable LoopNum1=0, LoopNum1 control verification process Program generates the circulation pass of test data at random, defines the predetermined cycle-index MAXLOOP1 of primary control program, primary control program definition Temporary variable j=0, defines primary control program synchronous mark position MFlag；Simultaneously from control application definition program cyclic variable LoopNum2 Generate the circulation pass of test data in=0, LoopNum2 control verification process at random from control program, definition makes a reservation for from control program Cycle-index MAXLOOP2 (MAXLOOP2=MAXLOOP1), from control application definition temporary variable k=0, definition is same from control program Step flag bit SFlag, from control application definition implementing result Returning mark position ResultFlag；

S302.4 primary control program reset primary control programs synchronous mark position, i.e., MFlag sets to 0；From control Program reset from control program Synchronous mark position, i.e., SFlag sets to 0, and ResultFlag sets to 0；

S302.5 primary control programs and from control program simultaneously generate the first test data and the second test data, constitute test swash Sensitivity volume is encouraged, method is as follows：Primary control program is identical with the process from control Program Generating test data, random using normal distribution Number generating functions generate KN (KN generally takes 100~1000) it is individual centered on sensitive spot, (fixed value can take sensitive spot to fixed value Arbitrary value in floating point representation in mantissa's excursion) it is variance, meets the test data of normal distribution；Normal distribution random number Generating function includes two steps：The first step meets equally distributed random number using random number generator generation in C language built-in function； Second step uses BoxMuller methods, and these equally distributed random numbers are converted to the random number for meeting normal distribution；Master control Program sensitive spot concentrates KpNum*KN the first test data that KpNum sensitive spot is generated；Concentrated from control program sensitive spot KpNum*KN the second test data that KpNum sensitive spot is generated；First test data of primary control program generation constitutes the One test data set DataSet1, DataSet1 is stored in main control chip the memory space with ADDR1 as initial address, from control Second test data of Program Generating constitutes the second test data set DataSet2, DataSet2 be stored in from control chip with ADDR6 is the memory space of initial address；

It is to be measured that S302.6 primary control programs and the demand model defined according to S302.2 respectively simultaneously from control program generate IN bars Examination instruction；Primary control program turns S302.6.1, IN the first test and excitation program of generation；Meanwhile, turn S302.6.2 from control program, it is raw Into IN the second test and excitation program；

S302.6.1 primary control programs are serially IN bars IN the first test and excitation program of instruction generation to be tested, are every The method all same of first test and excitation program of instruction generation to be measured, process is as follows：

If S302.6.1.1 instructions to be tested are instructed for computing class, randomly choosed first from test data set DataSet1 OpNum operand；Then in instruction previous existence to be tested into instruction is moved, move instruction and act as operand moving correspondence Register in；The first store instruction is generated after instruction to be tested, the first store instruction act as arriving operation result storage Main control chip address is the memory space of ADDR4；It is finally ADDR2 by the first test and excitation program storage to main control chip address Memory space, turn S302.6.1.3；

If S302.6.1.2 instructions to be tested are control class instruction, referred into the second storage in instruction previous existence to be tested first Order, it is the memory space of ADDR4 that the second store instruction is act as current status register value storage to main control chip address；So The 3rd store instruction is generated after instruction to be tested afterwards, the 3rd store instruction act as arriving status register value storage after execution Main control chip address is the memory space of ADDR4；It is finally ADDR2 by the first test and excitation program storage to main control chip address Memory space, turn S302.6.1.3；

S302.6.1.3 ADDR2 increase an address bit, and ADDR4 increases an address bit, and j increases 1, if j<InsNum, table Show that the instruction to be tested still has demand model not generate the first test and excitation program, primary control program turns S302.6.1, if j >= InsNum, represents that all demand models that primary control program has been the instruction to be tested generate the first test and excitation program, if Through being that the instruction to be tested of IN bars generates IN sections of the first test and excitation program, primary control program turns S302.7, and otherwise, primary control program turns S302.6.1), primary control program is next first test and excitation program of instruction generation to be tested；

S302.6.2 is serially IN bars IN the second test and excitation program of instruction generation to be tested from control program, is every The process all same of second test and excitation program of instruction generation to be measured, comprises the following steps：

If S302.6.2.1 instructions to be tested are instructed for computing class, OpNum behaviour is randomly choosed first from DataSet2 Count；Then moved instruction and act as operand moving corresponding register into instruction is moved in instruction previous existence to be tested In；The 4th store instruction is generated after instruction to be tested, the 4th store instruction act as arriving operation result storage from control chip Address is the memory space of ADDR10；Finally by the second test and excitation program storage to from control chip address for ADDR7 storage Space, turns S302.6.2.3；

If S302.6.2.2 instructions to be tested are control class instruction, referred into the 5th storage in instruction previous existence to be tested first Order, it is the memory space of ADDR10 that the 5th store instruction act as arriving the storage of current status register value from control chip address； Then the 6th store instruction is generated after instruction to be tested, the 6th store instruction act as storing status register value after execution To from control chip address for ADDR10 memory space；It is to from control chip address by the second test and excitation program storage finally The memory space of ADDR7, turns S302.6.2.3；

S302.6.2.3 ADDR7 increase an address bit, and ADDR10 increases an address bit, and k increases 1, if k<InsNum, Represent that the instruction to be tested still has demand model not generate the second test and excitation program, turn S302.6.2 from control program, if k >=InsNum, represents from all demand models that control program has been the instruction to be tested and generates the second test and excitation program, if It has been IN bars IN sections of the second test and excitation program of instruction generation to be tested, S302.7 has been turned from control program；Otherwise, turn from control program S302.6.2, is next second test and excitation program of instruction generation to be tested；

Synchronous mark position SFlag is put 1 by S302.7 from control program, is represented from control chip and the master control core to be received such as has been in Piece sends the IN state of the first test and excitation program, turns S302.8；Meanwhile, primary control program is detected from control Program Synchronization flag bit SFlag, if SFlag=1, expression is waited for from control program, IN the first test and excitation that primary control program will be generated It is the memory space of ADDR8 that program is all sent to from control chip address, turns S302.8；Otherwise, S302.7 is turned；

MFlag is put 1 by S302.8 primary control programs, represents that main control chip enters wait state, and primary control program turns S302.9；Together When from control Programmable detection primary control program synchronous mark position MFlag, if MFlag=1, i.e. primary control program is waited for, from Control program turns S302.9；Otherwise, S302.8 is turned from control program；

The IN of generation the second test and excitation program is sent to main control chip initial address by S302.9 from control program The memory space of ADDR3, while primary control program receives IN the second test and excitation program sent from control program；

S302.10 primary control programs are according to the initial value of RADDR2 heavy duties address AD DR2 and jump to address AD DR2, order IN the first test and excitation program of primary control program generation is performed, address AD DR3 is then branched to, order is performed from control program life Into IN the second test and excitation programs, the first test and excitation program implementing result record is the storage of ADDR4 in initial address Space, the second test and excitation program implementing result record is the memory space of ADDR5 in initial address；Simultaneously from control program according to The initial value of RADDR7 heavy duty address ADs DR7 simultaneously jumps to address AD DR7, and order is performed to be surveyed from IN second of control Program Generating Examination incentive programme, then branches to address AD DR8, and order performs IN the first test and excitation program of primary control program generation, the One test and excitation implementing result and the second test and excitation program implementing result are separately recorded in initial address for ADDR9 and ADDR10 Memory space；

First test and excitation implementing result is sent to the storage that main control chip address is ADDR11 by S302.11 from control program Space, the memory space that main control chip address is ADDR12 is sent to by the second test and excitation program implementing result, and will be from control Returning mark position ResultFlag puts 1 to program implementing result, and S302.12 is turned from control program；Primary control program is detected from control simultaneously Program implementing result Returning mark position ResultFlag, if ResultFlag=1, represent from control program will from control chip Perform IN the first test and excitation program and IN the second test and excitation program implementing result returns to main control chip, primary control program Turn S302.12；If ResultFlag=0, represent from control program also will not perform IN the first test and excitation program from control chip Main control chip is returned to IN the second test and excitation program implementing result, primary control program turns S302.11；

S302.12 primary control programs contrast main control chip and perform IN the first test and excitation program and IN respectively from control chip The result of individual second test and excitation program, such as implementing result are different, turn S302.13；Otherwise, LoopNum1 increases 1, LoopNum2 and increases 1, primary control program turns S302.12.1, while turning S302.12.2 from control program；

S302.12.1 primary control programs compare the size of LoopNum1 and MAXLOOP1, if LoopNum1<MAXLOOP1, it is main Control program turns S302.4；If LoopNum1 >=MAXLOOP1, primary control program is returned to debugging main frame and completes signal, and primary control program turns S302.14；

S302.12.2 compares the size of LoopNum2 and MAXLOOP2 from control program, if LoopNum2<MAXLOOP2, from Control program turns S302.4；If LoopNum2 >=MAXLOOP2, terminate from control program；

The first test and excitation program or the second test and excitation program and master that S302.13 primary control programs record makes a mistake Control chip and the result of the first test and excitation program or the second test and excitation program is performed from control chip, and record content is passed through JTAG1 is transmitted to debugging main frame；

S302.14 terminates primary control program, turns S303；

If S303 debugging main frames receive the completion signal that primary control program is passed back by JTAG1, verification process terminates；Such as Fruit debugging main frame is received primary control program and is passed back the first test and excitation program or the second test and excitation journey for making a mistake by JTAG1 Sequence and main control chip and the result of the first test and excitation program or the second test and excitation program is performed from control chip, debug main frame The first test and excitation program for making a mistake of display or the second test and excitation program and main control chip and perform the from control chip The result of one test and excitation program or the second test and excitation program, verification process terminates.

Fig. 4 is the test and excitation generation template of the instruction of computing class and control class instruction in the present invention.Computing class instruction testing Excitation template includes three parts：Concurrently OpNum operand is moved into OpNum register, execute instruction, by result Write back to memory space.Control class instruction testing excitation template includes three parts, and storage current status register value, execution refer to Make, store status register value after execution.According to the status register for performing the type selecting needs preservation that control class is instructed, control Class command function processed includes：Reprogramming execution sequence, change pipeline state, change perform authority and change buffer status.

Fig. 5 is main control chip and flows schematic diagram from control chip-stored spatial data.Main control chip and from control chip pass through HPI buses carry out data transfer, and message transmission rate easily turns into bottleneck, therefore the data storage that can use program as far as possible exists In the address space of chip oneself.Defined respectively in main control chip address space with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 and ADDR12 are the memory space of initial address, interim during subsequent execution for depositing primary control program The data and code of generation.Being defined respectively from control chip address space with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 is the memory space of initial address, for depositing the data and generation that are produced during subsequent execution from control program temporarily Code.Primary control program generates the first test data and the first test and excitation program in the process of implementation, is respectively stored in main control chip Initial address is the memory space of ADDR1 and ADDR2.The second test data and second is generated in the process of implementation from control program to survey Examination incentive programme, it is the memory space of ADDR6 and ADDR7 to be respectively stored in from control chip initial address.Primary control program is by first Test and excitation program is moved to being the memory space of ADDR8 from control chip initial address by HPI data/address bus, is led to from control program It is the memory space of ADDR3 to cross HPI data/address bus and move to main control chip initial address the second test and excitation program.Master control journey After sequence has performed the first test and excitation program and the second test and excitation program, the first test and excitation program implementing result record is existed Main control chip initial address is the memory space of ADDR4, and the second test and excitation program implementing result record is in main control chip starting Address is the memory space of ADDR5.After having performed the first test and excitation program and the second test and excitation program from control program, by the It is ADDR9 that one test and excitation implementing result and the second test and excitation program implementing result are separately recorded in from control chip initial address With the memory space of ADDR10, and implementing result is moved to main control chip initial address as the storage of ADDR11 and ADDR12 is empty Between.So, when can ensure configuration processor to greatest extent, instruction and data is all in the local storage space of chip.

When running primary control program on main control chip, primary control program generates the first test and excitation program storage ADDR2's Memory space, it is the memory space of ADDR3 to move to main control chip initial address the second test and excitation program from control program, main Control program is according to the initial value of RADDR2 heavy duties address AD DR2 and jumps to address AD DR2, and order performs primary control program generation IN the first test and excitation program, then branches to address AD DR3, and order is performed and swashed from IN second test of control Program Generating Program is encouraged, the first test and excitation program implementing result record is the memory space of ADDR4, the second test and excitation journey in initial address Sequence implementing result record is the memory space of ADDR5 in initial address.The first test and excitation is held by HPI buses from control program Row result is sent to the memory space that main control chip address is ADDR11, and the second test and excitation program implementing result is sent into master Control chip address is the memory space of ADDR12.Primary control program contrasts main control chip and performs IN first respectively from control chip and surveys Examination incentive programme and the IN result of the second test and excitation program, implementing result compare.

When being run from control chip from control program, from control Program Generating the second test and excitation program storage ADDR7's Memory space, primary control program moves to being the memory space of ADDR8 from control chip initial address the first test and excitation program, from Control program is according to the initial value of RADDR7 heavy duties address AD DR7 and jumps to address AD DR7, and order is performed from control Program Generating IN the second test and excitation program, then branches to address AD DR8, and IN first test that order performs primary control program generation swashs Program is encouraged, the first test and excitation program implementing result and the second test and excitation program implementing result are separately recorded in initial address and are The memory space of ADDR9 and ADDR10, is then sent to main control chip ground by HPI buses by the first test and excitation implementing result Location is the memory space of ADDR11, and the second test and excitation program implementing result is sent into main control chip address depositing for ADDR12 Storage space.

Claims (7)

1. a kind of microprocessor silicon posteriority card device towards compatible design, towards the microprocessor silicon of compatible design after verify dress Put by debugging main frame, development board, main control chip and from control chip constitute：

Debugging main frame is connected with main control chip, from control chip；Debugging main frame and main control chip pass through the first joint test working group JTAG1 is connected, and is connected by the second joint test working group JTAG2 with from control chip；Have on debugging main frame and opened using CCS is integrated Send out two sets of softwares of environment exploitation：Primary control program and from control program, primary control program is responsible for generation main control chip test and excitation, control Main control chip processed performs test and excitation, comparison main control chip and is held from control chip with from control chip execution test and excitation result and treatment The software of row result mistake；Generation is responsible for from control program perform test and excitation from control chip from control chip testing excitation, control Software；

Development board has been equipped with the general development board of multiple interfaces and bus, can dispose multiple processor chips, chip chamber by Data/address bus is connected, and each chip possesses the stand-alone interface with debugging main-machine communication；Main control chip, from control chip be inserted into development board On；

Main control chip is the chip or objective chip for having passed through checking, and main control chip is connected with debugging main frame and HPI buses；Master control Chip is connected by JTAG1 with debugging main frame, and other resources on development board are communicated and accessed by HPI buses；Master control core Piece downloads primary control program from debugging main frame, runs primary control program, is responsible for generation main control chip test and excitation, control main control chip and holds Row test and excitation, compare main control chip with from control chip perform test and excitation result and treatment from control chip implementing result mistake, Inspection result is transmitted to debugging main frame again by JTAG1；

It is compatible chip to be verified from control chip, is connected with debugging main frame and HPI buses from control chip；Pass through from control chip JTAG2 is connected with debugging main frame, and other resources on development board are communicated and accessed by HPI buses；From control chip from debugging Main frame is downloaded from control program, and operation is responsible for excitation generation, excitation operation from control program；

It is characterized in that the primary control program flow is：

The first step, defines the sensitive point set in verification process, and sensitive point set is made up of sensitive spot, and sensitive spot is right in floating-point operation Operation result precision and the degree of accuracy influence larger particular values, including positive negative zero, positive minus infinity and invalid number；Order is sensitive It is KpNum that point concentrates sensitive spot number, and KpNum is positive integer；Defined respectively in main control chip address space with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 and ADDR12 are the memory space of initial address, define RADDR2 and are equal to The value of ADDR2, RADDR2 is the initial address that multistage the first test and excitation program is stored in main control chip；

Second step, defines demand model and test and excitation template；

3rd step, defines primary control program cyclic variable LoopNum1=0, defines the predetermined cycle-index MAXLOOP1 of program, MAXLOOP1 is positive integer, defines temporary variable j=0, defines primary control program synchronous mark position MFlag, and MFlag is represented when being 1 Main control chip such as has been at the state that the second test and excitation program is sent from control chip to be received；

4th step, reset primary control program synchronous mark position, i.e., MFlag sets to 0；

5th step, generates the first test data, constitutes the first test data set DataSet1, and method is：Primary control program is to sensitivity Each sensitive spot that point is concentrated, it is individual centered on sensitive spot, fixed value using normal distribution random number generating function generation KN For variance, meet the first test data of normal distribution, KN is positive integer；Sensitive spot concentrates what KpNum sensitive spot was generated KpNum*KN the first test datas constitute the first test data set DataSet1, DataSet1 be stored in main control chip with ADDR1 is the memory space of initial address；

6th step, the demand model defined according to second step generates the instruction to be tested of IN bars at random, and IN is positive integer, IN> KpNum*KN/2；For every instruction to be tested, according to the test and excitation template that second step is defined, the test of generation first swashs at random Encourage program；It is serially IN bars IN section the first test and excitation program of instruction generation to be tested, is that every instruction to be tested generates the The process of one test and excitation program is identical, comprises the following steps：

If 6.1 instructions to be tested are instructed for computing class, OpNum operand is randomly choosed first from DataSet1；Then exist Instruction previous existence to be tested, into instruction is moved, is moved during instruction act as operand moving corresponding register；To be tested The first store instruction is generated after instruction, it is ADDR4 that the first store instruction is act as operation result storage to main control chip address Memory space；It is finally the memory space of ADDR2 by the first test and excitation program storage to main control chip address；Turn 6.3；

If 6.2 instructions to be tested are control class instruction, first in instruction previous existence to be tested into the second store instruction, the second storage refers to It is the memory space of ADDR4 that order is act as current status register value storage to main control chip address；Then in finger to be tested The 3rd store instruction is generated after order, the 3rd store instruction is act as status register value storage after execution to main control chip address It is the memory space of ADDR4；It is finally the memory space of ADDR2 by the first test and excitation program storage to main control chip address； Turn 6.3；

6.3ADDR2 increases an address bit, and address bit=machine work is wide/and 8, ADDR4 increases an address bit, and j increases 1, if j< InsNum, represents that the instruction to be tested still has demand model not generate the first test and excitation program, turns the 6th step, if j >= InsNum, represents that all demand models that primary control program has been the instruction to be tested generate the first test and excitation program, if Through being IN bars IN sections of the first test and excitation program of instruction generation to be tested, turn the 7th step, otherwise, turn the 6th step；

7th step, from control Program Synchronization flag bit SFlag, if SFlag=1, expression is waited for from control program for detection, It is the memory space of ADDR8 that IN the first test and excitation program that 6th step is generated is all sent to from control chip address, is turned 8th step；If SFlag=0, represent from control program and be in busy condition, turn the 7th step；

8th step, MFlag is set to 1, represents that main control chip enters wait state；

9th step, receives IN the second test and excitation program sent from control program, is stored in main control chip address depositing for ADDR3 Storage space；

Tenth step, primary control program is according to the value heavy duty address AD DR2 of RADDR2 and jumps to address AD DR2, and order performs master control IN the first test and excitation program of Program Generating, then branches to address AD DR3, and order performs IN from control Program Generating Second test and excitation program, the first test and excitation program implementing result record is the memory space of ADDR4, second in initial address Test and excitation program implementing result record is the memory space of ADDR5 in initial address；

11st step, primary control program detection from control program implementing result Returning mark position ResultFlag, if ResultFlag =1, represent IN the first test and excitation program and IN the second test and excitation journey that will have been performed from control chip from control program Sequence implementing result returns to main control chip, turns the 12nd step；If ResultFlag=0, representing also will be from control core from control program IN the first test and excitation programs and IN the second test and excitation program implementing result that piece is performed return to main control chip, turn the 11 steps；

12nd step, contrasts main control chip and performs IN the first test and excitation program and IN second test respectively from control chip The result of incentive programme, such as implementing result are different, turn the 13rd step；Otherwise, LoopNum1 increases 1, if LoopNum1< MAXLOOP1, represents that primary control program not yet reaches the predetermined cycle-index of program, turns the 4th step, if LoopNum1 >= MAXLOOP1, represents that primary control program has reached the predetermined cycle-index of program, is returned to debugging main frame and completes signal, turns the tenth Four steps；

13rd step, the first test and excitation program for making a mistake of record or the second test and excitation program and main control chip and from Control chip performs the result of the first test and excitation program or the second test and excitation program, and record content is transmitted to by JTAG1 Debugging main frame；

14th step, primary control program terminates；

It is described to be from control program circuit：

Step 1. is identical with the first step of primary control program, the sensitive point set of definition；Defined respectively from control chip address space with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 are the memory space of initial address, are subsequently being held from control program for depositing The interim data for producing and code during row, define RADDR7 and are equal to ADDR7, and the value of RADDR7 is the test and excitation of multistage second Program from control chip in store initial address, for carrying out heavy duty to address ADDR7；

Step 2. defines demand model and test and excitation template；

Step 3. is generated at random in defining program cyclic variable LoopNum2=0, LoopNum2 control verification process from control program The circulation pass of test data, definition is equal to the predetermined cycle-index MAXLOOP2 of primary control program identical, MAXLOOP2 MAXLOOP1；Define temporary variable k=0；From control Program Synchronization flag bit SFlag, SFlag is represented from control chip when being 1 for definition The state that main control chip to be received sends the first test and excitation program such as it has been in；Definition has been returned from control program implementing result Flag bit ResultFlag, ResultFlag are represented when being 1 and are tested the first test and excitation program and second from control program Incentive programme implementing result writes back to main control chip memory space；

Step 4. resets and is set to 0 from control Program Synchronization flag bit, i.e. SFlag, and ResultFlag sets to 0；

Step 5. is identical with the 5th step of primary control program, generates the second test data, constitutes the second test data set DataSet2, DataSet2 is stored in the memory space with ADDR6 as initial address from control chip；

Step 6. generates the instruction to be tested of IN bars at random according to the instruction template that step 2 is defined, for every instruction to be tested, root The second test and excitation program is generated at random according to test and excitation template；It is serially IN sections second test of instruction generation to be tested of IN bars Incentive programme, is that the process of every second test and excitation program of instruction generation to be tested is identical, is comprised the following steps：

If 6.1 ' instructions to be tested are instructed for computing class, OpNum operand is randomly choosed first from DataSet2；Then exist Instruction previous existence, into instruction is moved, is moved during instruction act as operand moving corresponding register, and the is generated after instruction Four store instructions, it is the memory space of ADDR10 that the 4th store instruction act as arriving operation result storage from control chip address； Finally by the second test and excitation program storage to from control chip address for ADDR7 memory space；Turn 6.3 '；

If 6.2 ' instructions to be tested are control class instruction, first in instruction previous existence into the 5th store instruction, the 5th store instruction is made With for by current status register value store to from control chip address be ADDR10 memory space；Then is generated after instruction Six store instructions, it is ADDR10's that the 6th store instruction act as arriving status register value storage after execution from control chip address Memory space；Finally by the second test and excitation program storage to from control chip address for ADDR7 memory space；Turn 6.3 '；

6.3 ' ADDR7 increase an address bit, and ADDR10 increases an address bit, and k increases 1, if k<InsNum, represents described to be measured Examination instruction still has demand model not generate the second test and excitation program, goes to step 6；If k >=InsNum, represent from control program The second test and excitation program is generated through all demand models for the instruction to be tested, if being the instruction generation to be tested of IN bars IN sections of the second test and excitation program, goes to step 7；Otherwise, 6 are gone to step, is next second test and excitation of instruction generation to be tested Program；

Step 7. puts 1 from control Program Synchronization flag bit SFlag, represents from control chip and the main control chip transmission to be received such as be in The state of the first test and excitation program；

Step 8. receives IN the first test and excitation program that primary control program sends, and it is ADDR8 to be stored in from control chip initial address Memory space；

Step 9. detection primary control program synchronous mark position MFlag, if MFlag=1, i.e. primary control program is waited for, will The memory space that main control chip initial address is ADDR3 is sent to from IN the second test and excitation program of control Program Generating, is turned Step 10；Otherwise, 9 are gone to step；

From control program is according to the initial value of RADDR7 heavy duty address ADs DR7 and jumps to address AD DR7, order is performed step 10. From IN the second test and excitation program of control Program Generating, address AD DR8 is then branched to, order performs primary control program generation IN the first test and excitation program, the first test and excitation implementing result and the second test and excitation program implementing result are separately recorded in Initial address is the memory space of ADDR9 and ADDR10；

First test and excitation implementing result is sent to step 11. memory space that main control chip address is ADDR11, and second surveys Examination incentive programme implementing result is sent to the memory space that main control chip address is ADDR12, and will be from control program implementing result Returning mark position ResultFlag puts 1；

Step 12.LoopNum2 increases 1, if LoopNum2<MAXLOOP2, expression not yet reaches the predetermined circulation of program from control program Number of times, goes to step 4；If LoopNum2 >=MAXLOOP2, expression has reached the predetermined cycle-index of program from control program, from control EP (end of program).

2. as claimed in claim 1 towards the microprocessor silicon posteriority card device of compatible design, it is characterised in that the KN takes Value scope is 100~1000, and the fixed value takes the arbitrary value in mantissa's excursion in sensitive spot floating point representation.

3. as claimed in claim 1 towards the microprocessor silicon posteriority card device of compatible design, it is characterised in that the normal state Distribution random numbers generating function includes two steps：The first step meets uniform point using random number generator generation in C language built-in function The random number of cloth；These equally distributed random numbers are converted to and meet normal state by second step using classical BoxMuller algorithms The random number of distribution.

4. as claimed in claim 1 towards the microprocessor silicon posteriority card device of compatible design, it is characterised in that the master control The method of program and demand model and test and excitation template defined in the control program is：Measurement of power is treated by Object--oriented method Can instruct carries out abstract modeling, defines demand model, and process is：Effect according to instruction internal different instruction position will be instructed and divided It is some fields, including opcode field, operand field, condition perform bit field, parallel bit field, each field is one The stochastic variable of individual Prescribed Properties, constraints defines type, span and the random distribution of stochastic variable field Ratio；For different demand models, including double operand instruction, single-operand instruction and nothing are set up in the instruction of different types of structure Operand instruction, makes the number of instruction operands for OpNum, and the OpNum of double operand instruction is equal to 2, single-operand instruction OpNum is equal to 1, and the OpNum of no operand instruction is equal to 0, makes demand model number for InsNum, and InsNum is positive integer； It is that test and excitation template is set up in the instruction of computing class and control class instruction respectively on the basis of demand model；Computing class instruction testing Excitation template includes three parts：Concurrently OpNum operand is moved into OpNum register, execute instruction, by result Write back to memory space；Control class instruction testing excitation template includes three parts：Storage current status register value, execution refer to Make, store status register value after execution；According to the status register for performing the type selecting needs preservation that control class is instructed, control Class command function processed includes：Reprogramming execution sequence, change pipeline state, change perform authority and change buffer status.

5. as claimed in claim 1 towards the microprocessor silicon posteriority card device of compatible design, it is characterised in that described MAXLOOP1 and MAXLOOP2 are set to the 1% of computational space.

6. as claimed in claim 1 towards the microprocessor silicon posteriority card device of compatible design, it is characterised in that the master control Program or the first test data set DataSet1 or the second test data set DataSet2 generating process are as follows from control program：

7.1 defined variable i=0；

I-th sensitive spot that the 7.2 pairs of sensitive spots are concentrated, generation KN is centered on sensitive spot, fixed value as variance, meet normal state The test data of distribution, during the test data of generation is added into DataSet1 or DataSet2, i increases 1；

If 7.3 i<KpNum, turns 7.2；If i >=KpNum, DataSet1 or DataSet2 generation terminate.

7. the microprocessor silicon posteriority card device in a kind of use claim 1~6 described in any claim is to be verified The method that compatible chip carries out functional verification, it is characterised in that comprise the following steps：

Step one, debugging main frame is passed through respectively by CCS IDEs by compiled primary control program and from control program JTAG1 and JTAG2 download to main control chip and from control chip, and start and respectively perform primary control program and from control program；

Step 2, main control chip operation primary control program, while from the operation of control chip from control program, primary control program is responsible for generating master control Chip testing excitation, control main control chip perform test and excitation, compare main control chip and perform test and excitation result from control chip With treatment from control chip implementing result mistake, it is responsible for generating from control chip testing excitation from control program, controls from control chip execution Test and excitation：

2.1) primary control program and define respective sensitive point set respectively simultaneously from control program, define sensitive spot and concentrate sensitive spot number It is KpNum；Defined respectively with ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR11 in main control chip address space Be the memory space of initial address with ADDR12, for deposit primary control program during subsequent execution the interim data for producing and Code, defines RADDR2 and is equal to ADDR2, for carrying out heavy duty to address ADDR2；Defined respectively from control chip address space Memory space with ADDR6, ADDR7, ADDR8, ADDR9 and ADDR10 as initial address, for depositing from control program follow-up The interim data for producing and code in implementation procedure, define RADDR7 and are equal to ADDR7, for carrying out heavy duty to address ADDR7；

2.2) primary control program and from control program simultaneously define respective demand model and test and excitation template respectively；

2.3) primary control program defines program cyclic variable LoopNum1=0, in LoopNum1 control verification process primary control program with Machine generates the circulation pass of test data, defines the predetermined cycle-index MAXLOOP1 of primary control program, and primary control program definition is interim to be become Amount j=0, defines primary control program synchronous mark position MFlag；Simultaneously from control application definition program cyclic variable LoopNum2=0, Generate the circulation pass of test data in LoopNum2 control verification process at random from control program, definition is circulated from control program is predetermined Number of times MAXLOOP2, MAXLOOP2=MAXLOOP1, from control application definition temporary variable k=0, define from control Program Synchronization mark Position SFlag, from control application definition implementing result Returning mark position ResultFlag；

2.4) primary control program reset primary control program synchronous mark position, i.e., MFlag sets to 0；From control Program reset from control Program Synchronization mark Will position, i.e., SFlag sets to 0, and ResultFlag sets to 0；

2.5) primary control program and the first test data and the second test data are generated simultaneously from control program, constitute test and excitation sensitive Space, method is as follows：Primary control program is identical with the process from control Program Generating test data, is generated using normal distribution random number Function generation KN is centered on sensitive spot, fixed value as variance, meet the test data of normal distribution；Primary control program sensitive spot Concentrate KpNum*KN the first test data that KpNum sensitive spot is generated；KpNum sensitivity is concentrated from control program sensitive spot KpNum*KN the second test data that point is generated；First test data of primary control program generation constitutes the first test data set DataSet1, DataSet1 are stored in main control chip the memory space with ADDR1 as initial address, from the of control Program Generating Two test datas constitute the second test data set DataSet2, and DataSet2 is stored in from control chip with ADDR6 as starting point The memory space of location；

2.6) primary control program and from control program simultaneously respectively according to 2.2) definition demand model generate the instruction to be tested of IN bars；It is main Control program turns 2.6.1), IN the first test and excitation program of generation；Meanwhile, turn 2.6.2 from control program), generation IN second is surveyed Examination incentive programme；

2.6.1) primary control program is serially IN bars IN the first test and excitation program of instruction generation to be tested, is every finger to be measured The process all same of order the first test and excitation program of generation, comprises the following steps：

2.6.1.1) if instruction to be tested is instructed for computing class, OpNum is randomly choosed from test data set DataSet1 first Individual operand；Then moved instruction and act as operand moving corresponding posting into instruction is moved in instruction previous existence to be tested In storage；The first store instruction is generated after instruction to be tested, the first store instruction is act as operation result storage to master control Chip address is the memory space of ADDR4；It is finally depositing for ADDR2 by the first test and excitation program storage to main control chip address Storage space, turns 2.6.1.3)；

2.6.1.2) if instruction to be tested is control class instruction, first in instruction previous existence to be tested into the second store instruction, second It is the memory space of ADDR4 that store instruction is act as current status register value storage to main control chip address；Then treating The 3rd store instruction is generated after test instruction, the 3rd store instruction is act as status register value storage after execution to master control core Piece address is the memory space of ADDR4；It is finally the storage of ADDR2 by the first test and excitation program storage to main control chip address Space, turns 2.6.1.3)；

2.6.1.3) ADDR2 increases an address bit, and ADDR4 increases an address bit, and j increases 1, if j<InsNum, represents described Instruction to be tested still has demand model not generate the first test and excitation program, and primary control program turns 2.6.1), if j >=InsNum, Represent that all demand models that primary control program has been the instruction to be tested generate the first test and excitation program, if being IN bars 2.7) IN sections of the first test and excitation program of instruction generation to be tested, turn, and otherwise, primary control program turns 2.6.1), under primary control program is One first test and excitation program of instruction generation to be tested；

2.6.2 it is serially) IN bars IN the second test and excitation program of instruction generation to be tested from control program, is every finger to be measured The process all same of order the second test and excitation program of generation, comprises the following steps：

2.6.2.1) if instruction to be tested is instructed for computing class, OpNum operand is randomly choosed first from DataSet2；So Afterwards in instruction previous existence to be tested into instruction is moved, move during instruction act as operand moving corresponding register；Treating The 4th store instruction is generated after test instruction, the 4th store instruction act as storing operation result to from control chip address and is The memory space of ADDR10；Finally the second test and excitation program storage is turned to being the memory space of ADDR7 from control chip address 2.6.2.3)；

2.6.2.2) if instruction to be tested is control class instruction, first in instruction previous existence to be tested into the 5th store instruction, the 5th It is the memory space of ADDR10 that store instruction act as arriving the storage of current status register value from control chip address；Then treating The 6th store instruction is generated after test instruction, the 6th store instruction act as arriving status register value storage after execution from control Chip address is the memory space of ADDR10；Finally by the second test and excitation program storage to from control chip address for ADDR7 Memory space, turns 2.6.2.3)；

2.6.2.3) ADDR7 increases an address bit, and ADDR10 increases an address bit, and k increases 1, if k<InsNum, represents described Instruction to be tested still has demand model not generate the second test and excitation program, and 2.6.2 is turned from control program), if k >=InsNum, Represent from all demand models that control program has been the instruction to be tested and generate the second test and excitation program, if being IN bars 2.7) IN sections of the second test and excitation program of instruction generation to be tested, turn；Otherwise, 2.6.2 is turned from control program), it is next to be measured Examination instruction the second test and excitation program of generation；

2.7) synchronous mark position SFlag is put 1 from control program, represents from control chip and the main control chip transmission to be received such as be in 2.8) the IN state of the first test and excitation program, turn；Meanwhile, primary control program is detected from Program Synchronization flag bit SFlag is controlled, such as Fruit SFlag=1, expression is waited for from control program, IN the first test and excitation program whole that primary control program will be generated It is the memory space of ADDR8 to be sent to from control chip address, and 2.8) primary control program turns；Otherwise, 2.7) primary control program turns；

2.8) MFlag is put 1 by primary control program, represents that main control chip enters wait state, and 2.9) primary control program turns；Simultaneously from control journey Sequence detection primary control program synchronous mark position MFlag, if MFlag=1, i.e. primary control program is waited for, and turns from control program 2.9)；Otherwise, turn 2.8) from control program；

2.9) IN of generation the second test and excitation program is sent to main control chip initial address depositing for ADDR3 from control program Storage space, while primary control program receives IN the second test and excitation program sent from control program；

2.10) primary control program is according to the initial value of RADDR2 heavy duties address AD DR2 and jumps to address AD DR2, and order performs master IN the first test and excitation program of Program Generating is controlled, address AD DR3 is then branched to, order performs the IN from control Program Generating Individual second test and excitation program, the first test and excitation program implementing result record is the memory space of ADDR4 in initial address, the Two test and excitation program implementing results record is the memory space of ADDR5 in initial address；Simultaneously from control program according to RADDR7 The initial value of heavily loaded address AD DR7 simultaneously jumps to address AD DR7, and order performs IN the second test and excitation from control Program Generating Program, then branches to address AD DR8, and order performs IN the first test and excitation program of primary control program generation, the first test Excitation implementing result and the second test and excitation program implementing result are separately recorded in the storage that initial address is ADDR9 and ADDR10 Space；

2.11) the first test and excitation implementing result is sent to the memory space that main control chip address is ADDR11 from control program, Second test and excitation program implementing result is sent to main control chip address and is the memory space of ADDR12, and will held from control program Returning mark position ResultFlag puts 1 to row result, turns 2.12) from control program；Primary control program detection simultaneously is performed from control program Result Returning mark position ResultFlag, if ResultFlag=1, represent from control program will perform IN from control chip First test and excitation program and IN the second test and excitation program implementing result return to main control chip, and 2.12) primary control program turns； If ResultFlag=0, represent from control program also will not perform IN the first test and excitation program and IN second from control chip Test and excitation program implementing result returns to main control chip, and 2.11) primary control program turns；

2.12) primary control program contrasts main control chip and performs IN the first test and excitation program and IN second respectively from control chip The result of test and excitation program, such as implementing result are different, turn 2.13)；Otherwise, LoopNum1 increases 1, LoopNum2 and increases 1, master control journey Sequence turns 2.12.1), while turning 2.12.2 from control program)；

2.12.1) primary control program compares the size of LoopNum1 and MAXLOOP1, if LoopNum1<MAXLOOP1, represents master control Program not yet reaches the predetermined cycle-index of program, and 2.4) primary control program turns；If LoopNum1 >=MAXLOOP1, master control journey is represented Sequence has reached the predetermined cycle-index of program, is returned to debugging main frame and completes signal, and 2.14) primary control program turns；

2.12.2 the size of LoopNum2 and MAXLOOP2) is compared from control program, if LoopNum2<MAXLOOP2, represents from control Program not yet reaches the predetermined cycle-index of program, turns 2.4) from control program；If LoopNum2 >=MAXLOOP2, represent from control journey Sequence has reached the predetermined cycle-index of program, terminates from control program；

2.13) primary control program record makes a mistake the first test and excitation program or the second test and excitation program and main control chip With the result that the first test and excitation program or the second test and excitation program are performed from control chip, and record content is passed through into JTAG1 It is transmitted to debugging main frame；

2.14) terminate primary control program, go to step three；

Step 3, if debugging main frame receives the completion signal that main control chip is passed back by JTAG1, verification process terminates；Such as Fruit debugging main frame is received main control chip and is passed back the first test and excitation program or the second test and excitation journey for making a mistake by JTAG1 Sequence and main control chip and the result of the first test and excitation program or the second test and excitation program is performed from control chip, debug main frame The first test and excitation program for making a mistake of display or the second test and excitation program and main control chip and perform the from control chip The result of one test and excitation program or the second test and excitation program, verification process terminates.