CN104658937A - Method for measuring breakdown voltage of gate oxide layer of groove type VDMOS device - Google Patents
Method for measuring breakdown voltage of gate oxide layer of groove type VDMOS device Download PDFInfo
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- CN104658937A CN104658937A CN201310589482.4A CN201310589482A CN104658937A CN 104658937 A CN104658937 A CN 104658937A CN 201310589482 A CN201310589482 A CN 201310589482A CN 104658937 A CN104658937 A CN 104658937A
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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Abstract
The invention provides a method for measuring the breakdown voltage of a gate oxidation layer of a groove type VDMOS device. The method comprises the following steps: providing a silicon substrate with an epitaxial layer; forming an initial oxidation layer on the epitaxial layer; performing photoetching and etching so as to form a figure on the initial oxidation layer; performing etching by using the initial oxidation layer on which the figure is formed as a mask film, forming parallel grooves at interval at an active region, wherein both ends of the grooves are positioned at the edge of the active region; removing the initial oxidation layer, and forming a sacrificial oxidation layer on the epitaxial layer; removing the sacrificial oxidation layer, and forming a gate oxidation layer on the epitaxial layer; depositing polycrystalline silicon on the grooves and the gate oxidation layer outside the grooves; etching the polycrystalline silicon in the active region outside the grooves so as to form a test silicon wafer for the gate oxidation layer; measuring the breakdown voltage of the gate oxidation layer by applying voltage on the polycrystalline silicon and both ends of the silicon substrate. The method is high in operability and low in cost, the method can be implemented in multiple technology steps for manufacturing devices, and is favorable for monitoring and improving the manufacturing technology of the devices.
Description
Technical field
The invention belongs to technical field of semiconductors, be specifically related to a kind of method measuring trench VDMOS device gate oxide breakdown voltage.
Background technology
Gate oxide integrity (GOI) is the very important test event considering and assess quality of gate oxide in semiconductor fabrication.Way comparatively conventional at present grows one deck gate oxide on a silicon substrate, then on gate oxide, one deck polysilicon is grown, by applying voltage at the two ends of polysilicon and silicon substrate, test out the puncture voltage of gate oxide, and judge integrality and the quality of gate oxide according to the gate oxide breakdown voltage tested, but the test result of the method may not be inconsistent with the actual conditions of device.
In order to the actual conditions making test result more press close to device, usually by some figures of design, first can be made on a silicon substrate, and then grown gate oxide and polysilicon on a silicon substrate.Design these figures usually to need to make specific mask plate (i.e. GOI version), on specific silicon substrate, corresponding structure is produced by these mask plates, thus form GOI sheet, by judging integrality and the quality of gate oxide to the mensuration of GOI sheet gate oxide breakdown voltage, but these techniques all can expend regular hour and financial resources.
For trench VDMOS device, although adopt said method can consider the quality of gate oxide to a certain extent, but it not only expends time in and financial resources, in addition for the situation that component grid oxidizing layer puncture voltage is on the low side, its which step being difficult to determine in manufacturing process causes the generation of this problem, thus the manufacturing process of difficulty to device is improved.
Summary of the invention
The invention provides a kind of method measuring trench VDMOS device gate oxide breakdown voltage, its strong operability, cost is low, can implement in trench VDMOS device manufacture craft process, is conducive to monitoring device making technics and improving.
A kind of method measuring trench VDMOS device gate oxide breakdown voltage provided by the invention, comprises the steps:
The silicon substrate with epitaxial loayer is provided, is set with active area regions on said epitaxial layer there;
The epitaxial loayer of described silicon substrate forms initial oxide layer;
Photoetching, etching, described initial oxide layer forms figure;
Etch for mask with the initial oxide layer forming described figure, form parallel and spaced groove in described active area region, the two ends of described groove are positioned at the edge of described active area region;
Remove described initial oxide layer, and form sacrificial oxide layer on said epitaxial layer there;
Remove described sacrificial oxide layer, and form gate oxide on said epitaxial layer there;
Depositing polysilicon on the gate oxide of described groove and described groove outside;
Etch the polysilicon in the active area region of described groove outside, form gate oxide test silicon wafer, the two ends of the polysilicon of its trench interiors are connected with the polysilicon of periphery, described active area region;
By applying voltage at the polysilicon of described gate oxide test silicon wafer and silicon substrate two ends, measure the puncture voltage of described gate oxide.
According to the method for mensuration trench VDMOS device gate oxide breakdown voltage provided by the invention, the degree of depth of described groove is 1.5 ~ 2.5um, and width is 0.6 ~ 1um.
According to the method for mensuration trench VDMOS device gate oxide breakdown voltage provided by the invention, the distance≤3um between described adjacent trenches.
According to the method for mensuration trench VDMOS device gate oxide breakdown voltage provided by the invention, adopt wet oxidation to form described initial oxide layer, and the thickness of described initial oxide layer is 0.1 ~ 1um.
According to the method for mensuration trench VDMOS device gate oxide breakdown voltage provided by the invention, the thickness of described sacrificial oxide layer is
According to the method for mensuration trench VDMOS device gate oxide breakdown voltage provided by the invention, the thickness of described gate oxide is 0.05 ~ 0.2um.
According to the method for mensuration trench VDMOS device gate oxide breakdown voltage provided by the invention, on the gate oxide of described groove outside, the thickness of the polysilicon of deposit is
The present invention also provides a kind of gate oxide test silicon wafer, comprising:
There is the silicon substrate of epitaxial loayer, be set with active area region on said epitaxial layer there;
Parallel and the spaced groove being arranged on inside, described epitaxial loayer active area region, its two ends are positioned at the edge of described active area region;
Be arranged on the gate oxide of described epi-layer surface;
Be arranged on the polysilicon strip of described trench interiors;
Be arranged on the polysilicon layer of periphery, described active area region, it is connected with the two ends of described polysilicon strip.
According to gate oxide test silicon wafer provided by the invention, the degree of depth of described groove is 1.5 ~ 2.5um, and the width of described groove is 0.6 ~ 1um, the spacing≤3um between described adjacent trenches.
According to gate oxide test silicon wafer provided by the invention, the thickness of described gate oxide is 0.05 ~ 0.2um, and the thickness of described polysilicon layer is
A kind of method measuring trench VDMOS device gate oxide breakdown voltage provided by the invention, its strong operability, cost is low, can directly be realized by the Making programme of trench VDMOS device, and implement in multiple processing steps that can make in trench VDMOS device, thus be conducive to monitoring trench VDMOS device manufacture craft and improving.
Accompanying drawing explanation
Fig. 1 to Fig. 6 is the schematic flow sheet of the method for the mensuration groove-shaped VDMOS gate oxide breakdown voltage of one embodiment of the invention;
Fig. 7 is the plan structure schematic diagram of the gate oxide test silicon wafer of one embodiment of the invention;
Fig. 8 is the equivalent structure schematic diagram of gate oxide test silicon wafer when carrying out gate oxide breakdown voltage determination of one embodiment of the invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with drawings and Examples of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment 1
A kind of method measuring groove-shaped VDMOS gate oxide breakdown voltage of the present invention, can realize in the technical process manufacturing trench VDMOS device and be implemented, it can comprise the steps:
Step 1, provide the silicon substrate with epitaxial loayer, be set with active area regions on said epitaxial layer there;
Specifically as shown in Figure 1, the described silicon substrate with epitaxial loayer can be the epitaxial wafer of this area routine, also the method for this area routine can be adopted on silicon substrate 1 to grow epitaxial loayer 2, the active area region set on the epitaxial layer 2 is used for forming the active area of trench VDMOS device, in the present embodiment, the shape of described active area region is rectangle.
Step 2, on the epitaxial loayer of described silicon substrate, form initial oxide layer;
Particularly, can adopt wet oxidation on the epitaxial loayer 2 of described silicon substrate 1, form the initial oxide layer 3 that thickness is 0.1 ~ 1um; In the present embodiment, the thickness of the initial oxide layer 3 formed can be 1um, and the temperature of wet oxidation can be 950 DEG C.
Step 3, photoetching, etching, described initial oxide layer forms figure;
Particularly, can by spin coating photoresist on described initial oxide layer 3, undertaken exposing rear development by mask plate, photoresist corresponding above active area region is formed the figure with parallel and spaced striped, again with the photoresist layer with figure for mask etches, thus initial oxide layer 3 above active area region being formed the figure with parallel and spaced striped, the width of described striped can be 0.6 ~ 1um, and the distance between adjacent stripes can be 1 ~ 3um; In the present embodiment, the width of described striped can be 1um, and the distance between adjacent stripes can be 3um.
Step 4, etch for mask with the initial oxide layer forming described figure, form parallel and spaced groove in described active area region, the two ends of described groove are positioned at the edge of active area region;
Specifically as shown in Figure 2, dry etching can be adopted, as plasma etching as described in active area region formed groove 4, the degree of depth D of wherein said groove 4 can be 1.5 ~ 2.5um, distance between the width of groove 4 and adjacent trenches 4 is corresponding with the figure on initial oxide layer 3, and in the present embodiment, the degree of depth of described groove 4 is 1.5 ~ 2um, width is 1um, and the distance between adjacent trenches 4 is 3um.
Step 5, remove described initial oxide layer, and form sacrificial oxide layer on said epitaxial layer there;
Specifically as shown in Figure 3, first chemical reagent can be adopted, as hydrofluoric acid corrodes, to remove the initial oxide layer 3 on epitaxial loayer 2; Then can adopt thermal oxidation formed thickness be
sacrificial oxide layer (not shown), the thickness of the sacrificial oxide layer formed in the present embodiment can be
it is for removing the part of epitaxial loayer 2 surface suffered damage when etching, thus improves the quality of the follow-up gate oxide formed on epitaxial loayer 2 surface.
Step 6, remove described sacrificial oxide layer, and form gate oxide on said epitaxial layer there;
Specifically as shown in Figure 4, first chemical reagent can be adopted, as hydrofluoric acid corrodes, to remove the sacrificial oxide layer (not shown) on epitaxial loayer 2; Then adopt dry oxidation to form the gate oxide 5 that thickness is 0.05 ~ 0.2um, in the present embodiment, the thickness of the gate oxide 5 formed is 0.1um.
Step 7, on the gate oxide of described groove and described groove outside depositing polysilicon;
Specifically as shown in Figure 5, chemical vapour deposition (CVD) can be adopted at described groove 4 depositing polysilicon 6, and deposit a layer thickness is on the gate oxide 5 of described groove 4 outside
polysilicon 6, in the present embodiment, polysilicon 6 fills whole groove 4, and the thickness of polysilicon 6 formed on the gate oxide 5 of described groove 4 outside can be
Step 8, the polysilicon etched in the active area region of described groove outside, form gate oxide test silicon wafer, the two ends of the polysilicon of its trench interiors are connected with the polysilicon of periphery, described active area region;
Specifically as shown in Figure 6, polysilicon 6 in the active area region of described groove 4 outside can be fallen by direct etching, now form in groove 4 inside the polysilicon 6 that namely polysilicon strip 61(is filled in groove 4 inside), and it is not shown to form polysilicon layer 62(in periphery, active area region), polysilicon layer 62 is formed with the two ends of polysilicon strip 61 respectively and is connected; In addition, photoetching, etching can also be carried out to the silicon substrate 1 after depositing polysilicon 6, while the polysilicon 6 in the active area region etching away described groove 4 outside, form field plate in ring district, to improve the make efficiency of trench VDMOS device.
Step 9, by applying voltage at the polysilicon of described gate oxide test silicon wafer and silicon substrate two ends, measure the puncture voltage of described gate oxide;
Specifically as shown in Figure 7, Figure 8, positive electricity can be applied on the polysilicon layer 62 of periphery, active area region, silicon substrate 1 applies negative electricity, by increasing voltage gradually, until gate oxide 5 is breakdown, to record the puncture voltage of described gate oxide 5; When gate oxide 5 puncture voltage measures, gate oxide 5 is between polysilicon 6 and silicon substrate 1 all the time, therefore can consider and assess quality and the integrality of gate oxide 5 according to the puncture voltage of measured gate oxide 5.
Further, common process can also be adopted after described step 9 to complete the follow-up making of trench VDMOS device, as tagma injection and drive in, the injection in source region and driving in, in follow-up manufacturing process, the gate oxide test silicon wafer that said method is formed can not change, and other structure can not be added on the polysilicon layer 62 of periphery, described active area region, therefore can by applying at polysilicon layer 62 and silicon substrate 1 two ends the puncture voltage that voltage carrys out the gate oxide 5 in the follow-up rear processing step of the real time measure, and the manufacture craft of trench VDMOS device is monitored by the puncture voltage measured, thus search in processing step the reason causing gate oxide 5 puncture voltage on the low side targetedly, and in time the manufacture craft of trench VDMOS device is improved, thus ensure quality and the integrality of trench VDMOS device gate oxide 5.
Embodiment 2
As shown in Figure 6, Figure 7, a kind of gate oxide test silicon wafer provided by the invention, comprising: the silicon substrate 1 with epitaxial loayer 2, is set with active area region on the epitaxial layer 2; Parallel and the spaced groove 4 being arranged on inside, described epitaxial loayer 2 active area region, its two ends are positioned at the edge of described active area region; Be arranged on the gate oxide 5 on described epitaxial loayer 2 surface; Be arranged on the polysilicon strip 61 of described groove 4 inside; Be arranged on the polysilicon layer 62 of periphery, described active area region, it is connected with the two ends of described polysilicon strip 61.
The described gate oxide test silicon wafer of the present embodiment can be prepared to step 8 according to the step 1 in embodiment 1, in the present embodiment, the degree of depth of described groove 4 is 2um, width is 1um, spacing between adjacent trenches 4 is 3um, and the thickness of described gate oxide 4 is 0.1um, the thickness of described polysilicon layer 62 is
By applying voltage at the polysilicon layer 62 of above-mentioned gate oxide test silicon wafer and the two ends of silicon substrate 1, may be used for the puncture voltage measuring component grid oxidizing layer 4, and then considering and assess quality and the integrality of component grid oxidizing layer 4.In addition, those skilled in the art can also in this gate oxide test silicon wafer conveniently technique proceed the making of follow-up trench VDMOS device, in subsequent fabrication process, without the need to other structure additional on the polysilicon layer 62 of the periphery, active area region of this gate oxide test silicon wafer, therefore it is used in the test carrying out gate oxide breakdown voltage in each subsequent step of trench VDMOS device manufacturing process, thus monitors the manufacture craft of VDMOS device and improve.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. measure a method for groove-shaped VDMOS gate oxide breakdown voltage, it is characterized in that, comprise the steps:
The silicon substrate with epitaxial loayer is provided, is set with active area regions on said epitaxial layer there;
The epitaxial loayer of described silicon substrate forms initial oxide layer;
Photoetching, etching, described initial oxide layer forms figure;
Etch for mask with the initial oxide layer forming described figure, form parallel and spaced groove in described active area region, the two ends of described groove are positioned at the edge of described active area region;
Remove described initial oxide layer, and form sacrificial oxide layer on said epitaxial layer there;
Remove described sacrificial oxide layer, and form gate oxide on said epitaxial layer there;
Depositing polysilicon on the gate oxide of described groove and described groove outside;
Etch the polysilicon in the active area region of described groove outside, form gate oxide test silicon wafer, the two ends of the polysilicon of its trench interiors are connected with the polysilicon of periphery, described active area region;
By applying voltage at the polysilicon of described gate oxide test silicon wafer and silicon substrate two ends, measure the puncture voltage of described gate oxide.
2. method according to claim 1, is characterized in that, the degree of depth of described groove is 1.5 ~ 2.5um, and width is 0.6 ~ 1um.
3. method according to claim 1, is characterized in that, the distance≤3um between described adjacent trenches.
4. according to the arbitrary described method of claims 1 to 3, it is characterized in that, adopt wet oxidation to form described initial oxide layer, and the thickness of described initial oxide layer is 0.1 ~ 1um.
5., according to the arbitrary described method of claims 1 to 3, it is characterized in that, the thickness of described sacrificial oxide layer is
6., according to the arbitrary described method of claims 1 to 3, it is characterized in that, the thickness of described gate oxide is 0.05 ~ 0.2um.
7., according to the arbitrary described method of claims 1 to 3, it is characterized in that, on the gate oxide of described groove outside, the thickness of the polysilicon of deposit is
8. a gate oxide test silicon wafer, is characterized in that, comprising:
There is the silicon substrate of epitaxial loayer, be set with active area region on said epitaxial layer there;
Parallel and the spaced groove being arranged on inside, described epitaxial loayer active area region, its two ends are positioned at the edge of described active area region;
Be arranged on the gate oxide of described epi-layer surface;
Be arranged on the polysilicon strip of described trench interiors;
Be arranged on the polysilicon layer of periphery, described active area region, it is connected with the two ends of described polysilicon strip.
9. gate oxide test silicon wafer according to claim 8, is characterized in that, the degree of depth of described groove is 1.5 ~ 2.5um, and the width of described groove is 0.6 ~ 1um, the spacing≤3um between described adjacent trenches.
10. gate oxide test silicon wafer according to claim 8 or claim 9, it is characterized in that, the thickness of described gate oxide is 0.05 ~ 0.2um, and the thickness of described polysilicon layer is
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113643997A (en) * | 2021-07-30 | 2021-11-12 | 天津环鑫科技发展有限公司 | Groove shape monitoring method and structural device |
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| US5849621A (en) * | 1996-06-19 | 1998-12-15 | Advanced Micro Devices, Inc. | Method and structure for isolating semiconductor devices after transistor formation |
| CN1194413C (en) * | 2002-09-09 | 2005-03-23 | 北京大学 | Vertical channel FET and its manufacture |
| CN103094087A (en) * | 2011-11-01 | 2013-05-08 | 上海华虹Nec电子有限公司 | Method of etching groove polycrystalline silicon gate |
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| US5387538A (en) * | 1992-09-08 | 1995-02-07 | Texas Instruments, Incorporated | Method of fabrication of integrated circuit isolation structure |
| US5849621A (en) * | 1996-06-19 | 1998-12-15 | Advanced Micro Devices, Inc. | Method and structure for isolating semiconductor devices after transistor formation |
| CN1194413C (en) * | 2002-09-09 | 2005-03-23 | 北京大学 | Vertical channel FET and its manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113643997A (en) * | 2021-07-30 | 2021-11-12 | 天津环鑫科技发展有限公司 | Groove shape monitoring method and structural device |
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