CN104658937B - A kind of method for determining trench VDMOS device gate oxide breakdown voltage - Google Patents
A kind of method for determining trench VDMOS device gate oxide breakdown voltage Download PDFInfo
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- CN104658937B CN104658937B CN201310589482.4A CN201310589482A CN104658937B CN 104658937 B CN104658937 B CN 104658937B CN 201310589482 A CN201310589482 A CN 201310589482A CN 104658937 B CN104658937 B CN 104658937B
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- gate oxide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The present invention provides a kind of method for determining trench VDMOS device gate oxide breakdown voltage, including：Silicon substrate with epitaxial layer is provided；Initial oxide layer is formed on epitaxial layer；Photoetching, etching, form figure on initial oxide layer；To form the initial oxide layer of figure as mask is performed etching, parallel and spaced groove is formed in active area region, the two ends of groove are located at the edge of active area region；Removal initial oxide layer, and sacrificial oxide layer is formed on epitaxial layer；Removal sacrificial oxide layer, and gate oxide is formed on epitaxial layer；Depositing polysilicon on gate oxide outside groove and groove；The polysilicon in active area region outside etching groove, forms gate oxide test silicon wafer；By in polysilicon and silicon substrate two ends applied voltage, determining the breakdown voltage of gate oxide.The method strong operability, low cost can be implemented in multiple processing steps of element manufacturing, be conducive to being monitored device making technics and improving.
Description
Technical field
The invention belongs to technical field of semiconductors, and in particular to one kind determines trench VDMOS device gate oxide breakdown
The method of voltage.
Background technology
Gate oxide integrity (GOI) be consider and assess in semiconductor fabrication one of quality of gate oxide it is extremely important
Test event.Way more conventional at present is to grow one layer of gate oxide on a silicon substrate, then raw on gate oxide
One layer of polysilicon long, by the two ends applied voltage in polysilicon and silicon substrate, tests out the breakdown voltage of gate oxide, and according to
The integrality and quality of gate oxide are judged according to the gate oxide breakdown voltage of test, but the test result of the method can
Can not be inconsistent with the actual conditions of device.
In order that test result more presses close to the actual conditions of device, it will usually by designing some figures, first made
Make on a silicon substrate, then to grow gate oxide and polysilicon on a silicon substrate again.Designing these figures generally needs to make special
Fixed mask plate (i.e. GOI editions), produces corresponding structure, so as to be formed by these mask plates on specific silicon substrate
GOI pieces, by judging the measure of GOI piece gate oxide breakdown voltages the integrality and quality of gate oxide, but these
Technique can expend regular hour and financial resources.
For trench VDMOS device, although can to a certain extent consider the matter of gate oxide using the above method
Amount, but it not only expends time and financial resources, and further for the situation that component grid oxidizing layer breakdown voltage is relatively low, it is difficult to determination is
Which step in manufacturing process causes the generation of this problem, so that difficulty is improved to the manufacturing process of device.
The content of the invention
A kind of method for determining trench VDMOS device gate oxide breakdown voltage of present invention offer, its strong operability, into
This is low, can be implemented during trench VDMOS device manufacture craft, be conducive to being monitored device making technics and
Improve.
A kind of method of measure trench VDMOS device gate oxide breakdown voltage that the present invention is provided, including following step
Suddenly：
Silicon substrate with epitaxial layer is provided, active area region is set on said epitaxial layer there；
Initial oxide layer is formed on the epitaxial layer of the silicon substrate；
Photoetching, etching, figure is formed on the initial oxide layer；
To form the initial oxide layer of the figure as mask is performed etching, parallel and phase is formed in the active area region
The groove being mutually spaced, the two ends of the groove are located at the edge of the active area region；
The initial oxide layer is removed, and forms sacrificial oxide layer on said epitaxial layer there；
The sacrificial oxide layer is removed, and forms gate oxide on said epitaxial layer there；
Depositing polysilicon on gate oxide outside the groove and the groove；
The polysilicon in the active area region outside the groove is etched, gate oxide test silicon wafer is formed, in its groove
The two ends of the polysilicon in portion are connected with the polysilicon of active area region periphery；
By the polysilicon in the gate oxide test silicon wafer and silicon substrate two ends applied voltage, the gate oxidation is determined
The breakdown voltage of layer.
The method of the measure trench VDMOS device gate oxide breakdown voltage provided according to the present invention, the groove
Depth is 1.5~2.5 μm, and width is 0.6~1 μm.
The method of the measure trench VDMOS device gate oxide breakdown voltage provided according to the present invention, the adjacent ditch
The distance between groove≤3 μm.
The method of the measure trench VDMOS device gate oxide breakdown voltage provided according to the present invention, using wet method oxygen
Change forms the initial oxide layer, and the thickness of the initial oxide layer is 0.1~1 μm.
The method of the measure trench VDMOS device gate oxide breakdown voltage provided according to the present invention, the sacrifice oxygen
Change layer thickness be
The method of the measure trench VDMOS device gate oxide breakdown voltage provided according to the present invention, the gate oxidation
The thickness of layer is 0.05~0.2 μm.
The method of the measure trench VDMOS device gate oxide breakdown voltage provided according to the present invention, outside the groove
The thickness of the polysilicon of deposit is on the gate oxide in portion
The present invention also provides a kind of gate oxide test silicon wafer, including：
Silicon substrate with epitaxial layer, is set with active area region on said epitaxial layer there；
The parallel and spaced groove being arranged on inside the epitaxial layer active area region, its two ends are located at described active
The edge of region；
It is arranged on the gate oxide of the epi-layer surface；
It is arranged on the polysilicon strip of the trench interiors；
The polysilicon layer of the active area region periphery is arranged on, it is connected with the two ends of the polysilicon strip.
According to the gate oxide test silicon wafer that the present invention is provided, the depth of the groove is 1.5~2.5 μm, the groove
Width be 0.6~1 μm, spacing≤3 μm between the adjacent trenches.
According to the gate oxide test silicon wafer that the present invention is provided, the thickness of the gate oxide is 0.05~0.2 μm, described
The thickness of polysilicon layer is
A kind of method of measure trench VDMOS device gate oxide breakdown voltage that the present invention is provided, its strong operability,
Low cost, directly can be realized, and can be made in trench VDMOS device by the Making programme of trench VDMOS device
Multiple processing steps in implemented, so as to be conducive to that trench VDMOS device manufacture craft is monitored and improved.
Brief description of the drawings
Fig. 1 to Fig. 6 is the flow of the method for the groove-shaped VDMOS gate oxide breakdowns voltage of measure of one embodiment of the invention
Schematic diagram；
Fig. 7 is the overlooking the structure diagram of the gate oxide test silicon wafer of one embodiment of the invention；
Fig. 8 for one embodiment of the invention gate oxide test silicon wafer when gate oxide breakdown voltage determination is carried out etc.
Effect structural representation.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing of the invention and implementation
Example, is clearly and completely described to the technical scheme in the embodiment of the present invention, it is clear that described embodiment is the present invention
A part of embodiment, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not having
The every other embodiment obtained under the premise of creative work is made, the scope of protection of the invention is belonged to.
Embodiment 1
A kind of method for determining groove-shaped VDMOS gate oxide breakdowns voltage of the present invention, can be in manufacture groove type VDMOS
Realize and be practiced in the technical process of device, it may include steps of：
The silicon substrate of step 1, offer with epitaxial layer, sets active area region on said epitaxial layer there；
Specifically as shown in figure 1, the silicon substrate with epitaxial layer can be the conventional epitaxial wafer in this area, it is also possible to adopt
Epitaxial layer 2 is grown on silicon substrate 1 with the conventional method in this area, the active area region for setting on the epitaxial layer 2 is used
Forming the active area of trench VDMOS device, in the present embodiment, the active area region is shaped as rectangle.
Step 2, on the epitaxial layer of the silicon substrate form initial oxide layer；
Specifically, can use wet oxidation formed on the epitaxial layer 2 of the silicon substrate 1 thickness for 0.1~1 μm just
Beginning oxide layer 3；In the present embodiment, the thickness of the initial oxide layer 3 for being formed can be 1 μm, and the temperature of wet oxidation can be with
It is 950 DEG C.
Step 3, photoetching, etching, figure is formed on the initial oxide layer；
Specifically, can be shown after being exposed by mask plate by the spin coating photoresist on the initial oxide layer 3
Shadow, forms the figure with parallel and spaced striped on corresponding photoresist above active area region, then with figure
The photoresist layer of shape is performed etching for mask, so as to formed on initial oxide layer 3 above active area region have it is parallel and
The figure of spaced striped, the width of the striped can be 0.6~1 μm, and the distance between adjacent stripes can be 1~3 μ
m；In the present embodiment, the width of the striped can be 1 μm, and the distance between adjacent stripes can be 3 μm.
Step 4, to form the initial oxide layer of the figure as mask is performed etching, form flat in the active area region
Capable and spaced groove, the two ends of the groove are located at the edge of active area region；
Specifically as shown in Fig. 2 dry etching can be used, such as plasma etching forms groove in the active area region
4, wherein the depth D of the groove 4 can be 1.5~2.5 μm, the distance between width and adjacent trenches 4 of groove 4 with it is initial
Figure in oxide layer 3 is corresponding, and in the present embodiment, the depth of the groove 4 is 1.5~2 μm, and width is 1 μm, adjacent ditch
The distance between groove 4 is 3 μm.
Step 5, the removal initial oxide layer, and sacrificial oxide layer is formed on said epitaxial layer there；
Specifically as shown in figure 3, chemical reagent can be used first, and such as hydrofluoric acid is corroded, to go on epitaxial layers 2
Initial oxide layer 3；Then can use thermal oxide formed thickness forSacrificial oxide layer (do not show in figure
Go out), the thickness of the sacrificial oxide layer formed in the present embodiment can beIt is used for the surface of epitaxial layers 2 and is entering
The part of suffered damage during row etching, so as to improve the quality of the follow-up gate oxide formed on the surface of epitaxial layer 2.
Step 6, the removal sacrificial oxide layer, and gate oxide is formed on said epitaxial layer there；
Specifically as shown in figure 4, chemical reagent can be used first, and such as hydrofluoric acid is corroded, to go on epitaxial layers 2
Sacrificial oxide layer (not shown)；Then dry oxidation is used to form the gate oxide 5 that thickness is for 0.05~0.2 μm, at this
In embodiment, the thickness of the gate oxide 5 for being formed is 0.1 μm.
Depositing polysilicon on step 7, the gate oxide outside the groove and the groove；
Specifically as shown in figure 5, chemical vapor deposition can be used in the depositing polysilicon 6 of the groove 4, and in the ditch
A layer thickness is deposited on gate oxide 5 outside groove 4 isPolysilicon 6, in the present embodiment, polycrystalline
Silicon 6 fills whole groove 4, and the thickness of the polysilicon 6 formed on gate oxide 5 outside the groove 4 can be
The polysilicon in active area region outside step 8, the etching groove, forms gate oxide test silicon wafer, its
The two ends of the polysilicon of trench interiors are connected with the polysilicon of active area region periphery；
Specifically as shown in fig. 6, the polysilicon 6 in the active area region outside the groove 4 can be fallen with direct etching, now
Polysilicon strip 61 (being filled in the polysilicon 6 inside groove 4) is internally formed in groove 4, and in active area region periphery shape
Into the (not shown) of polysilicon layer 62, polysilicon layer 62 forms with the two ends of polysilicon strip 61 be connected respectively；Further, it is also possible to
Photoetching, etching are carried out to the silicon substrate 1 after depositing polysilicon 6, it is many in the active area region etched away outside the groove 4
While crystal silicon 6, field plate is formed in ring region, to improve the producing efficiency of trench VDMOS device.
Step 9, by the polysilicon in the gate oxide test silicon wafer and silicon substrate two ends applied voltage, determine described
The breakdown voltage of gate oxide；
Specifically as shown in Figure 7, Figure 8, positive electricity can be applied on the polysilicon layer 62 of active area region periphery, in silicon substrate
Apply negative electricity on 1, by gradually increasing voltage, until gate oxide 5 is breakdown, to measure the breakdown potential of the gate oxide 5
Pressure；When the breakdown voltage of gate oxide 5 is determined, gate oxide 5 is between polysilicon 6 and silicon substrate 1 all the time, therefore according to institute
The quality and integrality of gate oxide 5 can be considered and assessed to the breakdown voltage of the gate oxide 5 for measuring.
Further, the follow-up system of trench VDMOS device can also be completed using common process after the step 9
Make, such as the injection in body area and drive in, the injection of source region and drive in, in follow-up manufacturing process, the grid that the above method is formed
Oxide layer test silicon wafer will not change, and will not add other on the polysilicon layer 62 of active area region periphery
Structure, therefore can be by processing step after polysilicon layer 62 and the two ends applied voltage of silicon substrate 1 are follow-up come the real time measure
Gate oxide 5 breakdown voltage, and the manufacture craft of trench VDMOS device is monitored by the breakdown voltage for determining, from
And the reason for cause the breakdown voltage of gate oxide 5 relatively low in processing step is targetedly searched, and in time to groove-shaped VDMOS
The manufacture craft of device is improved, so as to ensure the quality and integrality of trench VDMOS device gate oxide 5.
Embodiment 2
As shown in Figure 6, Figure 7, a kind of gate oxide test silicon wafer that the present invention is provided, including：Silicon lining with epitaxial layer 2
Bottom 1, is set with active area region on the epitaxial layer 2；It is parallel and spaced be arranged on the active area region of the epitaxial layer 2
Internal groove 4, its two ends are located at the edge of the active area region；It is arranged on the gate oxide 5 on the surface of the epitaxial layer 2；
It is arranged on the polysilicon strip 61 inside the groove 4；Be arranged on the polysilicon layer 62 of active area region periphery, its with it is described
The two ends connection of polysilicon strip 61.
The gate oxide test silicon wafer of the present embodiment can be made according to the step 1 in embodiment 1 to step 8
Standby, in the present embodiment, the depth of the groove 4 is 2 μm, and width is 1 μm, and the spacing between adjacent trenches 4 is 3 μm, and
The thickness of the gate oxide 4 is 0.1 μm, and the thickness of the polysilicon layer 62 is
By polysilicon layer 62 and the two ends applied voltage of silicon substrate 1 in above-mentioned gate oxide test silicon wafer, Ke Yiyong
In the breakdown voltage of measure component grid oxidizing layer 4, and then consider and assess the quality and integrality of component grid oxidizing layer 4.Additionally,
Those skilled in the art can also proceed according to common process follow-up groove-shaped in the gate oxide test silicon wafer
The making of VDMOS device, in subsequent fabrication process, the polysilicon layer of the active area region periphery of the gate oxide test silicon wafer
Without additional other structures on 62, therefore it can be used to be carried out in each subsequent step of trench VDMOS device manufacturing process
The test of gate oxide breakdown voltage, so as to the manufacture craft to VDMOS device is monitored and improves.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
Pipe has been described in detail with reference to foregoing embodiments to the present invention, it will be understood by those within the art that：Its according to
The technical scheme described in foregoing embodiments can so be modified, or which part or all technical characteristic are entered
Row equivalent；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology
The scope of scheme.
Claims (10)
1. a kind of method for determining groove-shaped VDMOS gate oxide breakdowns voltage, it is characterised in that comprise the following steps：
Silicon substrate with epitaxial layer is provided, active area region is set on said epitaxial layer there；
Initial oxide layer is formed on the epitaxial layer of the silicon substrate；
Photoetching, etching, figure is formed on the initial oxide layer；
To form the initial oxide layer of the figure as mask is performed etching, form parallel and mutual in the active area region
Every groove, the two ends of the groove are located at the edge of the active area region；
The initial oxide layer is removed, and forms sacrificial oxide layer on said epitaxial layer there；
The sacrificial oxide layer is removed, and forms gate oxide on said epitaxial layer there；
Depositing polysilicon on gate oxide outside the groove and the groove；
The polysilicon in the active area region outside the groove is etched, gate oxide test silicon wafer is formed, its trench interiors
The two ends of polysilicon are connected with the polysilicon of active area region periphery；
By the polysilicon in the gate oxide test silicon wafer and silicon substrate two ends applied voltage, the gate oxide is determined
Breakdown voltage.
2. method according to claim 1, it is characterised in that the depth of the groove is 1.5~2.5 μm, and width is 0.6
~1 μm.
3. method according to claim 1, it is characterised in that the distance between adjacent described groove≤3 μm.
4. according to any described method of claims 1 to 3, it is characterised in that form the initial oxidation using wet oxidation
Layer, and the thickness of the initial oxide layer is 0.1~1 μm.
5. according to any described method of claims 1 to 3, it is characterised in that the thickness of the sacrificial oxide layer is
6. according to any described method of claims 1 to 3, it is characterised in that the thickness of the gate oxide is 0.05~0.2
μm。
7. according to any described method of claims 1 to 3, it is characterised in that deposited on the gate oxide outside the groove
The thickness of polysilicon be
8. a kind of gate oxide test silicon wafer, it is characterised in that including：
Silicon substrate with epitaxial layer, is set with active area region on said epitaxial layer there；
The parallel and spaced groove being arranged on inside the epitaxial layer active area region, its two ends are located at described active trivial
The edge in domain；
It is arranged on the gate oxide of the epi-layer surface；
It is arranged on the polysilicon strip of the trench interiors；
The polysilicon layer of the active area region periphery is arranged on, it is connected with the two ends of the polysilicon strip.
9. gate oxide test silicon wafer according to claim 8, it is characterised in that the depth of the groove is 1.5~2.5
μm, the width of the groove is 0.6~1 μm, spacing≤3 μm between the adjacent groove.
10. gate oxide test silicon wafer according to claim 8 or claim 9, it is characterised in that the thickness of the gate oxide is
0.05~0.2 μm, the thickness of the polysilicon layer is
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5387538A (en) * | 1992-09-08 | 1995-02-07 | Texas Instruments, Incorporated | Method of fabrication of integrated circuit isolation structure |
| US5849621A (en) * | 1996-06-19 | 1998-12-15 | Advanced Micro Devices, Inc. | Method and structure for isolating semiconductor devices after transistor formation |
| CN1194413C (en) * | 2002-09-09 | 2005-03-23 | 北京大学 | Vertical channel FET and its manufacture |
| CN103094087A (en) * | 2011-11-01 | 2013-05-08 | 上海华虹Nec电子有限公司 | Method of etching groove polycrystalline silicon gate |
-
2013
- 2013-11-20 CN CN201310589482.4A patent/CN104658937B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5387538A (en) * | 1992-09-08 | 1995-02-07 | Texas Instruments, Incorporated | Method of fabrication of integrated circuit isolation structure |
| US5849621A (en) * | 1996-06-19 | 1998-12-15 | Advanced Micro Devices, Inc. | Method and structure for isolating semiconductor devices after transistor formation |
| CN1194413C (en) * | 2002-09-09 | 2005-03-23 | 北京大学 | Vertical channel FET and its manufacture |
| CN103094087A (en) * | 2011-11-01 | 2013-05-08 | 上海华虹Nec电子有限公司 | Method of etching groove polycrystalline silicon gate |
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Effective date of registration: 20220726 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District, Cheng Fu Road, No. 298, Zhongguancun Fangzheng building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |