CN104660081A - Actively-clamped double three-level converter and loss balanced-modulation algorithm thereof - Google Patents
Actively-clamped double three-level converter and loss balanced-modulation algorithm thereof Download PDFInfo
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Abstract
An actively-clamped double three-level converter and a loss balanced-modulation algorithm thereof belong to medium-and-high-voltage frequency converters and modulation algorithms. The converter comprises a precharge circuit, an actively-clamped three-level rectifying circuit, a capacitor filtering circuit, an actively-clamped three-level inverter circuit, 36 pulse-driving circuits and a control panel, wherein the actively-clamped three-level rectifying circuit, the capacitor filtering circuit and the actively-clamped three-level inverter circuit are connected through laminated busbars; the precharge circuit is arranged at the front end of the actively-clamped three-level rectifying circuit; a controller is connected with the actively-clamped three-level rectifying circuit and the actively-clamped three-level inverter circuit through the 36 pulse-driving circuits. Through optimized selection of the redundant zero state of the actively-clamped three-level converter, the improved seven-segment space vector modulation is adopted to reduce loss of two power devices in each phase of a bridge arm, so that the voltage utilization ratio and the loading capacity of the converter can be improved, the voltage and current harmonic distortion rate is reduced, and the practical medium-and-high-voltage frequency converter is provided.
Description
Technical field
The present invention relates to a kind of medium-high voltage frequency converter and modulation algorithm, be specifically related to a kind of active clamp dual three-level frequency converter and loss balancing modulation algorithm thereof.
Background technology
Energy shortage and environmental pollution are the current common global problems faced of the mankind.China's energy is relatively poor and energy utilization rate is low, and economic growth presents extensive style, very urgent in China to effective utilization of the energy.In Eleventh Five-Year Plan, China proposes to set up resource-conserving and environment-friendly society, Development of Circular economy, realizes the conception of sustainable development.NPC three-level converter is widely used in pressure in industry, shipping industry, mining industry and traction application, but have the shortcoming failing so far to overcome to be in essence exactly that the loss of traditional NPC three-level inverter power device in running is uneven, the capacity and the power device switching frequency which greatly limits frequency converter promote.For this shortcoming of NPC three-level converter, Berlin, Germany University of Science and Technology professor T.Bruckner proposes the topological structure of active clamp three-level converter, to solve the uneven shortcoming produced with alleviation NPC of loss distribution.
Space vector modulation algorithm is a kind of pulse width modulation algorithm of multi-level frequency conversion device, compares with convention carrier pulse width modulation algorithm, has higher voltage utilization and lower percent harmonic distortion, is more applicable for the contour performance motor control strategy of vector control.At present, there is voltage utilization low, the shortcoming that percent harmonic distortion is large in active clamp three-level converter many employings carried based PWM algorithm.
Summary of the invention
The object of the invention is to provide a kind of active clamp dual three-level frequency converter and loss balancing modulation algorithm thereof, solve in frequency converter running, the unbalanced technical problem of power device loss, improves the percent harmonic distortion of voltage utilization and reduction electric current and voltage.
The object of the present invention is achieved like this: this frequency converter comprises pre-charge circuit, active clamp three level rectification circuit, capacitor filter, active clamp three-level inverter circuit, 36 road pulse driving circuit and controllers; Wherein active clamp three level rectification circuit, capacitor filter and active clamp three-level inverter circuit adopt stack bus bar to be connected, pre-charge circuit is in active clamp three level rectification circuit front end, controller comprises digital signal processor DSP and on-site programmable gate array FPGA, wherein digital signal processor DSP and on-site programmable gate array FPGA pass through bus communication, produce 36 road control waves, be connected with drive circuit by optical fiber, 36 road pulse driving circuits are connected with active clamp three level rectification circuit and active clamp three-level inverter circuit; Active clamp three level rectification circuit and the every phase brachium pontis of active clamp three-level inverter circuit are made up of six IGBT;
The loss balancing modulation algorithm of this frequency converter, comprises the following steps:
The first step, according to the difference of power factor, determines the primary and secondary nought state chosen;
Second step, first defines modulation degree
in formula: V
reffor reference voltage vector, V
dcfor direct voltage; Then according to the difference of modulation degree m, the Dynamic gene k=0.5+0.5*m determining primary and secondary nought state action time is calculated; In formula: k is Dynamic gene, m is modulation degree;
3rd step, in each carrier cycle, the action time of nought state is designated as t
0, according to the difference of Dynamic gene k, the action time of main nought state is k*t
0, the action time of secondary nought state is (1-k) * t
0;
4th step, when power factor equals 1, in a carrier cycle, chooses vector and only exists and once switch, define 6 kinds of output voltage number of state indexes and be respectively 1-6; When nought state and P-state switch, employing vector order is: [4 → 3 → 1 → 1 → 3 → 4], and when N state and nought state switch, employing vector order is: [6 → 2 → 5 → 5 → 2 → 6];
5th step, according to sequence of operation and the action time of vector, produces gate electrode drive signals, switches transducer power device.
Beneficial effect, owing to have employed technique scheme, active clamp dual three-level frequency converter of the present invention and loss balancing modulation algorithm thereof are compared with traditional NPC three-level converter, the loss of inner two power devices of every phase brachium pontis can be reduced, thus make inner two the power device losses of every phase brachium pontis lower, the load capacity of frequency converter and the lifting of switching frequency can be improved; Compare with conventional active clamper three-level converter carried based PWM algorithm, improve the voltage utilization of frequency converter, reduce the percent harmonic distortion of electric current and voltage.
Accompanying drawing explanation
Fig. 1 is the system construction drawing of active clamp dual three-level frequency converter of the present invention.
Fig. 2 is active clamp tri-level inversion side structure figure of the present invention.
Fig. 3 is active clamp three level fundamental space polar plot of the present invention.
Fig. 4 is the SVPWM waveform of community, NPC three level seven segmentation of the present invention first district first.
Fig. 5 is the SVPWM waveform of community, active clamp three level loss balancing of the present invention first district first.
Embodiment
Below in conjunction with accompanying drawing, one embodiment of the present of invention are further described;
Fig. 1 is the system construction drawing of active clamp dual three-level frequency converter of the present invention, and this frequency converter comprises pre-charge circuit, active clamp three level rectification circuit, capacitor filter, active clamp three-level inverter circuit, 36 road pulse driving circuits and DSP+FPGA control board; Active clamp three level rectification circuit, capacitor filter and active clamp three-level inverter circuit adopt stack bus bar to be connected, pre-charge circuit is in active clamp three level rectification circuit front end, controller comprises digital signal processor DSP and on-site programmable gate array FPGA, wherein digital signal processor DSP and on-site programmable gate array FPGA pass through bus communication, produce 36 road control waves, be connected with drive circuit by optical fiber, 36 road pulse driving circuits are connected with active clamp three level rectification circuit and active clamp three-level inverter circuit; Active clamp three level rectification circuit and the every phase brachium pontis of active clamp three-level inverter circuit are made up of six IGBT;
Active clamp dual three-level frequency converter loss balancing space vector modulation algorithm is as follows:
The first step, according to the difference of power factor, determine the primary and secondary nought state chosen:
As shown in Figure 2, the every phase brachium pontis of active clamp three-level converter has 6 power devices, and therefore nought state has four kinds of output modes: OU1, OU2, OL1, OL2, and the on off state of A phase and output voltage are in table 1.
Table 1 ANPC three-level converter on off state
The loss distribution situation of active clamp three-level converter power device is subject to the impact of modulation degree m and power factor pf: in different modulation degree m situations, varying in size of load current, and then affects the loss distribution of power device; When power factor pf is different, can affect the flow direction of load current and the conducting of device and switching, when pf equals 1 or-1, the loss skewness of ANPC converter is more remarkable, and therefore the present invention only considers boundary condition.
As shown in table 1, the commutation mode switched between output state P and O has 4 kinds:
with
the switching of output state N and O equally also has four kinds.In often kind of situation, the loss of power device is not identical, therefore the action time of reasonable distribution nought state, and the loss balancing that just can realize power device controls.Although active clamp three-level converter has multiple power device participation work under various commutation mode, the device producing switching loss in essence only has two, and power device conducting when load current is positive and negative and switching are respectively as shown in tables 2 and 3.
Table 2 electric current is timing change of current device
Table 3 electric current is change of current device time negative
The change of current provided in table 2 and table 3 can be divided into 4 classes according to the difference of the sense of current: mode 1: positive voltage negative current; Mode 2: positive voltage positive current; Mode 3: negative voltage positive current; Mode 4: negative voltage negative current.
For active clamp three-level converter, when power factor be 1, modulation degree higher time, the T of every phase brachium pontis
2and T
3heating is the most serious, and loss is maximum.In order to address this problem, the reduction T that try one's best
2and T
3on-state loss, according to the difference of power factor, action time of four kinds of modes is also different: when 0≤pf≤1, mode 2 and mode 4 longer for action time, when-1≤pf≤0, mode 1 and mode 3 longer for action time.
In order to the loss of balance power device, during mode 1, first nought state chooses OU2, and next chooses OL1; During mode 2, first nought state chooses OL1, and next chooses OU2; During mode 3, first nought state chooses OL2, and next chooses OU1; During mode 4, first nought state chooses OU1, and next chooses OL2, and the primary and secondary nought state chosen is as shown in table 4.
Table 4 primary and secondary nought state
Second step, according to the difference of modulation degree m, calculates the Dynamic gene k determining primary and secondary nought state action time:
In order to the loss of balance power device, under different modes, the ON time of two kinds of nought states is determined by modulation degree m and power factor pf.Wherein, modulation degree
in formula: V
reffor reference voltage vector, V
dcfor direct voltage.When power factor is 1, an existing way 2 and mode 4 two kinds of changes of current, in a carrier cycle T, the ON time of first brachium pontis power device of A phase is as shown in table 5.
Switch device conductive time during table 5 pf=1
As shown in Table 5, the ON time of device is determined by modulation degree m and k.When k increases, T
2, D
5oN time reduce, T
5, D
2oN time increase, T
1, D
1oN time constant.Along with the increase of modulation degree, T
2loss is higher, and heating is comparatively serious, therefore wants its ON time of corresponding reduction.In different modulation degree situations, in order to balance power device loss, the value of k is different, and when modulation degree is lower, power device loss is lower, and in order to simplify calculating, the relation of k and modulation degree m is such as formula shown in (1).
k＝0.5+0.5*m (1)
3rd step, determine the action time of primary and secondary nought state:
For active clamp three-level converter, often have 6 kinds of on off states mutually, therefore frequency converter has 216 kinds of on off states.
In alpha-beta plane, as shown in Figure 3, wherein X to represent in four kinds of nought states any one to the polar plot corresponding to active clamp three-level converter on off state.Be divided into 6 large regions, each large regions is divided into again 6 zonules, the difference in region residing for reference voltage, and can be synthesized by different voltage vectors, voltage vector is divided into four classes: zero vector (V
0), short vector (V
1-V
6), middle vector (V
7-V
12) and long vector (V
13-V
18).
Action time and the on off sequence of active clamp three-level converter vector can obtain according to NPC, in order to balancing loss, need to choose different nought states.Adopt Central Symmetry seven segmentation SVPWM, for community, first district first, on off sequence is as shown in table 6.Every switching that only there is nought state and P-state mutually, or the switching of N state and nought state as seen from table.
In each carrier cycle, the action time of nought state is designated as t
0, according to the difference of Dynamic gene k, the action time of main nought state is k*t
0, the action time of secondary nought state is (1-k) * t
0.
Table 6 first district first community seven segmentation on off sequence
4th step, determine the switching sequence in each carrier cycle:
NPC three level seven segmentation SVPWM waveform as shown in Figure 4, active clamp three-level converter loss balancing SVPWM waveform as shown in Figure 5, calculate the nought state resultant action time, unification distributes, when nought state and P-state switch, employing vector order is: [4 → 3 → 1 → 1 → 3 → 4], and when N state and nought state switch, employing vector order is: [6 → 2 → 5 → 5 → 2 → 6].
5th step, according to sequence of operation and the action time of vector, produces gate electrode drive signals, switches transducer power device.
More than describe the present invention in detail.Should be appreciated that the ordinary skill of this area just design according to the present invention can make many modifications and variations without the need to creative work.Therefore, all technical staff in the art, all should by the determined protection range of claims under this invention's idea on the basis of existing technology by the technical scheme that logic analysis, reasoning obtain.
Claims (2)
1. an active clamp dual three-level frequency converter, is characterized in that: this frequency converter comprises pre-charge circuit, active clamp three level rectification circuit, capacitor filter, active clamp three-level inverter circuit, 36 road pulse driving circuit and controllers; Wherein active clamp three level rectification circuit, capacitor filter and active clamp three-level inverter circuit adopt stack bus bar to be connected, pre-charge circuit is in active clamp three level rectification circuit front end, controller comprises digital signal processor DSP and on-site programmable gate array FPGA, wherein digital signal processor DSP and on-site programmable gate array FPGA pass through bus communication, produce 36 road control waves, be connected with drive circuit by optical fiber, 36 road pulse driving circuits are connected with active clamp three level rectification circuit and active clamp three-level inverter circuit; Active clamp three level rectification circuit and the every phase brachium pontis of active clamp three-level inverter circuit are made up of six IGBT.
2. the loss balancing modulation algorithm of a kind of active clamp dual three-level frequency converter according to claim 1, is characterized in that, comprise the following steps:
The first step, according to the difference of power factor, determines the primary and secondary nought state chosen;
Second step, first defines modulation degree
in formula: V
reffor reference voltage vector, V
dcfor direct voltage; Then according to the difference of modulation degree m, the Dynamic gene k=0.5+0.5*m determining primary and secondary nought state action time is calculated; In formula: k is Dynamic gene, m is modulation degree;
3rd step, in each carrier cycle, the action time of nought state is designated as t
0, according to the difference of Dynamic gene k, the action time of main nought state is k*t
0, the action time of secondary nought state is (1-k) * t
0;
4th step, when power factor equals 1, in a carrier cycle, chooses vector and only exists and once switch, define 6 kinds of output voltage number of state indexes and be respectively 1-6; When nought state and P-state switch, employing vector order is: [4 → 3 → 1 → 1 → 3 → 4], and when N state and nought state switch, employing vector order is: [6 → 2 → 5 → 5 → 2 → 6];
5th step, according to sequence of operation and the action time of vector, produces gate electrode drive signals, switches transducer power device.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105337524A (en) * | 2015-11-25 | 2016-02-17 | 安徽大学 | Balance control method for tri-level active neutral point clamped photovoltaic inverter switching losses |
| CN108377104A (en) * | 2018-03-15 | 2018-08-07 | 浙江大学 | A kind of space vector control method applied to mixed type three-phase tri-level active neutral point clamped multi converter |
| CN108387830A (en) * | 2018-01-16 | 2018-08-10 | 中国矿业大学 | A kind of IGBT overcurrent detecting devices and method based on active clamp feedback-type |
| CN110912134A (en) * | 2019-11-29 | 2020-03-24 | 中国船舶重工集团公司第七一九研究所 | Multi-level active power filter with low harmonic content |
| CN113765428A (en) * | 2021-08-31 | 2021-12-07 | 河北科技大学 | Active neutral point clamped three-level converter and regulation and control method thereof |
| WO2024077942A1 (en) * | 2022-10-12 | 2024-04-18 | 阳光电源股份有限公司 | Loss-balanced modulation method for anpc topology and converter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6411067B1 (en) * | 2001-02-20 | 2002-06-25 | Abb Ab | Voltage source converters operating either as back-to-back stations or as parallel static var compensators |
| CN1393049A (en) * | 2000-09-13 | 2003-01-22 | Abb研究有限公司 | Controlling and regulating method for three level power converter having active clamping switches, and device therefor |
| CN101013818A (en) * | 2007-02-07 | 2007-08-08 | 哈尔滨九洲电气股份有限公司 | Three-level medium voltage converter for megawatt wind power generation |
| CN101714816A (en) * | 2008-09-30 | 2010-05-26 | 洛克威尔自动控制技术股份有限公司 | Power electronic module pre-charge system and method |
-
2015
- 2015-01-26 CN CN201510039365.XA patent/CN104660081B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1393049A (en) * | 2000-09-13 | 2003-01-22 | Abb研究有限公司 | Controlling and regulating method for three level power converter having active clamping switches, and device therefor |
| US6411067B1 (en) * | 2001-02-20 | 2002-06-25 | Abb Ab | Voltage source converters operating either as back-to-back stations or as parallel static var compensators |
| CN101013818A (en) * | 2007-02-07 | 2007-08-08 | 哈尔滨九洲电气股份有限公司 | Three-level medium voltage converter for megawatt wind power generation |
| CN101714816A (en) * | 2008-09-30 | 2010-05-26 | 洛克威尔自动控制技术股份有限公司 | Power electronic module pre-charge system and method |
Non-Patent Citations (3)
| Title |
|---|
| 邵章平等: "基于DSP和CPLD的三电平背靠背变流器研究", 《电力电子技术》 * |
| 郑宏等: "双馈电机双三电平调速系统的研究", 《科技广场》 * |
| 郝琦: "有源钳位逆变器最小开关损耗调制策略的研究", 《机车电传动》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105337524A (en) * | 2015-11-25 | 2016-02-17 | 安徽大学 | Balance control method for tri-level active neutral point clamped photovoltaic inverter switching losses |
| CN105337524B (en) * | 2015-11-25 | 2018-06-29 | 安徽大学 | Three level active neutral-point-clamped photovoltaic DC-to-AC converter switching loss balance control methods |
| CN108387830A (en) * | 2018-01-16 | 2018-08-10 | 中国矿业大学 | A kind of IGBT overcurrent detecting devices and method based on active clamp feedback-type |
| CN108377104A (en) * | 2018-03-15 | 2018-08-07 | 浙江大学 | A kind of space vector control method applied to mixed type three-phase tri-level active neutral point clamped multi converter |
| CN108377104B (en) * | 2018-03-15 | 2020-02-28 | 浙江大学 | Space vector control method applied to hybrid three-phase three-level active neutral point clamped converter |
| CN110912134A (en) * | 2019-11-29 | 2020-03-24 | 中国船舶重工集团公司第七一九研究所 | Multi-level active power filter with low harmonic content |
| CN113765428A (en) * | 2021-08-31 | 2021-12-07 | 河北科技大学 | Active neutral point clamped three-level converter and regulation and control method thereof |
| CN113765428B (en) * | 2021-08-31 | 2023-09-05 | 河北科技大学 | Active neutral point clamped three-level converter and regulation and control method thereof |
| WO2024077942A1 (en) * | 2022-10-12 | 2024-04-18 | 阳光电源股份有限公司 | Loss-balanced modulation method for anpc topology and converter |
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