CN104716032A - 使用间隔件双重图案化印刷多个结构宽度的方法 - Google Patents

使用间隔件双重图案化印刷多个结构宽度的方法 Download PDF

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CN104716032A
CN104716032A CN201410772816.6A CN201410772816A CN104716032A CN 104716032 A CN104716032 A CN 104716032A CN 201410772816 A CN201410772816 A CN 201410772816A CN 104716032 A CN104716032 A CN 104716032A
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CN104716032B (zh
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金勇韩
崔尹升
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Texas Instruments Inc
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Abstract

本申请案涉及一种使用间隔件双重图案化印刷多个结构宽度的方法。可通过以下方式形成含有按规则间距的线性结构(104)及(106)的集成电路(100)：在用于线性结构的材料层(146)上方以为所要线性结构的间距的两倍的心轴间距形成线性心轴。缩短用于第一多个线性结构(104)的心轴。在心轴上方保形地形成间隔件材料层，且各向异性地凹蚀间隔件材料层以形成心轴的横向表面上的间隔件(136)及(138)。经缩短心轴上的间隔件(136)由于各向异性凹蚀而比未经缩短心轴上的间隔件(138)窄。移除心轴，从而使间隔件(136)及(138)留在适当位置中以形成用于线性结构的基于间隔件的蚀刻掩模(144)。使用基于间隔件的蚀刻掩模(144)蚀刻用于线性结构(104)及(106)的材料层(146)以形成线性结构。来自经缩短心轴的线性结构(104)具有低于来自未经缩短心轴的线性结构(106)的宽度。

Description

使用间隔件双重图案化印刷多个结构宽度的方法
技术领域
本发明涉及集成电路的领域。更特定来说，本发明涉及集成电路中的MOS晶体管。
背景技术
集成电路可含有具有小于30纳米的栅极长度及小于100纳米的栅极间距的金属氧化物半导体(MOS)晶体管。举例来说在一些逻辑电路或静态随机存取存储器(SRAM)单元中，使一些栅极具有比其它栅极窄的宽度可为合意的。用于形成所述栅极的光刻过程可使用照射源，举例来说可能无法以所要间距及宽度印刷用于所述栅极的蚀刻掩模的193纳米氟化氩准分子激光器。形成用于所述栅极的所述蚀刻掩模的一种方法是执行两个或两个以上图案化步骤，从而在每一图案化步骤中图案化所述栅极的子集。双重或多重图案化可印刷具有两种不同宽度的栅极，但额外图案化不合意地增加所述集成电路的制作成本及过程复杂度。另一方法是由沉积于心轴上方的间隔件层形成栅极蚀刻掩模。可在一个图案化步骤中印刷用于所有所述栅极的所述心轴的蚀刻掩模。然而，由所述所沉积间隔件层的厚度确定所述栅极蚀刻掩模的栅极长度，且因此形成具有两种不同宽度的栅极可是成问题的。可关于含有具有鳍片的鳍片场效晶体管(finFET)的集成电路记录对小于光学光刻过程的单一图案化能力的间距的类似限制。形成具有两种不同鳍片宽度的鳍片可是成问题的。
发明内容
下文呈现简化发明内容以便提供对本发明的一或多个方面的基本理解。本发明内容并非本发明的扩展概述，且既不打算识别本发明的关键或紧要元件，也不打算记述其范围。而是，本发明内容的主要目的为以简化形式呈现本发明的一些概念作为稍后所呈现的更详细说明的前言。
可通过以下方式形成含有按规则间距且具有拥有第一宽度的第一多个线性特征及拥有第二宽度的第二多个线性结构的线性结构的集成电路，其中所述第一宽度小于所述第二宽度：在用于所述线性结构的材料层上方形成线性心轴。所述心轴形成有为所述线性结构的所述间距的两倍的间距。缩短用于所述第一多个线性结构的心轴。在所述心轴上方保形地形成间隔件材料层且各向异性地凹蚀所述间隔件材料层以形成所述心轴的横向表面上的间隔件。在所述经缩短心轴(也就是所述第一多个线性结构的心轴)上的间隔件由于所述各向异性凹蚀而比在未经缩短心轴(也就是所述第二多个线性结构的心轴)上的间隔件窄。移除所述心轴，从而使所述间隔件留在适当位置中以形成用于所述线性结构的基于间隔件的蚀刻掩模。使用所述基于间隔件的蚀刻掩模蚀刻用于所述线性结构的所述材料层以形成具有拥有所要相应宽度的所述第一多个线性结构及所述第二多个线性结构的所述线性结构。
附图说明
图1A到图1I是含有通过实例性过程序列形成的平面MOS晶体管的集成电路的横截面，其是以连续制作阶段描绘的。
图2A到图2H是含有通过另一实例性过程序列形成的finFET的集成电路的横截面，其是以连续制作阶段描绘的。
图3A到图3H是含有通过又一实例性过程序列形成的finFET的集成电路的横截面，其是以连续制作阶段描绘的。
具体实施方式
参考附图描述本发明。所述图未按比例绘制且其仅经提供以图解说明本发明。下文参考用于图解说明的实例应用来描述本发明的几个方面。应理解，众多特定细节、关系及方法经陈述以提供对本发明的理解。然而，所属领域的技术人员将容易地认识到，可在不使用所述特定细节中的一或多者或者使用其它方法的情况下实践本发明。在其它实例中，未详细展示众所周知的结构或操作以避免使本发明模糊。本发明不受动作或事件的所图解说明排序限制，这是因为一些动作可以不同次序发生及/或与其它动作或事件同时发生。此外，并非需要所有所图解说明动作或事件来实施根据本发明的方法。
以下申请案含有相关材料且据此以其全文并入：与本申请案同时提出申请的标题为“finFET装置的设计及集成(DESIGN AND INTEGRATION OF FINFET DEVICE)”的申请案xx/xxx，xxx(代理人档案号为TI-72131)。
可通过以下方式形成含有按规则间距且具有拥有第一宽度的第一多个线性特征及拥有第二宽度的第二多个线性结构的线性结构的集成电路，其中所述第一宽度小于所述第二宽度：在用于所述线性结构的材料层上方形成线性心轴。所述心轴形成有为栅极的所要间距的两倍的间距。缩短用于所述第一多个线性结构的心轴。在所述心轴上方保形地形成间隔件材料层且各向异性地凹蚀所述间隔件材料层以形成所述心轴的横向表面上的间隔件。在所述经缩短心轴(也就是所述第一多个线性结构的心轴)上的间隔件由于所述各向异性凹蚀而比在未经缩短心轴(也就是所述第二多个线性结构的心轴)上的间隔件窄。移除所述心轴，从而使所述间隔件留在适当位置中以形成用于所述线性结构的基于间隔件的蚀刻掩模。使用所述基于间隔件的蚀刻掩模蚀刻用于所述线性结构的所述材料层以形成具有拥有所要相应宽度的所述第一多个线性结构及所述第二多个线性结构的所述线性结构。
形成如所描述的所述线性结构可有利地以低于使用运用双重图案化的过程序列的集成电路制作成本提供具有第一较窄的宽度的所述第一多个线性特征及具有第二较宽的宽度的所述第二多个线性结构。
所述集成电路的一个版本可含有平面MOS晶体管，其中用于所述线性结构的所述材料层为栅极材料层，且所述线性结构为所述MOS晶体管的栅极，所述栅极具有拥有第一宽度的第一多个栅极及拥有第二宽度的第二多个栅极，其中所述第一宽度小于所述第二宽度。可形成按规则间距的所述栅极。
所述集成电路的另一版本可含有finFET，其中用于所述线性结构的所述材料层为在所述集成电路的衬底的顶部处的半导体材料，且所述线性结构为所述finFET的鳍片，所述鳍片具有拥有第一鳍片宽度的第一多个鳍片及拥有第二鳍片宽度的第二多个鳍片，其中所述第一鳍片宽度小于所述第二鳍片宽度。可形成按规则间距的所述鳍片。出于本发明的目的，如适用于栅极的术语宽度指代所述栅极沿在所述栅极下方的沟道区中的电流流动方向的物理宽度。出于本发明的目的，术语“间距”指代例如栅极、鳍片或心轴的相同结构的邻近实例的中心之间的横向距离。
所述集成电路的又一版本可含有finFET，其中用于所述线性结构的所述材料层为栅极材料层，且所述线性结构为所述finFET的栅极，所述栅极具有拥有第一宽度的第一多个栅极及拥有第二宽度的第二多个栅极，其中所述第一宽度小于所述第二宽度。可形成按规则间距的所述栅极。
图1A到图1I是含有通过实例性过程序列形成的平面MOS晶体管的集成电路的横截面，其是按连续制作阶段描绘的。参考图1A，在例如硅晶片的衬底102上形成集成电路100。集成电路100包含用于MOS晶体管的第一多个栅极104的至少一个区域及用于MOS晶体管的第二多个栅极106的至少一个区域。将形成的第一多个栅极104的所要宽度小于将形成的第二多个栅极106的所要宽度。可在衬底102的顶部表面处形成场氧化物108以横向隔离例如晶体管的组件。在衬底102的顶部表面处在用于第一多个栅极104的区域及用于第二多个栅极106的区域中形成栅极电介质层110。
在栅极电介质层110上方形成栅极材料层112。举例来说，栅极材料层112可包含20纳米到50纳米的多晶体硅(通常称为多晶硅)，及/或可包含例如氮化钛或氮化钽的金属栅极材料。在栅极材料层112上方以为第一多个栅极104及第二多个栅极106的栅极的所要间距的两倍长的间距116形成心轴114。心轴114可形成有提供第一多个栅极104及第二多个栅极106的邻近实例之间的所要分离的宽度118。心轴114的实例有可能延伸越过用于第一多个栅极104的区域或用于第二多个栅极106的区域的边界，如图1A中所描绘。举例来说，心轴114可包含二氧化硅及/或氮化硅，且通过以下方式而形成：在栅极材料层112上方形成心轴材料层；在心轴材料层上形成光致抗蚀剂的蚀刻掩模；及使用反应离子蚀刻(RIE)过程蚀刻心轴材料。替代地，心轴114可使用光学光刻过程由光敏聚酰亚胺形成。心轴114的其它材料及形成方法都在本实例的范围内。举例来说，心轴114的高度120可为第二多个栅极106的所要宽度的两倍到四倍。
参考图1B，在心轴114及栅极材料层112上方形成掩模材料层122。举例来说，掩模材料层122可包含用作底部抗反射涂层(BARC)的有机聚合物，或可包含用于更耐用掩模的非晶碳。在暴露用于第一多个栅极104的区域且覆盖用于第二多个栅极106的区域的掩模材料层122上方形成光致抗蚀剂图案124。可使用低分辨率过程形成光致抗蚀剂图案124，此有利地减少集成电路100的制作成本。
参考图1C，在由光致抗蚀剂图案124暴露的区域(包含用于第一多个栅极104的区域)中移除掩模材料层122，且将其留在由光致抗蚀剂图案124覆盖的区域(包含用于第二多个栅极106的区域)中。举例来说，可通过对于心轴114及栅极材料层112来说具选择性的各向异性等离子体蚀刻过程或RIE过程移除掩模材料层122。可随后移除光致抗蚀剂图案124，或可使其留在适当位置中。
参考图1D，举例来说，通过各向异性蚀刻缩短在第一多个栅极104的区域中的心轴114的实例126。所述缩短过程可不实质上减小在第一多个栅极104的区域中的心轴114的实例126的宽度118。在第二多个栅极106的区域中的心轴114的实例128受掩模材料层122保护且因此实质上不受缩短过程影响。在完成缩短过程之后，在第一多个栅极104的区域中的心轴114的实例126可比在第二多个栅极106的区域中的心轴114的实例128短(举例来说)为将形成的第二多个栅极106的所要宽度的一倍到三倍的垂直距离130。在完成缩短过程之后，移除掩模材料层122。可使用实质上不使心轴114或栅极材料层112降级的蚀刻过程移除掩模材料层122。可使用灰化过程移除掩模材料层122中的有机材料。可使用各项同性等离子体蚀刻过程移除掩模材料层122中的无机材料。
参考图1E，在心轴114及栅极材料层112上方保形地形成间隔件材料层132。举例来说，间隔件材料层132可包含二氧化硅或氮化硅。在心轴114的横向表面上的间隔件材料层132的水平厚度134大约为将形成的第二多个栅极106的所要宽度。
参考图1F，各向异性地凹蚀图1E的间隔件材料层132以形成在于第一多个栅极104的区域中的心轴114的实例126上的第一多个间隔件136且形成在于第二多个栅极106的区域中的心轴114的实例128上的第二多个间隔件138。执行各向异性凹蚀以使得第一多个间隔件136的水平厚度140小于第二多个间隔件138的水平厚度142。第一多个间隔件136的水平厚度140大约为将形成的第一多个栅极104的所要宽度。第二多个间隔件138的水平厚度142大约为将形成的第二多个栅极106的所要宽度。
参考图1G，移除图1F的心轴114，从而使第一多个间隔件136及第二多个间隔件138留在适当位置中以形成基于间隔件的蚀刻掩模144。可使用对于间隔件136及138以及栅极材料层112来说具选择性的湿式蚀刻移除心轴114。举例来说，可使用缓冲氢氟酸的稀释水蚀刻从基于氮化硅的间隔件136及138以及多晶硅的栅极材料层112移除心轴114中的二氧化硅。在另一实例中，可使用灰化过程后续接着湿式清洁步骤(使用硫酸及过氧化氢的水混合物)从基于二氧化硅的间隔件136及138以及多晶硅的栅极材料层112移除心轴114中的聚酰亚胺。
参考图1H，使用基于间隔件的蚀刻掩模144蚀刻图1G的栅极材料层112以形成包含第一多个栅极104及第二多个栅极106的栅极146。第一多个栅极104的宽度148小于第二多个栅极106的宽度150。可在场氧化物108上方形成栅极146的实例，结果是按实质上恒定间距形成栅极146。
参考图1I，移除图1H的基于间隔件的蚀刻掩模144，从而使栅极146留在适当位置中。可使用对于栅极146来说具选择性的蚀刻过程移除基于间隔件的蚀刻掩模144。可在可能用旋涂涂布保护栅极电介质层110之后使用缓冲氢氟酸的稀释水蚀刻移除基于间隔件的蚀刻掩模144中的二氧化硅。可使用借助氟自由基的等离子体蚀刻移除基于间隔件的蚀刻掩模144中的氮化硅。在后续处理中有可能用金属栅极替换栅极146。
图2A到图2H是含有通过另一实例性过程序列形成的finFET的集成电路的横截面，其是以连续制作阶段描述的。参考图2A，在于顶部表面处具有半导体材料的衬底202(例如硅晶片)上形成集成电路200。集成电路200包含用于finFET的第一多个鳍片204的至少一个区域及用于finFET的第二多个鳍片206的至少一个区域。将形成的第一多个鳍片204的所要宽度小于将形成的第二多个鳍片206的所要宽度。
在衬底202上方以为第一多个鳍片204及第二多个鳍片206的鳍片的所要间距的两倍长的间距216形成心轴214。心轴214可形成有提供第一多个鳍片204及第二多个鳍片206的邻近实例之间的所要分离的宽度218。心轴214可包含二氧化硅或聚酰亚胺且如参考图1A所描述而形成。心轴214的其它材料及形成方法都在本实例的范围内。举例来说，心轴214的高度可为第二多个鳍片206的所要宽度的两倍到四倍。
参考图2B，在心轴214上方形成暴露用于第一多个鳍片204的区域且覆盖用于第二多个鳍片206的区域的蚀刻掩模222。在一个实例中，蚀刻掩模222可包含光致抗蚀剂且通过光学光刻过程形成。在另一实例中，蚀刻掩模222可包含非光敏材料且如参考图1B及图1C所描述而形成。可使用低分辨率过程形成蚀刻掩模222，此有利地减少集成电路200的制作成本。
参考图2C，举例来说，通过各向异性蚀刻缩短在第一多个鳍片204的区域中的心轴214的实例226。所述缩短过程可不实质上减小在第一多个鳍片204的区域中的心轴214的实例226的宽度218。在第二多个鳍片206的区域中的心轴214的实例228受蚀刻掩模222保护且因此实质上不受缩短过程影响。在完成缩短过程之后，在第一多个鳍片204的区域中的心轴214的实例226可比在第二多个鳍片206的区域中的心轴214的实例228短(举例来说)为将形成的第二多个鳍片206的所要宽度的一倍到三倍的垂直距离230。
在完成缩短过程之后，移除蚀刻掩模222。可使用实质上不使心轴214或衬底202降级的蚀刻过程移除蚀刻掩模222。可使用灰化过程或湿式清洁过程(使用硫酸及过氧化氢的水溶液)移除蚀刻掩模层222中的有机材料。可使用各项同性等离子体蚀刻过程或氢氟酸的水缓冲溶液移除蚀刻掩模222中的二氧化硅。可使用各项同性等离子体蚀刻过程移除蚀刻掩模222中的氮化硅。
参考图2D，在心轴214及栅极材料层212上方保形地形成间隔件材料层232。举例来说，间隔件材料层232可包含二氧化硅或氮化硅。在心轴214的横向表面上的间隔件材料层232的水平厚度234大约为将形成的第二多个鳍片206的所要宽度。
参考图2E，各向异性地凹蚀图2D的间隔件材料层232以形成在于第一多个鳍片204的区域中的心轴214的实例226上的第一多个间隔件236且形成在于第二多个鳍片206的区域中的心轴214的实例228上的第二多个间隔件238。执行各向异性凹蚀以使得第一多个间隔件236的水平厚度240小于第二多个间隔件238的水平厚度242。第一多个间隔件236的水平厚度240大约为将形成的第一多个鳍片204的所要宽度。第二多个间隔件238的水平厚度242大约为将形成的第二多个鳍片206的所要宽度。
参考图2F，移除图2E的心轴214，从而使第一多个间隔件236及第二多个间隔件238留在适当位置中以形成基于间隔件的蚀刻掩模244。可使用对于间隔件236及238以及衬底202来说具选择性的湿式蚀刻移除心轴214。举例来说，可使用缓冲氢氟酸的稀释水蚀刻移除心轴214中的二氧化硅。在另一实例中，可使用灰化过程后续接着湿式清洁步骤(使用硫酸及过氧化氢的水混合物)移除心轴214中的聚酰亚胺。
参考图2G，使用基于间隔件的蚀刻掩模244蚀刻图2F的衬底202以形成包含第一多个鳍片204及第二多个鳍片206的鳍片246。第一多个鳍片204的宽度248小于第二多个鳍片206的宽度250。所述蚀刻过程可为时间蚀刻以提供鳍片246的所要高度。
参考图2H，移除图2G的基于间隔件的蚀刻掩模244，从而使鳍片246留在适当位置中。可使用对于衬底202及鳍片246的半导体材料来说具选择性的蚀刻过程移除基于间隔件的蚀刻掩模244。可使用缓冲氢氟酸的稀释水蚀刻移除基于间隔件的蚀刻掩模244中的二氧化硅。可使用借助氟自由基的等离子体蚀刻移除基于间隔件的蚀刻掩模244中的氮化硅。作为场氧化物形成的部分，可在衬底202上于鳍片246之间形成隔离氧化物252。
图3A到图3H是含有通过又一实例性过程序列形成的finFET的集成电路的横截面，其是按连续制作阶段描述的。参考图3A，在于顶部表面上具有半导体材料的衬底302(例如硅晶片)上形成集成电路300。在衬底302的顶部表面处形成鳍片354。可在衬底302上方于鳍片354之间形成隔离氧化物352。集成电路300包含用于finFET的第一多个鳍片304的至少一个区域及用于finFET的第二多个鳍片306的至少一个区域。将形成的第一多个鳍片304的所要宽度小于将形成的第二多个鳍片306的所要宽度。
参考图3B，在鳍片354上方形成向下延伸到隔离氧化物352的栅极材料层312。栅极材料层312可包含多晶硅，及/或可包含例如氮化钛或氮化钽等金属栅极材料。栅极材料层312覆盖鳍片354。
在栅极材料层312上方以为第一多个栅极304及第二多个栅极306的栅极的所要间距的两倍长的间距316形成心轴314。心轴314可形成有提供第一多个栅极304及第二多个栅极306的邻近实例之间的所要分离的宽度318。举例来说，心轴314可包含二氧化硅及/或氮化硅，且通过以下方式而形成：在栅极材料层312上方形成心轴材料层；在心轴材料层上形成光致抗蚀剂的蚀刻掩模；及使用RIE过程蚀刻心轴材料。替代地，心轴314可使用光学光刻过程由光敏聚酰亚胺形成。心轴314的其它材料及形成方法都在本实例的范围内。举例来说，心轴314的高度可为第二多个栅极306的所要宽度的两倍到四倍。
参考图3C，缩短在第一多个栅极304的区域中的心轴314的实例326，举例来说如参考图1B到图1D所描述。所述缩短过程可不实质上减小在第一多个栅极304的区域中的心轴314的实例326的宽度318。在第二多个栅极306的区域中的心轴314的实例328受掩模材料层322保护且因此实质上不受缩短过程影响。在完成缩短过程之后，在第一多个栅极304的区域中的心轴314的实例326可比在第二多个栅极306的区域中的心轴314的实例328短(举例来说)为将形成的第二多个栅极306的所要宽度的一倍到三倍的垂直距离330。
参考图3D，在心轴314及栅极材料层312上方保形地形成间隔件材料层332。举例来说，间隔件材料层332可包含二氧化硅或氮化硅。在心轴314的横向表面上的间隔件材料层332的水平厚度334大约为将形成的第二多个栅极306的所要宽度。
参考图3E、图3E-1及图3E-2，各向异性地凹蚀图3D的间隔件材料层332以形成在于第一多个栅极304的区域中的心轴314的实例326上的第一多个间隔件336且形成在于第二多个栅极306的区域中的心轴314的实例328上的第二多个间隔件338。执行各向异性凹蚀以使得第一多个间隔件336的水平厚度340小于第二多个间隔件338的水平厚度342。第一多个间隔件336的水平厚度340大约为将形成的第一多个栅极304的所要宽度。第二多个间隔件338的水平厚度342大约为将形成的第二多个栅极306的所要宽度。
参考图3F，移除图3E的心轴314，从而使第一多个间隔件336及第二多个间隔件338留在适当位置中以形成基于间隔件的蚀刻掩模344。举例来说，可移除心轴314，如参考图1G所描述。
参考图3G，使用基于间隔件的蚀刻掩模344蚀刻图3F的栅极材料层312以形成包含第一多个栅极304及第二多个栅极306的栅极346。第一多个栅极304的宽度348小于第二多个栅极306的宽度350。
参考图3H，移除图3G的基于间隔件的蚀刻掩模344，从而使栅极346留在适当位置中。可使用对于栅极346来说具选择性的蚀刻过程移除基于间隔件的蚀刻掩模344。可在可能用旋涂涂布保护栅极电介质层310之后使用缓冲氢氟酸的稀释水蚀刻移除基于间隔件的蚀刻掩模344中的二氧化硅。可使用借助氟自由基的等离子体蚀刻移除基于间隔件的蚀刻掩模344中的氮化硅。在后续处理中有可能用金属栅极替代栅极346。
尽管上文已描述本发明的各种实施例，但应理解，所述实施例仅通过实例而非限制的方式呈现。在不背离本发明的精神或范围的情况下，可根据本文中的揭示内容对所揭示实施例做出众多改变。因此，本发明的广度及范围不应受上文所描述的实施例中的任一者限制。而是，本发明的范围应根据所附权利要求书及其等效物来界定。

Claims (20)

1.一种形成集成电路的方法，其包括以下步骤：
提供用于线性结构的材料层；
在用于所述线性结构的所述材料层上方形成多个心轴，所述心轴具有为所述线性结构的所要间距的两倍长的间距；
缩短所述多个所述心轴中的在用于第一多个所述线性结构的区域中的第一组心轴，使得所述多个所述心轴中的在用于第二多个所述线性结构的区域中的第二组心轴实质上不被缩短；
在所述第一组所述心轴、所述第二组所述心轴及用于所述线性结构的所述材料层上方保形地形成间隔件材料层；
各向异性地凹蚀所述间隔件材料层以形成用于所述第一多个所述线性结构的所述区域中的所述第一组所述心轴上的第一多个间隔件，且形成用于所述第二多个所述线性结构的所述区域中的所述第二组所述心轴上的第二多个间隔件，使得所述第一多个间隔件的水平厚度小于所述第二多个间隔件的水平厚度；
移除所述心轴，从而使所述第一多个间隔件及所述第二多个间隔件留在适当位置中以形成基于间隔件的蚀刻掩模；以及
使用所述基于间隔件的蚀刻掩模蚀刻用于所述线性结构的所述材料层以形成包含所述第一多个所述线性结构及所述第二多个所述线性结构的所述线性结构，其中所述第一多个线性结构的宽度小于所述第二多个线性结构的宽度。
2.根据权利要求1所述的方法，其中：
用于所述线性结构的所述材料层包含多晶硅；且
所述线性结构为平面金属氧化物半导体MOS晶体管的栅极。
3.根据权利要求1所述的方法，其中：
用于所述线性结构的所述材料层包含所述集成电路的衬底的晶体硅；且
所述线性结构为鳍片场效晶体管finFET的鳍片。
4.根据权利要求1所述的方法，其中：
用于所述线性结构的所述材料层包含多晶硅；且
所述线性结构为finFET的栅极。
5.根据权利要求1所述的方法，其中所述心轴包含二氧化硅。
6.根据权利要求1所述的方法，其中所述间隔件材料层包含氮化硅。
7.根据权利要求1所述的方法，其中所述缩短用于所述第一多个所述线性结构的所述区域中的所述第一组所述心轴的步骤经执行以使得所述第一多个线性结构的所述区域中的所述第一组所述心轴比所述第二多个线性结构的所述区域中的所述第二组所述心轴短为所述第二多个线性结构的所要宽度的一倍到三倍的垂直距离。
8.根据权利要求1所述的方法，其中所述形成所述间隔件材料层的步骤经执行以使得所述心轴的横向表面上的所述间隔件材料层的水平厚度大约为所述第二多个线性结构的所要宽度。
9.一种形成集成电路的方法，其包括以下步骤：
提供包括半导体材料的衬底；
在所述衬底上方形成包括多晶硅的栅极材料层；
在用于晶体管的栅极的所述栅极材料层上方形成多个心轴，所述栅极包含第一多个所述栅极及第二多个所述栅极，所述心轴具有为所述栅极的所要间距的两倍长的间距；
在所述心轴上方形成掩模材料层；
移除用于所述第一多个所述栅极的区域中的所述掩模材料层，且留下用于所述第二多个所述栅极的区域中的所述掩模材料层；
缩短用于所述第一多个所述栅极的所述区域中的第一组所述心轴，使得用于所述第二多个所述栅极的所述区域中的第二组所述心轴实质上不被缩短；
在所述心轴及用于所述栅极的所述材料层上方保形地形成间隔件材料层；
各向异性地凹蚀所述间隔件材料层以形成用于所述第一多个所述栅极的所述区域中的所述第一组所述心轴上的第一多个间隔件，且形成用于所述第二多个所述栅极的所述区域中的所述第二组所述心轴上的第二多个间隔件，使得所述第一多个所述间隔件的水平厚度小于所述第二多个所述间隔件的水平厚度；
移除所述心轴，从而使所述第一多个间隔件及所述第二多个间隔件留在适当位置中以形成基于间隔件的蚀刻掩模；
使用所述基于间隔件的蚀刻掩模蚀刻用于所述栅极的所述材料层以形成包含所述第一多个所述栅极及所述第二多个所述栅极的所述栅极，其中所述第一多个所述栅极的宽度小于所述第二多个所述栅极的宽度；以及
移除所述基于间隔件的蚀刻掩模。
10.根据权利要求9所述的方法，其中所述晶体管为平面MOS晶体管。
11.根据权利要求9所述的方法，其中所述晶体管为finFET。
12.根据权利要求9所述的方法，其中所述心轴包含二氧化硅。
13.根据权利要求9所述的方法，其中所述间隔件材料层包含氮化硅。
14.根据权利要求9所述的方法，其中所述缩短用于所述第一多个所述栅极的所述区域中的所述第一组所述心轴的步骤经执行以使得所述第一多个所述栅极的所述区域中的所述第一组所述心轴比所述第二多个所述栅极的所述区域中的所述第二组所述心轴短为所述第二多个所述栅极的所要宽度的一倍到三倍的垂直距离。
15.根据权利要求9所述的方法，其中所述形成所述间隔件材料层的步骤经执行以使得所述心轴的横向表面上的所述间隔件材料层的水平厚度大约为所述第二多个所述栅极的所要宽度。
16.一种形成集成电路的方法，其包括以下步骤：
提供包括半导体材料的衬底；
在所述衬底上方形成用于finFET的鳍片的多个心轴，所述鳍片包含第一多个所述鳍片及第二多个所述鳍片，所述心轴具有为所述鳍片的所要间距的两倍长的间距；
在所述心轴上方形成暴露用于所述第一多个所述鳍片的区域且在用于所述第二多个所述鳍片的区域中覆盖所述衬底的蚀刻掩模；
缩短用于所述第一多个所述鳍片的所述区域中的第一组所述心轴，使得用于所述第二多个所述鳍片的所述区域中的第二组所述心轴实质上不被缩短；
移除所述蚀刻掩模；
在所述心轴及所述衬底上方保形地形成间隔件材料层；
各向异性地凹蚀所述间隔件材料层以形成用于所述第一多个所述鳍片的所述区域中的所述第一组所述心轴上的第一多个间隔件，且形成用于所述第二多个所述鳍片的所述区域中的所述第二组所述心轴上的第二多个间隔件，使得所述第一多个所述间隔件的水平厚度小于所述第二多个所述间隔件的水平厚度；
移除所述心轴，从而使所述第一多个间隔件及所述第二多个间隔件留在适当位置中以形成基于间隔件的蚀刻掩模；
使用所述基于间隔件的蚀刻掩模蚀刻所述衬底以形成包含所述第一多个所述鳍片及所述第二多个所述鳍片的所述鳍片，其中所述第一多个所述鳍片的宽度小于所述第二多个所述鳍片的宽度；以及
移除所述基于间隔件的蚀刻掩模。
17.根据权利要求16所述的方法，其中所述心轴包含二氧化硅。
18.根据权利要求16所述的方法，其中所述间隔件材料层包含氮化硅。
19.根据权利要求16所述的方法，其中所述缩短用于所述第一多个所述鳍片的所述区域中的所述第一组所述心轴的步骤经执行以使得所述第一多个所述鳍片的所述区域中的所述第一组所述心轴比所述第二多个所述鳍片的所述区域中的所述第二组所述心轴短为所述第二多个所述鳍片的所要宽度的一倍到三倍的垂直距离。
20.根据权利要求16所述的方法，其中所述形成所述间隔件材料层的步骤经执行以使得所述心轴的横向表面上的所述间隔件材料层的水平厚度大约为所述第二多个所述鳍片的所要宽度。
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