CN104749511A - Description method of well resistor - Google Patents

Abstract

The invention discloses a description method of a well resistor. On the basis of a conventional well resistor evaluation, a buried layer potential of the well resistor is increased to change the resistance of the well resistor. The resistance of the well resistor can be described more precisely by introducing influence factors of the buried layer to the well resistor into the evaluation process of the well resistor.

Description

The describing method of trap resistance

Technical field

The present invention relates to SIC (semiconductor integrated circuit) design field, refer to a kind of describing method of trap resistance especially.

Background technology

Analog Circuit Design not only requires that resistance precision is high, more needs accurate resistance parameter and correctly describes resistive performance.The evaluation of current trap resistance all adopts the evaluation method of conventional resistive, i.e. two ends electric-resistivity method, and the impact for buried regions is ignored to some extent, and its resistance parameter extracts sign formula and is:

R(V)＝R0*(1+VC1*(n1n2)+VC2*(n1n2) ²)

But in side circuit application, often need to add noble potential at buried regions, and the different potentials that buried regions loads, very large on the impact of trap resistance.Buried regions current potential is particularly important for the extraction of the voltage parameter of conventional trap resistance, and voltage interdependence coefficient provides a more accurate trap resistance for circuit application person accurately.Therefore in the evaluation of trap resistance, introducing buried regions voltage interdependence coefficient is key point.

Summary of the invention

Technical matters to be solved by this invention is to provide a kind of describing method of trap resistance, can accurately calculate trap resistance.

For solving the problem, trap resistance of the present invention adopts following formula to describe:

$R\left(V\right)=R0*F1\left(V(n1,n2)\right)*F2\left(V(n2,n3)\right)*\frac{L-2\mathrm{dl}*F3\left(V(n2,n3)\right)}{W-2\mathrm{dw}*F4\left(V(n2,n3)\right)}$

Wherein,

F1(V(n1，n2))＝1+VC1*V(n1，n2)+VC2*V(n1，n2) ²；

F2(V(n2，n3))＝1+VC3*V(n2，n3)+VC4*V(n2，n3) ²；

F3(V(n2，n3))＝1+VC5*V(n2，n3)+VC6*V(n2，n3) ²；

F4(V(n2，n3))＝1+VC7*V(n2，n3)+VC8*V(n2，n3) ²；

V (n1 in formula, n2) n1 is represented, voltage between n2 two node, V (n2, n3) n2 is represented, voltage between n3 two node, , L is resistance length, W is resistor width, dl refers to the deviation of the resistance length brought due to fabrication error, dw refers to the deviation of the resistor width brought due to fabrication error, R0 refers to trap resistance square resistance, VC1, VC2 is conventional trap resistance single order, second order voltage coefficient, VC3, VC4 is the single order that buried regions voltage influence trap resistance extracts, second order voltage coefficient, VC5, VC6 raises single order to trap resistance effect length by buried regions voltage, second order voltage coefficient, VC7, VC8 raises by buried regions voltage the single order affected trap resistor width, second order voltage coefficient, described VC1 ~ VC8 is trap resistance coefficient.

Trap resistance coefficient abstracting method is as follows:

A) when buried regions current potential is 0 current potential under trap, R(V is passed through) computing formula extraction trap resistance coefficient dl, dw, VC1, VC2, R0;

B) when under trap, buried regions current potential is raised, select trap resistance test value during 3 ~ 5 kinds of different buried regions voltage, resistance length and width is selected all to be greater than the trap resistance of 10 μm, pass through R(V) computing formula, because resistor width and length are very large, now by R(V) impact of 2dw and 2dl in computing formula removes, and extracts trap resistance coefficient VC3, VC4;

C) select trap resistance test value during 3 ~ 5 kinds of different buried regions voltage, pass through R(V) computing formula, select one group of length identical and be greater than 10 μm, and the trap resistance that width is different, extract trap resistance coefficient VC7, VC8;

D) select trap resistance test value during 3 ~ 5 kinds of different buried regions voltage, pass through R(V) computing formula, select one group of width identical and be greater than 10 μm, and the trap resistance that length is different, extract trap resistance coefficient VC5, VC6.

The present invention evaluates on basis at conventional trap resistance, the influence factor of buried regions current potential to trap resistance under trap is listed in the appraisement system of trap resistance, makes buried regions current potential also can obtain accurate Calculation to the impact of trap resistance, for circuit application provides more accurate trap resistance.

Accompanying drawing explanation

Fig. 1 is P type well structure schematic diagram.

Embodiment

Described trap resistance of the present invention adopts following formula to describe:

$R\left(V\right)=R0*F1\left(V(n1,n2)\right)*F2\left(V(n2,n3)\right)*\frac{L-2\mathrm{dl}*F3\left(V(n2,n3)\right)}{W-2\mathrm{dw}*F4\left(V(n2,n3)\right)}---\left(1\right)$

Wherein,

F1(V(n1，n2))＝1+VC1*V(n1，n2)+VC2*V(n1，n2) ²；

F2(V(n2，n3))＝1+VC3*V(n2，n3)+VC4*V(n2，n3) ²；

F3(V(n2，n3))＝1+VC5*V(n2，n3)+VC6*V(n2，n3) ²；

F4(V(n2，n3))＝1+VC7*V(n2，n3)+VC8*V(n2，n3) ²；

V (n1 in formula, n2) n1 is represented, voltage between n2 two node, V (n2, n3) n2 is represented, voltage between n3 two node, L is resistance length, W is resistor width, dl refers to the deviation of the resistance length brought due to fabrication error, dw refers to the deviation of the resistor width brought due to fabrication error, R0 refers to trap resistance square resistance, VC1, VC2 is conventional trap resistance single order, second order voltage coefficient, VC3, VC4 is the single order that buried regions voltage influence trap resistance extracts, second order voltage coefficient, VC5, VC6 raises single order to trap resistance effect length by buried regions voltage, second order voltage coefficient, VC7, VC8 raises by buried regions voltage the single order affected trap resistor width, second order voltage coefficient, VC1 ~ VC8 is trap resistance coefficient.Trap resistance coefficient abstracting method is as follows:

A) when buried regions current potential is 0 current potential under trap, R(V is passed through) computing formula extraction trap resistance coefficient dl, dw, VC1, VC2, R0;

B) when under trap, buried regions current potential is raised, select trap resistance test value during 3 ~ 5 kinds of different buried regions voltage, resistance length and width is selected all to be greater than the trap resistance of 10 μm, as the trap resistance of W/L=20/20, pass through R(V) computing formula, because resistor width and length are very large, now by R(V) impact of 2dw and 2dl in computing formula removes, and extracts trap resistance coefficient VC3, VC4;

C) trap resistance test value during 3 ~ 5 kinds of different buried regions voltage is selected, pass through R(V) computing formula, select one group of length identical and be greater than 10 μm, and the trap resistance that width is different, as W/L=0.2/20, W/L=1/20, W/L=2/20, W/L=5/20, W/L=10/20, W/L=20/20 mono-trap resistance of packet size, extract trap resistance coefficient VC7, VC8;

D) trap resistance test value during 3 ~ 5 kinds of different buried regions voltage is selected, pass through R(V) computing formula, select one group of width identical and be greater than 10 μm, and the trap resistance that length is different, as W/L=20/5, W/L=20/10, W/L=20/20 mono-trap resistance of packet size, extract trap resistance coefficient VC5, VC6.

The above is trap resistance describing method of the present invention, is now described as follows in conjunction with an embodiment:

For P type trap resistance, its structure as shown in Figure 1, is isolated by N-type epitaxy layer (N-EPI) and n type buried layer (NBL) between P trap and P type substrate, and two contact PAD(n1 are received at trap resistance two ends respectively, n2), n type buried layer is drawn 1 end simultaneously and be connected to 1 contact PAD(n3).

In analogue circuit applications, according to different application demands, buried regions end needs to add different current potentials.Along with raising of buried regions current potential, the PN junction that P trap and N-type extension are formed enters reverse-biased, and PN junction place can form depletion region, and P trap side, due to the broadening of depletion region, makes P trap resistance current path narrow, thus makes P trap resistance become large.The present invention takes into account by the influence factor of buried regions current potential to trap resistance, extracts resistance parameter R0, VC1 ~ VC8, dL, dW by above-mentioned formula 1.Contemplated by the invention the impact of buried regions current potential on trap resistive voltage coefficient and trap resistance length and width size.

Above in formula 1:

F1 (V (n1, n2)) describes the voltage coefficient of trap resistance own:

F1(V(n1,n2))=1+VC1*V(n1,n2)+VC2*V(n1,n2) ²

F2 (V (n2, n3)) describes the trap resistive voltage coefficient that buried regions current potential is introduced:

F2(V(n2,n3))=1+VC3*V(n2,n3)+VC4*V(n2,n3) ²

F3 (V (n2, n3)) describes because the potential difference (PD) between buried regions and P trap causes the PN junction of P trap/N-type extension to exhaust, thus causes the change of trap resistance length:

F3(V(n2,n3))=1+VC5*V(n2,n3)+VC6*V(n2,n3) ²

F4 (V (n2, n3)) describes because the potential difference (PD) between buried regions and P trap causes the PN junction of P trap/N-type extension to exhaust, thus causes the change of trap resistor width:

F4(V(n2,n3))=1+VC7*V(n2,n3)+VC8*V(n2,n3) ²

The main extraction step of each parameter of trap resistance is as described below:

Design the trap electric resistance structure array of one group of different in width and length, as shown in the following chart: (unit: μm)

W	20	10	5	2	1	0.5	20	20
									L	20	20	20	20	20	20	10	5

When n type buried layer is 0 current potential, trap resistance coefficient can be extracted by formula 1: dL, dW, VC1, VC2, R0.

When n type buried layer current potential is raised, select trap resistance test value during 3 ~ 5 kinds of different N type buried regions voltage, select the trap resistance of large scale (W/L=20/20), substitute into formula 1, because resistor width and length are very large, now 2dW and 2dL impact can be removed, we can extract trap resistance coefficient thus: VC3, VC4.

Select trap resistance test value during 3 ~ 5 kinds of different N type buried regions voltage, by formula 1, use W/L=0.5/20, W/L=1/20, W/L=2/20, W/L=5/20, W/L=10/20, W/L=20/20 mono-the trap resistance of packet size can extract trap resistance coefficient: VC7, VC8.

Select trap resistance test value during 3 ~ 5 kinds of different N BL voltage, by formula 1, use W/L=20/5, W/L=20/10, W/L=20/20 etc. one the trap resistance of packet size can extract trap resistance coefficient: VC5, VC6.

In above formula 1, composition graphs 1:

N1: refer to trap resistance hot end;

N2: refer to trap resistance cold end;

N3: refer to buried regions potential end;

L refers to resistance length, and W refers to resistor width, and unit is μm;

Dl refers to the deviation of the resistance length brought due to fabrication error, and dw refers to the deviation of the resistor width brought due to fabrication error, and unit is μm;

R0: refer to trap resistance square resistance, unit is Ω/;

VC1, VC2: conventional trap resistance single order, second order voltage coefficient;

VC3, VC4: single order, second order voltage coefficient that buried regions voltage influence trap resistance extracts;

VC5, VC6: raise single order, the second order voltage coefficient to trap resistance effect length by buried regions voltage;

VC7, VC8: raised single order, second order voltage coefficient that trap resistor width is affected by buried regions voltage.

These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (2)

1. a describing method for trap resistance, is characterized in that: adopt following formula to describe:

$R\left(V\right)=R0*R1\left(V(n1,n2)\right)*F2\left(V(n2,n3)\right)*\frac{L-2\mathrm{dl}*F3\left(V(n2,n3)\right)}{W-2\mathrm{dl}*F4\left(V(n2,n3)\right)}$

Wherein,

F1(V(n1，n2))＝1+VC1*V(n1，n2)+VC2*V(n1，n2) ²；

F2(V(n2，n3))＝1+VC3*V(n2，n3)+VC4*V(n2，n3) ²；

F3(V(n2，n3))＝1+VC5*V(n2，n3)+VC6*V(n2，n3) ²；

F4(V(n2，n3))＝1+VC7*V(n2，n3)+VC8*V(n2，n3) ²；

V (n1 in formula, n2) n1 is represented, voltage between n2 two node, V (n2, n3) n2 is represented, voltage between n3 two node, L is resistance length, W is resistor width, dl refers to the deviation of the resistance length brought due to fabrication error, dw refers to the deviation of the resistor width brought due to fabrication error, R0 refers to trap resistance square resistance, VC1, VC2 is conventional trap resistance single order, second order voltage coefficient, VC3, VC4 is the single order that buried regions voltage influence trap resistance extracts, second order voltage coefficient, VC5, VC6 raises single order to trap resistance effect length by buried regions voltage, second order voltage coefficient, VC7, VC8 raises by buried regions voltage the single order affected trap resistor width, second order voltage coefficient, described VC1 ~ VC8 is trap resistance coefficient.

2. the describing method of trap resistance as claimed in claim 1, is characterized in that: described trap resistance coefficient abstracting method is as follows:

A) when buried regions current potential is 0 current potential under trap, R(V is passed through) computing formula extraction trap resistance coefficient dl, dw, VC1, VC2, R0;

B) when under trap, buried regions current potential is raised, select trap resistance test value during 3 ~ 5 kinds of different buried regions voltage, resistance length and width is selected all to be greater than the trap resistance of 10 μm, pass through R(V) computing formula, because resistor width and length are very large, now by R(V) impact of 2dw and 2dl in computing formula removes, and extracts trap resistance coefficient VC3, VC4;

C) select trap resistance test value during 3 ~ 5 kinds of different buried regions voltage, pass through R(V) computing formula, select one group of length identical and be greater than 10 μm, and the trap resistance that width is different, extract trap resistance coefficient VC7, VC8;

D) select trap resistance test value during 3 ~ 5 kinds of different buried regions voltage, pass through R(V) computing formula, select one group of width identical and be greater than 10 μm, and the trap resistance that length is different, extract trap resistance coefficient VC5, VC6.