CN104777456A - Configurable radar digital signal processor and processing method adopting same - Google Patents
Configurable radar digital signal processor and processing method adopting same Download PDFInfo
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- CN104777456A CN104777456A CN201510172252.7A CN201510172252A CN104777456A CN 104777456 A CN104777456 A CN 104777456A CN 201510172252 A CN201510172252 A CN 201510172252A CN 104777456 A CN104777456 A CN 104777456A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
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Abstract
The invention discloses a configurable radar digital signal processor and a processing method adopting the same. The configurable radar digital signal processor comprises eight modules, wherein a control logic module is used for receiving external configuration information and generating four ways of control signals, wherein a first way of control signal controls an address generation module to generate address read/write address signals of a butterfly coefficient module and an external storage module; a second way of control signal controls a data adjusting module to adjust data and transmit the data to a data distribution module; a third way of control signal controls the data distribution module to distribute the data to a multiplication tree module and a data post-processing module; a fourth way of control signal controls the data post-processing module to process the data and transmit the data to the data adjusting module and the external storage module; the butterfly coefficient module reads the data and transmits the data to the data distribution module, the external storage module reads the data and transmits the data to the data adjusting module, and the multiplication tree module completes multiplication operation and outputs a result to the data post-processing module. The configurable radar digital signal processor and the processing method adopting the configurable radar digital signal processor have the advantages of small caching and storing areas, multiple functions, low power consumption and short design period, and can be used for communication and real-time processing of radar digital signals.
Description
Technical field
The present invention relates to digital signal processing technique field, particularly the configurable Radar Digital Signal Processing of one, can be used for the real-time process of communication and radar signal.
Background technology
Along with Radar Signal Processing is theoretical and the development of digital technology, radar signal now adopts numerical approach process mostly.Digital Down Convert DDC, after digital to analog converter, for intermediate-freuqncy signal is moved zero-frequency, and extracts useful information, filters interfere information, extract data, reduces data rate; Pulse compression PC solves the contradiction between radar horizon and resolving power, and the method realizing pulse compression due to frequency domain greatly reduces than the operand of convolution, adopts the mode of frequency domain to realize pulse compression so general; Moving target detect MTD utilize Doppler effect to improve ability that radar detects moving-target under clutter background, improves the antijamming capability of radar.General radar signal processor adopts the mode of streamline to realize, its advantage continuously can process data, but this implementation hardware configuration is complicated, buffer memory and storage resources large, cost is high, power consumption is large, and does not meet the characteristic of pulse Doppler radar intermittent transmission and return pulse signal.
The patented technology " a kind of intermediate frequency LFM-PD radar signal real time processing system based on FPGA and DSP and disposal route " (application number CN201110131410, Authorization Notice No. CN102288941B) that BJ University of Aeronautics & Astronautics has discloses a kind of pulsed radar signal real-time processing method.The method adopts FPGA to complete if sampling, Digital Down Convert, pulse compression, completes moving target detect, correlative accumulation, moving target compensation and CFAR process with DSP.The deficiency that this patented technology exists is, whole system adopts the mode of streamline, needs a large amount of cache resources between flowing water at different levels, and area is large, and along with the increase of correlative accumulation number, the processing speed of DSP does not reach the requirement of process in real time.
Summary of the invention
The object of the invention is to, for above-mentioned existing the deficiencies in the prior art, propose a kind of configurable radar digital signal processor and disposal route thereof, to reduce processor cache and to store area, reduce costs, realize the real-time process of radar signal.
Technical thought of the present invention is: by time-multiplexed mode, realizes the real-time process of radar signal, and by the mode of plug-in storage, practical function module is separated with memory module, saves buffer memory and stores area, reducing costs.Its implementation is as follows:
One, a configurable radar digital signal processing device, is characterized in that comprising:
Steering logic module, for configuring the mode of operation of radar signal processor, produce the control signal corresponding with mode of operation, this control signal is transported to address generating module, data point reuse module, data allocation module, Data Post module;
Address generating module, for producing read/write address signal according to control signal, and outputs to butterfly coefficient module and plug-in memory module by address signal;
Butterfly coefficient module, for storing the butterfly coefficient needed for FFT/IFFT computing, and outputs to data allocation module according to the data that address control signal reading stores;
Plug-in memory module, for storing the operation result of the coefficient of low-pass filtering, the coefficient of matched filtering and Data Post module, and outputs to data point reuse module according to the data that address control signal reading stores;
Data point reuse module, for finding out the maximum value in Data Post module output data, and is shifted according to the output data of control signal to plug-in memory module or synchronously, the data after process is outputted to data allocation module;
Data allocation module, for exporting data, outer input data and constant 0 according to control signal select the output data of butterfly coefficient module, plug-in memory module, outputs to multiplication tree module and Data Post module by selection result;
Multiplication tree module, for carrying out multiplying to the data of data allocation module, outputs to Data Post module by after operation result cut position;
Data Post module, for carrying out plus/minus computing according to control signal to the output data of data allocation module, the output data of multiplication tree module, outputs to data point reuse module and plug-in memory module by operation result.
Two, carry out the method for radar digital signal processing with above-mentioned processor, comprise the steps:
(1) initial parameter configuration:
User by processor mode configuration information stored in the first configuration register, by length configuration information stored in the second configuration register, by the butterfly coefficient needed for FFT/IFFT computing stored in butterfly coefficient module, by the coefficient of low-pass filtering, the coefficient of matched filtering stored in plug-in memory module;
(2) control signal is produced:
When data enable signal is high level, processor enters duty, the value of working mark signal is high level, unison counter starts counting, according to the first configuration register and the second configuration register state value, counter judges whether counting terminates, and if so, then the value saltus step of working mark signal is low level, if not, then the value of working mark signal keeps high level;
When working mark signal is high level, the control module of Logic control module produces four control signals, first control signal is for controlling address generating module calculated address signal, second control signal be used for control data adjusting module to data be shifted/synchronous, 3rd control signal is used for control data distribution module and selects data, and the 4th control signal is used for control data post-processing module and carries out plus/minus computing to after data selection;
(3) computing has been judged whether:
Judge whether working mark signal is low level, and if so, then computing completes, if not, then computing does not complete, and performs step (4);
(4) address signal is produced:
Address produces signaling module under the control of the first control signal, and what produce butterfly coefficient module reads address signal, and what produce plug-in memory module reads address signal and writing address signal thereof simultaneously;
(5) data encasement:
Address signal of reading according to plug-in memory module reads data and outputs to data point reuse module, and according to the second control signal to data be shifted/synchronous after this result is delivered to data allocation module; Address signal of reading according to butterfly coefficient module reads butterfly coefficient, and these data are outputted to data allocation module; Receive outside input data, these data are outputted to data allocation module;
(6) data are distributed:
Data allocation module, under the control of the 3rd control signal, selects data from the output data of step (5), outputs to multiplication tree module, Data Post module;
(7) multiplying:
Multiplication tree module exports data to step (6) and carries out multiplying, outputs to Data Post module after the result of acquisition carries out cut position;
(8) Data Post:
Data Post module, under the control of the 4th control signal, is carried out plus/minus computing after selecting, will flow to plug-in memory module, data point reuse module after result of calculation cut position to the output data of step (6), step (7);
(9) data store:
The result of calculation of Data Post module is outputted to data point reuse module, finds out and export the maximum value of data and the highest significant position of this maximum value; The result of calculation of Data Post module is write in plug-in memory module, returns step (3).
The present invention compared with prior art has following characteristics:
The first, be separated with memory module owing to present invention employs functional module, can save a large amount of buffer memorys and store area, reduce cost, storage resources can be plug-in according to user's request, and reach utilization ratio of storage resources and maximize, dirigibility is high.
Second, because the present invention is extracted Digital Down Convert in radar digital signal processing, pulse compression, the common ground of moving target detect algorithm, design a multi-functional circuit structure, make the present invention can realize Digital Down Convert respectively, the moving target detect of the pulse compression that difference is counted and different number, also time-multiplexed mode order can be adopted to complete Digital Down Convert, the moving target detect of the pulse compression that difference is counted and different number, the mode of flowing water can also be adopted to carry out Digital Down Convert, the moving target detect of the pulse compression that difference is counted and different number, the design cycle shortening processor is short, improve efficiency.
Accompanying drawing explanation
Fig. 1 is the block scheme of processor of the present invention;
Fig. 2 is the block scheme of Logic control module in processor of the present invention;
Fig. 3 is the block scheme of data point reuse module in processor of the present invention;
Fig. 4 is the block scheme of Data Post module in processor of the present invention;
Fig. 5 is process flow figure of the present invention.
Embodiment
Below in conjunction with accompanying drawing, radar signal processor of the present invention is further described.
With reference to accompanying drawing 1, configurable radar digital signal processing device of the present invention comprises; Steering logic module 1, address generating module 2, butterfly coefficient module 3, plug-in memory module 4, data point reuse module 5, data allocation module 6, multiplication tree module 7 and Data Post module 8.Wherein:
Described steering logic module 1, it is connected with address generating module 2, data point reuse module 5, data allocation module 6 and Data Post module 8, for receiving outside the pattern configurations information, length configuration information, configuration enable signal and the data enable signal that input; When data enable signal is high level, produce four control signals according to pattern configurations information and length configuration information, these four control signals control different modules respectively and complete different functions.Wherein the first control signal is transferred to address generating module 2 by control bus, controls this address generating module 2 calculated address signal; Second control signal is transferred to data point reuse module 5 by control bus, control this data point reuse module 5 pairs of data to be shifted/synchronous; 3rd control signal is transferred to data allocation module 6 by control bus, controls this data allocation module 6 pairs of data and selects; 4th control signal is transferred to Data Post module 8 by control bus, controls this Data Post module 8 pairs of data selections and carries out plus/minus computing.
Described address generating module 2, it is connected with butterfly coefficient module 3 and plug-in memory module 4, for the control signal of receive logic control module 1, produce under control of the control signal butterfly coefficient module 3 read address signal and plug-in memory module 4 read address signal and writing address signal; The address signal of reading of butterfly coefficient module 3 is transferred to butterfly coefficient module 3 by reading address bus, the address signal of reading of plug-in memory module 4 is transferred to plug-in memory module 4 by reading address bus, and the writing address signal of plug-in memory module 4 gives plug-in memory module 4 by write address bus transfer.
Described butterfly coefficient module 3, it is connected with data allocation module 6, reading address signal for receiver address generation module 2, reading butterfly coefficient in butterfly coefficient module 3 according to reading address signal, the real part of this butterfly coefficient and imaginary part respectively by data bus transmission to data allocation module 6.
Described plug-in memory module 4, it is connected with data point reuse module 5, address signal and writing address signal is read for what receive real part that Data Post module 8 exports and imaginary data and address generating module 2, real part Data Post module 8 exported according to writing address signal and imaginary data write plug-in memory module 4, according to the data reading address signal and read plug-in memory module 4, the real part of these data and imaginary part respectively by data bus transmission to data point reuse module 5.
Described data point reuse module 5, it is connected with data allocation module 6, for receiving the control signal of steering logic module 1, the real part of the real part that plug-in memory module 4 exports and imaginary data and Data Post module 8 output and imaginary data, find out Data Post module 8 export real part and imaginary data in maximum value and judge its most significant digit, and judge it is real part that plug-in memory module 4 is exported and imaginary data is shifted or synchronously according to control signal: if control signal is high level, the real part then plug-in memory module 4 exported and imaginary data carry out shifting function, the figure place of displacement equals the difference that data bit width deducts most significant digit, if control signal is low level, then the real part plug-in memory module 4 exported and imaginary data are carried out synchronously, again by the real part after displacement/synchronous and imaginary data respectively by data bus transmission to data allocation module 6,
Described data allocation module 6, it is connected with multiplication tree module 7 and Data Post module 8, for receiving outer input data, the real part that exports of real part that butterfly coefficient 3 exports and imaginary data, data point reuse module 5 and the control signal of imaginary data, constant 0 and Logic control module 1, under control of the control signal received data are selected, and by data selecting by data bus transmission to Data Post module 8, by four data selecting respectively by data bus transmission to multiplication tree module 7.
Described multiplication tree module 7, it is connected with Data Post module 8, four for receiving data allocation module 6 export data, and the first data and the second data are carried out multiplying, 3rd data and the 4th data are carried out multiplying, then by after these two result of calculation cut positions respectively by data bus transmission to Data Post module 8.
Described Data Post module 8, it is connected with plug-in memory module 4 and data point reuse module 5, two for the output data of the control signal of receive logic control module 1, data allocation module 6, constant 0 and multiplication tree module 7 export data, received data are delivered to respectively real part passage and imaginary part passage, under control of the control signal, carry out plus/minus computing to after the data selection of real part passage and imaginary part passage, and give plug-in memory module 4 and data point reuse module 5 respectively by data bus transmission after real part and imaginary part two-way result being carried out cut position.
With reference to accompanying drawing 2, in processor of the present invention, Logic control module 1 comprises; First configuration register 11, second configuration register 12 and control module 13.Wherein:
First configuration register 11, it is connected with control module 13, for receiving configuration enable signal and the mode configuration signals of outside input, when configuration enable signal is high level, by configuration mode signal stored in the first configuration register 11, the data in the first configuration register 11 are outputted to control module 13 by data bus.
Second configuration register 12, it is connected with control module 13, for receiving configuration enable signal and the length configuration signal of outside input, when configuration enable signal is high level, by length configuration signal stored in the second configuration register 12, the data in the second configuration register 12 are outputted to control module 13 by data bus.
Control module 13, it is connected with address generating module 2, data point reuse module 5, data allocation module 6 and Data Post module 8, for receiving the outside data enable signal, the output data of the first configuration register 11 and the output data of the second configuration register that input, when data enable signal is high level, produce four control signals according to the output data of the first configuration register 11 and the output data of the second configuration register, these four control signals control different modules respectively and complete different functions.Wherein the first control signal is transferred to address generating module 2 by control bus, controls this address generating module 2 calculated address signal; Second control signal is transferred to data point reuse module 5 by control bus, control this data point reuse module 5 pairs of data to be shifted/synchronous; 3rd control signal is transferred to data allocation module 6 by control bus, controls this data allocation module 6 pairs of data and selects; 4th control signal is transferred to Data Post module 8 by control bus, controls this Data Post module 8 pairs of data selections and carries out plus/minus computing.
With reference to accompanying drawing 3, in processor of the present invention, data point reuse module 5 comprises; A maximum value unit 51, highest significant position unit 52 and a data shifts/lock unit 53.Wherein:
Maximum value unit 51, it is connected with highest significant position unit 52, for receiving the output data of Data Post module 8, finding out the maximum value that Data Post module 8 exports data, this maximum value is outputted to highest significant position unit 52 by data bus.
Highest significant position unit 52, it is connected with data shifts/lock unit 53, for receiving the output data of maximum value unit 51, finds out the highest significant position of these data, highest significant position is outputted to data shifts/lock unit 53 by data bus.
Data move/lock unit 53, it is connected with data allocation module 6, for receiving the output data of the output data of highest significant position unit 52, the control signal of steering logic module 1 and plug-in memory module 4, and judge it is real part that plug-in memory module 4 is exported and imaginary data is shifted or synchronously according to control signal: if control signal is high level, be shifted, the real part then plug-in memory module 4 exported and imaginary data carry out shifting function, and the figure place of displacement equals the difference that data bit width deducts most significant digit; If control signal is low level, carry out synchronous, then the real part plug-in memory module 4 exported and imaginary data are carried out synchronously; Again by the real part after displacement/synchronous and imaginary data respectively by data bus transmission to data allocation module 6.
With reference to accompanying drawing 4, in processor of the present invention, Data Post module 8 comprises; First data selection unit 81, second data selection unit, 82, cut position unit 83 and four plus/minus method unit.Wherein:
First data selection unit 81, it is connected with the first plus/minus method unit 84 and the 3rd plus/minus method unit 86, data, constant 0, the output data of data allocation module 6, the output data of the first plus/minus method unit 84 and the control signal of Logic control module 1 is exported for receiving two of multiplication tree module 7, under the control of this control signal, select two data respectively by data bus transmission give the first plus/minus method unit 84, select one of them data by data bus transmission give the 3rd plus/minus method unit 86.
First plus/minus method unit 84, it is connected with the first data selection unit 81 and the 3rd plus/minus method unit 86, for receiving the control signal that two of the first data selection unit 81 export data and Logic control module 1, under the control of this control signal, two data are carried out addition or subtraction, and operation result gives the first data selection unit 81 and the 3rd plus/minus method unit 86 by data bus transmission.
3rd plus/minus method unit 86, it is connected with cut position unit 83, for receiving by the output data of the first data selection unit 81, the output data of the first plus/minus method unit 84 and the control signal of Logic control module 1, under control of the control signal, two data are carried out addition or subtraction, operation result by data bus transmission to cut position unit 83.
Second data selection unit 82, it is connected with the second plus/minus method unit 85 and the 4th plus/minus method unit 87, data, constant 0, the output data of data allocation module 6, the output data of the second plus/minus method unit 85 and the control signal of Logic control module 1 is exported for receiving two of multiplication tree module 7, under the control of this control signal, select two data respectively by data bus transmission give the second plus/minus method unit 85, select one of them data by data bus transmission give the 4th plus/minus method unit 87.
Second plus/minus method unit 85, it is connected with the second data selection unit 82 and the 4th plus/minus method unit 87, for receiving the control signal that two of the second data selection unit 82 export data and Logic control module 1, under the control of this control signal, two data are carried out addition or subtraction, and operation result gives the second data selection unit 82 and the 4th plus/minus method unit 87 by data bus transmission.
4th plus/minus method unit 87, it is connected with cut position unit 83, for receiving by the output data of the second data selection unit 82, the output data of the second plus/minus method unit 85 and the control signal of Logic control module 1, under the control of this control signal, two data are carried out addition or subtraction, operation result by data bus transmission to cut position unit 83.
Cut position unit 83, it is connected with plug-in memory module 4 and data point reuse module 5, for the output data of the output data and the 4th plus/minus method unit 87 that receive the 3rd plus/minus method unit 86, give plug-in memory module 4 and data point reuse module 5 by after two data cut positions respectively by data bus transmission.
With reference to Fig. 5, utilize above-mentioned processor to carry out the method for radar digital signal processing, its step is as follows:
Step 1, initial parameter configures
User by processor mode configuration information stored in the first configuration register, by length configuration information stored in the second configuration register, by the butterfly coefficient needed for FFT/IFFT computing stored in butterfly coefficient module, by the coefficient of low-pass filtering, the coefficient of matched filtering stored in plug-in memory module;
Wherein, pattern configurations information bit wide is 2, comprises four kinds of mode of operations, when pattern configurations information is 00, enters Digital Down Convert pattern; When pattern configurations information is 01, enter frequency-domain impulse compact model; When pattern configurations information is 10, enter moving target detect pattern; When pattern configurations information is 11, enter time division multiplexing, time-multiplexed carry out Digital Down Convert, frequency-domain impulse compression and moving target detect computing;
The information of length configuration information bit wide to be 20, Gao Shiwei be pulse compression sequence length, the information of length range to be 2 to 1024, low ten be correlative accumulation number, number range is 2 to 1024.
Step 2, produces control signal
2a) when data enable signal is high level, processor enters duty, the value of working mark signal is high level, unison counter starts counting, according to the first configuration register and the second configuration register state value, counter judges whether counting terminates, and if so, then the value saltus step of working mark signal is low level, if not, then the value of working mark signal keeps high level;
2b) when working mark signal is high level, steering logic control module produces control signal, and these four control signals control respectively as follows:
Described first control signal, for controlling address generating module calculated address signal, different mode of operations needs different address signals, and concrete manifestation is as follows;
When processor is in Digital Down Convert pattern, this control signal reads address signal and writing address signal for what control that address generating module generates data plug-in modules; When processor is in frequency-domain impulse compact model, this control signal for control address generating module generate butterfly coefficient module read address signal and plug-in module read address signal and writing address signal; When processor is in moving target detect pattern, this control signal for control address generating module generate butterfly coefficient module read address signal and plug-in module read address signal and writing address signal; When processor is in time division multiplexing, this control signal for control address generating module generate butterfly coefficient module read address signal and plug-in module read address signal and writing address signal;
Described second control signal, for control data adjusting module to data be shifted/synchronous, different mode of operations needs to carry out different operations to data, and concrete manifestation is as follows;
When processor is in Digital Down Convert pattern, do not use this signal; When processor is in frequency-domain impulse compact model, this control signal be used for plug-in memory module export matched filtering coefficient carry out synchronously, to plug-in memory module export pulse train be shifted; When processor is in moving target detect pattern, this control signal be used for plug-in memory module export pulse train be shifted; When processor is in time division multiplexing pattern, this control signal is used for carrying out synchronously, being shifted to the pulse train that plug-in memory module exports to the matched filtering coefficient that plug-in memory module exports;
Described 3rd control signal is used for control data distribution module and selects data, and different mode of operations needs to carry out different selections to data, and concrete manifestation is as follows;
When processor is in Digital Down Convert pattern, this control signal gives data allocation module for selecting the output data of outer input data and data point reuse module, when processor is in frequency-domain impulse compact model, processor needs to carry out fast time domain FFT successively, matching factor is multiplied and fast time domain IFFT computing, when carrying out fast time domain FFT/IFFT computing, this control signal gives data allocation module for the output data of the output data and butterfly coefficient module of selecting outer input data, data point reuse module, carry out matching factor when being multiplied, this control signal gives data allocation module for selecting the output data of data point reuse module, when processor is in moving target detect pattern, processor needs to carry out slow time domain FFT computing, and this control signal gives data allocation module for the output data of the output data and butterfly coefficient module of selecting outer input data, data point reuse module, when processor is in time division multiplexing, processor needs to carry out Digital Down Convert, fast time domain FFT, matching factor is multiplied, fast time domain IFFT and slow time domain FFT computing, when carrying out Digital Down Convert, this control signal gives data allocation module for selecting the output data of outer input data and data point reuse module, when carrying out fast time domain FFT/IFFT and slow time domain FFT, this control signal is for selecting outer input data, the output data of data point reuse module and the output data of butterfly coefficient module give data allocation module, carry out matching factor when being multiplied, this control signal gives data allocation module for selecting the output data of data point reuse module,
Described 4th control signal is used for control data post-processing module and carries out plus/minus computing to after data selection, and different mode of operations needs different computings, and concrete manifestation is as follows;
When processor is in Digital Down Convert pattern, this control signal completes the accumulating operation in Digital Down Convert for control data post-processing module, when processor is in frequency-domain impulse compression, processor needs to carry out fast time domain FFT, matching factor is multiplied and fast time domain IFFT computing, when carrying out fast time domain FFT/IFFT, this control signal is used for the additive operation that control data post-processing module completes butterfly computation, carry out matching factor when being multiplied, this control signal is used for control data post-processing module and completes the additive operation of mating and being multiplied, when processor is in moving target detect, processor needs to carry out slow time domain FFT computing, and this control signal is used for the additive operation that control data post-processing module completes butterfly computation, when processor is in time division multiplexing, processor needs to carry out Digital Down Convert, fast time domain FFT, matching factor is multiplied, fast time domain IFFT and slow time domain FFT computing, when carrying out Digital Down Convert, this control signal completes the tired plus/minus computing in Digital Down Convert for control data post-processing module, when carrying out fast time domain FFT/IFFT and slow time domain FFT, this control signal completes the plus/minus method computing in butterfly computation for control data post-processing module, carry out matching factor when being multiplied, this control signal completes for control data post-processing module mates the plus/minus method computing in being multiplied.
Step 3, judges whether the computing corresponding to the pattern of finishing the work:
Computing corresponding to mode of operation is divided into four kinds: the first is Digital Down Convert pattern, comprises low-pass filtering and extract operation; The second is frequency-domain impulse compact model, comprises fast time domain FFT, matching factor is multiplied and fast time domain IFFT computing; The third is moving target detect pattern, comprises slow time domain FFT computing; 4th kind is time division multiplexing, comprises Digital Down Convert, fast time domain FFT, matching factor are multiplied, fast time domain IFFT and slow time domain FFT computing;
Judge whether that the computing corresponding to the pattern of finishing the work is by judging whether working mark signal is that low level realizes, if working mark signal is low level, then complete the computing corresponding to mode of operation, if working mark signal is high level, computing then corresponding to unfinished work pattern, performs step 4.
Step 4, produces address signal
Address produces signaling module under the control of the first control signal, and what produce butterfly coefficient module reads address signal, and what produce plug-in memory module reads address signal and writing address signal thereof simultaneously.
Step 5, data encasement
5a) receive outside input data, these data are outputted to data allocation module;
5b) read data according to the address signal of reading of plug-in memory module, the real part of these data and imaginary part are outputted to data point reuse module, and according to the second control signal to real part and imaginary data be shifted/synchronous after real part and imaginary results are delivered to data allocation module;
5c) read butterfly coefficient according to the address signal of reading of butterfly coefficient module, the real part of this butterfly coefficient and imaginary part are outputted to data allocation module.
Step 6, data are distributed
Data allocation module, under the control of the 3rd control signal, carries out data selection, selects four data and output to multiplication tree module, select data and output to Data Post module from five output data and constant 0 of step 5.
Step 7, multiplying
Multiplication tree module carries out multiplying to four output data that step 6 exports, and namely first the first data and the second data is carried out multiplying; Again the 3rd data and the 4th data are carried out multiplying; Then by after these two result of calculation cut positions respectively by data bus transmission to Data Post module.
Step 8, Data Post
Output data of Data Post module receiving step 6, two output Data Data of step 7 and constant 0, and received data are delivered to real part passage and imaginary part passage respectively; Again under the control of the 4th control signal, respectively plus/minus computing is carried out to the data of real part passage and imaginary part passage, finally real part and imaginary part two-way result to be carried out after cut position respectively by data bus transmission to plug-in memory module and data point reuse module.
Step 9, data store
The real part of Data Post module and imaginary data are outputted to data point reuse module, finds out the maximum value and highest significant position thereof that export data; The real part of Data Post module and imaginary data are write in plug-in memory module, returns step 3.
More than describing is only example of the present invention; obviously for the professional person of this area; after having understood content of the present invention and principle; all likely when not deviating from the principle of the invention, structure; carry out the various correction in form and details and change, but these corrections based on inventive concept and change are still within claims of the present invention.
Claims (5)
1. a configurable radar digital signal processing device, is characterized in that comprising:
Steering logic module (1), for configuring the mode of operation of radar signal processor, produce the control signal corresponding with mode of operation, this control signal is transported to address generating module (2), data point reuse module (5), data allocation module (6), Data Post module (8);
Address generating module (2), for producing read/write address signal according to control signal, and outputs to butterfly coefficient module (3) and plug-in memory module (4) by address signal;
Butterfly coefficient module (3), for storing the butterfly coefficient needed for FFT/IFFT computing, and outputs to data allocation module (6) according to the data that address control signal reading stores;
Plug-in memory module (4), for storing the operation result of the coefficient of low-pass filtering, the coefficient of matched filtering and Data Post module (8), and output to data point reuse module (5) according to the data that address control signal reading stores;
Data point reuse module (5), for finding out the maximum value in Data Post module (8) output data, and be shifted according to the output data of control signal to plug-in memory module (4) or synchronously, the data after process outputted to data allocation module (6);
Data allocation module (6), for exporting data, outer input data and constant 0 according to control signal select the output data of butterfly coefficient module (3), plug-in memory module (4), selection result is outputted to multiplication tree module (7) and Data Post module (8);
Multiplication tree module (7), for carrying out multiplying to the data of data allocation module (6), will output to Data Post module (8) after operation result cut position;
Data Post module (8), for carrying out plus/minus computing according to control signal to the output data of data allocation module (6), the output data of multiplication tree module (7), operation result is outputted to data point reuse module (5) and plug-in memory module (4).
2. configurable radar digital signal processing device according to claim 1, it is characterized in that, described Logic control module (1) comprising: the first configuration register (11), the second configuration register (12) and a control module (13); This first configuration register (11) is for the pattern configurations information of storage of processor, and this second configuration register (12) is for memory length configuration information; The input end of control module (13) is connected with the second configuration register (12) with the first configuration register (11), under the control of the first configuration register (11), the second configuration register (12) and the outside data enable signal inputted, produce control signal, export to address generating module (2), data point reuse module (5), data allocation module (6) and Data Post module (8).
3. configurable radar digital signal processing device according to claim 1, it is characterized in that, described data point reuse module (5) comprising: maximum value unit (51), a highest significant position unit (52) and a data shifts/lock unit (53); Maximum value unit (51) exports the maximum value of data for finding out Data Post module (8), and exports to highest significant position unit (52); Highest significant position unit (52) for finding out the highest significant position of maximum value, and exports to data shifts/lock unit (53); Data shifts/lock unit (53) for according to control signal and highest significant position, the output data to plug-in memory module (4) are shifted/synchronous, and export to data allocation module (6).
4. configurable radar digital signal processing device according to claim 1, it is characterized in that, described Data Post module (8) comprising: first data selection unit (81), the second data selection unit (82), a cut position unit (83) and four plus/minus method unit;
First data selection unit (81), for the control signal transmitted according to control module (1), from the output data of data allocation module (6), the output data of multiplication tree module (7), the output data of the first plus/minus method unit (84) and constant 0, select wherein two data and export to the first plus/minus method unit (84), select one of them data and export to the 3rd plus/minus method unit (86);
First plus/minus method unit (84), two data for exporting the first data selection unit (81) carry out plus/minus computing, and operation result are exported to data selection unit (81) and the 3rd plus/minus method unit (86);
3rd plus/minus method unit (86), for carrying out plus/minus computing to the output data of the first data selection unit (81) and the output data of the first plus/minus method unit (84), result is exported to cut position unit (83);
Second data selection unit (82), for the control signal transmitted according to control module (1), from the output data of data allocation module (6), the output data of multiplication tree module (7), the output data of the second plus/minus method unit (85) and constant 0, select wherein two data and export to the second plus/minus method unit (85), select one of them data and export to the 4th plus/minus method unit (87);
Second plus/minus method unit (85), carries out plus/minus computing for two data exported the second data selection unit (82), operation result is exported to the 4th plus/minus method unit (87);
4th plus/minus method unit (87), for carrying out plus/minus computing to the output data of the second data selection unit (82) and the output data of the second plus/minus method unit (85), operation result is exported to cut position unit (83);
Cut position unit (83), for exporting to plug-in memory module (4) and data point reuse module (5) after the Output rusults cut position to the 3rd plus/minus method unit (86) and the 4th plus/minus method unit (87).
5. utilize the processor of claim 1 to carry out a method for radar digital signal processing, comprise the steps:
(1) initial parameter configuration:
User by processor mode configuration information stored in the first configuration register, by length configuration information stored in the second configuration register, by the butterfly coefficient needed for FFT/IFFT computing stored in butterfly coefficient module, by the coefficient of low-pass filtering, the coefficient of matched filtering stored in plug-in memory module;
(2) control signal is produced:
When data enable signal is high level, processor enters duty, the value of working mark signal is high level, unison counter starts counting, according to the first configuration register and the second configuration register state value, counter judges whether counting terminates, and if so, then the value saltus step of working mark signal is low level, if not, then the value of working mark signal keeps high level;
When working mark signal is high level, the control module of Logic control module produces four control signals, first control signal is for controlling address generating module calculated address signal, second control signal be used for control data adjusting module to data be shifted/synchronous, 3rd control signal is used for control data distribution module and selects data, and the 4th control signal is used for control data post-processing module and carries out plus/minus computing to after data selection;
(3) computing has been judged whether:
Judge whether working mark signal is low level, and if so, then computing completes, if not, then computing does not complete, and performs step (4);
(4) address signal is produced:
Address produces signaling module under the control of the first control signal, and what produce butterfly coefficient module reads address signal, and what produce plug-in memory module reads address signal and writing address signal thereof simultaneously;
(5) data encasement:
Address signal of reading according to plug-in memory module reads data and outputs to data point reuse module, and according to the second control signal to data be shifted/synchronous after this result is delivered to data allocation module; Address signal of reading according to butterfly coefficient module reads butterfly coefficient, and these data are outputted to data allocation module; Receive outside input data, these data are outputted to data allocation module;
(6) data are distributed:
Data allocation module, under the control of the 3rd control signal, selects data from the output data of step (5), outputs to multiplication tree module, Data Post module;
(7) multiplying:
Multiplication tree module exports data to step (6) and carries out multiplying, outputs to Data Post module after the result of acquisition carries out cut position;
(8) Data Post:
Data Post module, under the control of the 4th control signal, is carried out plus/minus computing after selecting, will flow to plug-in memory module, data point reuse module after result of calculation cut position to the output data of step (6), step (7);
(9) data store:
The result of calculation of Data Post module is outputted to data point reuse module, finds out and export the maximum value of data and the highest significant position of this maximum value; The result of calculation of Data Post module is write in plug-in memory module, returns step (3).
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