CN104865854A - Chip control method and device - Google Patents
Chip control method and device Download PDFInfo
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- CN104865854A CN104865854A CN201510133711.0A CN201510133711A CN104865854A CN 104865854 A CN104865854 A CN 104865854A CN 201510133711 A CN201510133711 A CN 201510133711A CN 104865854 A CN104865854 A CN 104865854A
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- control signal
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
Abstract
The invention provides a chip control method and device. According to the chip control method and device, a first time value, a second time value and the ending period of a baseband processing chip in a first state are adopted as basis for switching between various kinds of states of a radio frequency transmitting-receiving chip, and signals outputted by the pins of the baseband processing chip are not adopted as switching basis for the radio frequency transmitting-receiving chip any more, and therefore, as long as the first time value and the second time value are set according to the working time sequence of the radio frequency transmitting-receiving chip, correct collaboration of the radio frequency transmitting-receiving chip under different working time sequences and the use of the baseband processing chip can be realized, and thus, normal communication can be realized.
Description
Technical field
The application relates to electronic information field, particularly relates to a kind of chip controls method and device.
Background technology
In the little base station design of LTE, need to utilize two pieces of different chips to realize the transmitting-receiving of radiofrequency signal and the process of baseband signal, the most frequently used way uses rf chip (such as chip AD9361) to realize radio-frequency receiving-transmitting, uses baseband processing chip (such as chip BSC9132) to realize Base-Band Processing.
Due to rf chip (such as chip AD9361) be operated in tdd mode time, the start-up time of D/A conversion unit needs about 18us, so there is the large problem of time delay, and rf chip (such as chip AD9361) is when being operated in fdd mode, time delay can significantly reduce.But because baseband processing chip (such as chip BSC9132) is operated in tdd mode, in this case, the work schedule of two chip blocks is different, if directly carry out the communication of data, link is by cisco unity malfunction.
Visible, when rf chip is different from the work schedule of baseband processing chip, how to realize both proper communications, become current problem demanding prompt solution.
Summary of the invention
This application provides a kind of control method and chip controls device of chip, object is to solve when rf chip is different from the work schedule of baseband processing chip, how to realize the problem of both proper communications.
To achieve these goals, this application provides following technical scheme:
A kind of chip controls method, comprising:
If rf chip is in the flush cycle of the second state, then after the flush cycle of described second state continues very first time value, the first control signal is sent to described rf chip, described first control signal is used for the latent period described rf chip being switched to the first state, and described very first time value sets according to the work schedule of described rf chip;
If described rf chip is after the latent period of described first state continues the second time value, the second control signal is sent to described rf chip, described second control signal is used for the beginning cycle described rf chip being switched to described first state, and described second time value sets according to the work schedule of described rf chip;
If described rf chip is at the durations of described first state, then when detecting that baseband processing chip is in the end period of described first state, send the 3rd control signal to described rf chip, described 3rd control signal is used for the end period described rf chip being switched to described first state.
Alternatively, detect the method that described baseband processing chip is in the end period of described first state to comprise:
When described baseband processing chip is in the durations of described first state, if detect that the output of the Enable pin of described baseband processing chip is rising edge, then determine that described baseband processing chip is switched to the end period of described first state.
Alternatively, the method that the described baseband processing chip of described detection is in the end period of described first state also comprises:
When described baseband processing chip is in waiting status, if detect that the output of the Enable pin of described baseband processing chip is rising edge and the output of TXNRX pin is high level time, determine that described baseband processing chip is switched to the beginning cycle of transmission state;
When described baseband processing chip is when the beginning cycle of described transmission state, if the clock signal of next clock period detected, then determine that described baseband processing chip is switched to the durations of transmission state;
When described baseband processing chip is in waiting status, if detect that the output of the Enable pin of described baseband processing chip is rising edge and the output of TXNRX pin is low level time, determine that described baseband processing chip is switched to the beginning cycle of accepting state;
When the beginning cycle of described baseband processing chip in described accepting state, if the clock signal of next clock period detected, then determine that described baseband processing chip is switched to the durations of accepting state.
Alternatively, described method also comprises:
When described rf chip is in the beginning cycle of described first state, if the clock signal of next clock period detected, then send the 4th control signal to described rf chip, described 4th control signal is used for the durations described rf chip being switched to described first state;
When described rf chip is in the end period of described first state, if the clock signal of next clock period detected, then send the 5th control signal to described rf chip, described 5th control signal is used for the flush cycle described rf chip being switched to described first state.
Alternatively, be transmission state in described first state, when described second state is accepting state, describedly sends the first control signal to described rf chip and comprise:
To the Enable pin output signal 0 of described rf chip, to the TXNRX pin output signal 0 of described rf chip;
Describedly send the second control signal to described rf chip and comprise:
To the Enable pin output signal 0 of described rf chip, to the TXNRX pin output signal 1 of described rf chip;
Describedly send the 3rd control signal to described rf chip and comprise:
To the Enable pin output signal 0 of described rf chip, to the TXNRX pin output signal 1 of described rf chip;
Be accepting state in described first state, when described second state is transmission state, describedly sends the first control signal to described rf chip and comprise:
To the Enable pin output signal 0 of described rf chip, to the TXNRX pin output signal 0 of described rf chip;
Describedly send the second control signal to described rf chip and comprise:
To the Enable pin output signal 1 of described rf chip, to the TXNRX pin output signal 0 of described rf chip;
Describedly send the 3rd control signal to described rf chip and comprise:
To the Enable pin output signal 1 of described rf chip, to the TXNRX pin output signal 0 of described rf chip;
Be transmission state in described first state, when described second state is accepting state, describedly sends the 4th control signal to described rf chip and comprise:
To the Enable pin output signal 0 of described rf chip, to the TXNRX pin output signal 1 of described rf chip;
Describedly send the 5th control signal to described rf chip and comprise:
To the Enable pin output signal 0 of described rf chip, to the TXNRX pin output signal 1 of described rf chip;
Be accepting state in described first state, when described second state is transmission state, describedly sends the 4th control signal to described rf chip and comprise:
To the Enable pin output signal 1 of described rf chip, to the TXNRX pin output signal 0 of described rf chip;
Describedly send the 5th control signal to described rf chip and comprise:
To the Enable pin output signal 1 of described rf chip, to the TXNRX pin output signal 0 of described rf chip.
A kind of chip controls, comprising:
First state machine, if for the flush cycle of rf chip in the second state, then after the flush cycle of described second state continues very first time value, the first control signal is sent to described rf chip, described first control signal is used for the latent period described rf chip being switched to the first state, and described very first time value sets according to the work schedule of described rf chip 1; If described rf chip is after the latent period of described first state continues the second time value, the second control signal is sent to described rf chip, described second control signal is used for the beginning cycle described rf chip being switched to described first state, and described second time value sets according to the work schedule of described rf chip; If described rf chip is at the durations of described first state, then when detecting that baseband processing chip is in the end period of described first state, send the 3rd control signal to described rf chip, described 3rd control signal is used for the end period described rf chip being switched to described first state.
Alternatively, described device also comprises:
Second state machine, the end period of described first state is in for detecting described baseband processing chip, the concrete grammar that the described baseband processing chip of described detection is in the end period of described first state comprises: when described baseband processing chip is in the durations of described first state, if detect that the output of the Enable pin of described baseband processing chip is rising edge, then determine that described baseband processing chip is switched to the end period of described first state.
Alternatively, described second state machine also for:
When described baseband processing chip is in waiting status, if detect that the output of the Enable pin of described baseband processing chip is rising edge and the output of TXNRX pin is high level time, determine that described baseband processing chip is switched to the beginning cycle of transmission state; When described baseband processing chip is when the beginning cycle of described transmission state, if the clock signal of next clock period detected, then determine that described baseband processing chip is switched to the durations of transmission state; When described baseband processing chip is in waiting status, if detect that the output of the Enable pin of described baseband processing chip is rising edge and the output of TXNRX pin is low level time, determine that described baseband processing chip is switched to the beginning cycle of accepting state; When the beginning cycle of described baseband processing chip in described accepting state, if the clock signal of next clock period detected, then determine that described baseband processing chip is switched to the durations of accepting state.
Alternatively, described first state machine also for:
When described rf chip is in the beginning cycle of described first state, if the clock signal of next clock period detected, then send the 4th control signal to described rf chip, described 4th control signal is used for the durations described rf chip being switched to described first state;
When described rf chip is in the end period of described first state, if the clock signal of next clock period detected, then send the 5th control signal to described rf chip, described 5th control signal is used for the flush cycle described rf chip being switched to described first state.
Alternatively, be transmission state at described first state machine in described first state, when described second state is accepting state, described first state machine is used for sending the first control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 0, to described rf chip TXNRX pin output signal 0;
Described first state machine is used for describedly sending the second control signal to described rf chip and comprising:
Described first state machine specifically for, to described rf chip Enable pin output signal 0, to described rf chip TXNRX pin output signal 1;
Described first state machine is used for describedly sending the 3rd control signal to described rf chip and comprising:
Described first state machine specifically for, to described rf chip Enable pin output signal 0, to described rf chip TXNRX pin output signal 1;
Be accepting state in described first state, when described second state is transmission state, described first state machine is used for sending the first control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 0, to described rf chip TXNRX pin output signal 0;
Described first state machine is used for sending the second control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 1, to described rf chip TXNRX pin output signal 0;
Described first state machine is used for sending the 3rd control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 1, to described rf chip TXNRX pin output signal 0;
Be transmission state in described first state, when described second state is accepting state, described first state machine is used for sending the 4th control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 0, to described rf chip TXNRX pin output signal 1;
Described first state machine is used for sending the 5th control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 0, to described rf chip TXNRX pin output signal 1;
Be accepting state in described first state, when described second state is transmission state, described first state machine is used for sending the 4th control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 1, to described rf chip TXNRX pin output signal 0;
Described first state machine is used for described rf chip transmission the 5th control signal and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 1, to described rf chip TXNRX pin output signal 0.
Chip controls method described in the application and device, use very first time value, the end period that second time value and baseband processing chip are in described first state carries out the foundation switched between each state as rf chip, and the signal that the pin not re-using baseband processing chip exports is as the switching foundation of rf chip, therefore, as long as according to work schedule setting very first time value and second time value of rf chip, the rf chip that can realize under different operating sequential cooperates with use the correct of baseband processing chip, thus realize the object of proper communication.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the application, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic diagram that rf chip AD9361 is operated in the independent fdd mode controlled of transmitting-receiving;
Fig. 2 is the sequential control schematic diagram of baseband processing chip BSC9132;
The process flow diagram of Fig. 3 a kind of chip controls method disclosed in the embodiment of the present application;
Fig. 4 is the process flow diagram that the described baseband processing chip BSC9132 of the disclosed detection of the embodiment of the present application is in the method for the end period of described first state;
The structural representation of Fig. 5 chip controls device disclosed in the embodiment of the present application.
Embodiment
Chip controls method disclosed in the embodiment of the present application, is used in the communication system that rf chip and baseband processing chip form jointly.Object is to make rf chip be operated in the independent fdd mode controlled of transmitting-receiving, and baseband processing chip is operated in ENABLE/TXNRX pin and controls (ENABLE/TXNRX PIN CONTROL) tdd mode, thus reduces the time delay of communication system.
In the embodiment of the application, be all described for rf chip AD9361 and baseband processing chip BSC9132.It should be noted that, method described in the application and device the rf chip that is suitable for and baseband processing chip be not limited to above-mentioned concrete chip, as long as use the chip of JESD207 interface standard, be all applicable to the method described in the application and device.
In above-mentioned communication system, as shown in Figure 1, the sequential control schematic diagram of baseband processing chip BSC9132 as shown in Figure 2 for the sequential control schematic diagram of rf chip AD9361.
Below in conjunction with the accompanying drawing in the embodiment of the present application, be clearly and completely described the technical scheme in the embodiment of the present application, obviously, described embodiment is only some embodiments of the present application, instead of whole embodiments.Based on the embodiment in the application, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the application's protection.
A kind of chip controls method disclosed in the embodiment of the present application, as shown in Figure 3, comprising:
S301: if rf chip AD9361 is at the data buffering period of state of the second state, then after the flush cycle of described second state continues very first time value, send the first control signal to described rf chip AD9361, described first control signal is used for the latent period described rf chip AD9361 being switched to the first state;
Wherein, very first time value sets according to the work schedule of described rf chip AD9361, such as, very first time value can be 6 ADC_CLK/64 clock period, and wherein ADC_CLK is sampling clock that user sets, the D/A conversion unit of chip coupling therewith;
In the present embodiment, the first state is transmission state, and the second state is accepting state, for convenience of description, in Fig. 3, uses tx to represent emission state, uses rx to represent accepting state.Use rfic_state_cnt1 to represent the time that the flush cycle of accepting state continues, use rfic_tx_flush_cnt to represent very first time value, use rfic_tx_wait to represent the latent period of transmission state.
In the present embodiment, the specific implementation sending the first control signal to described rf chip AD9361 can be: to the Enable pin output signal 0 of described rf chip AD9361, to the TXNRX pin output signal 0 of described rf chip AD9361.
S302: if rf chip AD9361 is after the latent period rfic_tx_wait of the state of transmission continues the second time value rfic_tx_switch_cnt, send the second control signal to rf chip AD9361, the second control signal is used for beginning cycle rfic_tx_start rf chip AD9361 being switched to transmission state;
Wherein, the second time value sets according to the work schedule of described rf chip AD9361;
In the present embodiment, the second time value sets according to the work schedule of described rf chip AD9361, also can be 6 ADC_CLK/64 clock period.
In Fig. 3, rfic_state_cnt2 is used to represent the time that rf chip AD9361 continues at rfic_tx_wait.
In the present embodiment, the specific implementation sending the second control signal to rf chip AD9361 can be: to the Enable pin output signal 0 of rf chip AD9361, to the TXNRX pin output signal 1 of rf chip AD9361.
S303: when rf chip AD9361 is in the beginning cycle rfic_tx_start of transmission state, if the clock signal of next clock period detected, to the Enable pin output signal 0 of rf chip AD9361, to the TXNRX pin output signal 1 of described rf chip AD9361, for rf chip AD9361 being switched to the durations rfic_tx of transmission state;
In S303, same as the prior art, still use the clock period of rf chip AD9361 to carry out switching to it and control.
S304: if rf chip AD9361 is at the durations rfic_tx of the state of transmission, then when detecting that baseband processing chip BSC9132 is in the end period of transmission state, send the 3rd control signal to rf chip AD9361, described 3rd control signal is used for end period rfic_tx_end rf chip AD9361 being switched to transmission state;
Wherein, the specific implementation sending the 3rd control signal to rf chip AD9361 can be: to the Enable pin output signal 0 of rf chip AD9361, to the TXNRX pin output signal 1 of rf chip AD9361.
In Fig. 3, use aic_state to represent the state that baseband processing chip BSC9132 is current, use aic_state_tx_end to represent the end period of the transmission state of baseband processing chip BSC9132.
S305: when rf chip AD9361 is in the end period rfic_tx_end of described first state, if the clock signal of next clock period detected, then to the Enable pin output signal 0 of rf chip AD9361, to the TXNRX pin output signal 1 of rf chip AD9361, for rf chip AD9361 being switched to the flush cycle rfic_tx_flush of transmission state;
Above for after being switched to transmission state, send switching condition and the flow process in each cycle of state, as shown in fig. 1, switching condition and the flow process in each cycle under accepting state are similar, comprise the following steps:
S306: if rf chip AD9361 is at the flush cycle rfic_tx_flush of the state of transmission, then after the flush cycle rfic_tx_flush of the state of transmission continues very first time value, to the Enable pin output signal 0 of rf chip AD9361, to the TXNRX pin output signal 0 of described rf chip AD9361, for rf chip AD9361 being switched to the latent period rfic_rx_wait of accepting state;
S307: if rf chip AD9361 is after the latent period of accepting state continues rfic_rx_wait second time value, to the Enable pin output signal 1 of rf chip AD9361, to the TXNRX pin output signal 0 of described rf chip AD9361, for rf chip AD9361 being switched to the beginning cycle rfic_rx_start of accepting state;
S308: when rf chip AD9361 is in the beginning cycle rfic_rx_start of accepting state, if the clock signal of next clock period detected, to the Enable pin output signal 1 of rf chip AD9361, to the TXNRX pin output signal 0 of rf chip AD9361, for rf chip AD9361 is switched to accepting state durations rfic_rx;
S309: if rf chip AD9361 is at the durations rfic_rx of accepting state, then when detecting that baseband processing chip BSC9132 is in the end period of accepting state, to the Enable pin output signal 1 of rf chip AD9361, to the TXNRX pin output signal 0 of rf chip AD9361, for rf chip AD9361 being switched to the end period rfic_rx_end of accepting state;
S310: when rf chip AD9361 is in the end period rfic_tx_end of accepting state, if the clock signal of next clock period detected, then to the Enable pin output signal 1 of rf chip AD9361, to the TXNRX pin output signal 0 of rf chip AD9361, for rf chip AD9361 being switched to the flush cycle rfic_rx_flush of accepting state.
As can be seen from above-mentioned steps, in the present embodiment, use very first time value, the second time value and the baseband processing chip current residing cycle to be foundation, radio frequency transceiving chip carries out switching and controls, therefore, it is possible to ensure the correct work of two chips be operated under different sequential.Thus making in a tdd system, rf chip can be operated in fdd mode, is conducive to the reduction of communication delay.
Further, as can be seen from Figure 3, the method described in the present embodiment is adopted, only need can realize above-mentioned purpose by ten states, control compared to existing state machine, the negligible amounts (not having waiting status) of the state used in the present embodiment, therefore, simple flow is easy to.
In the present embodiment, as previously mentioned, the end period that baseband processing chip BSC9132 is in described first state uses as one of condition switched, and is in the method for the end period of described first state the following detailed description of the described baseband processing chip BSC9132 of detection.
As shown in Figure 4, described method comprises:
S401: when baseband processing chip BSC9132 is in waiting status aic_wait, if detect that the output of the Enable pin of baseband processing chip BSC9132 is rising edge and the output of TXNRX pin is high level time, determine that baseband processing chip BSC9132 is switched to the beginning cycle tx_atart of transmission state;
S402: when baseband processing chip BSC9132 is when the beginning cycle tx_atart of the state of transmission, if the clock signal of next clock period detected, then determine that baseband processing chip BSC9132 is switched to the durations aic_tx of transmission state;
S403: when baseband processing chip BSC9132 is in the durations aic_tx of transmission state, if detect that the output of the Enable pin of baseband processing chip BSC9132 is rising edge, then determine that described baseband processing chip BSC9132 is switched to the end period tx_end of described first state;
S404: if the clock signal of next clock period detected, then determine that baseband processing chip BSC9132 is switched to waiting status aic_wait;
S405: when baseband processing chip BSC9132 is in waiting status aic_wait, if detect that the output of the Enable pin of baseband processing chip BSC9132 is rising edge and the output of TXNRX pin is low level time, determine that described baseband processing chip BSC9132 is switched to the beginning cycle tx_atart of accepting state;
S406: as the beginning cycle tx_atart of baseband processing chip BSC9132 in accepting state, if the clock signal of next clock period detected, then determines that baseband processing chip BSC9132 is switched to the durations aic_rx of accepting state;
S407: when baseband processing chip BSC9132 is in the durations aic_rx of accepting state, if detect that the output of the Enable pin of baseband processing chip BSC9132 is rising edge, then determine that baseband processing chip BSC9132 is switched to the end period rx_end of accepting state;
S408: if the clock signal of next clock period detected, then determine that baseband processing chip BSC9132 is switched to waiting status aic_wait.
Visible, in the present embodiment, first the signal by exporting Enable pin and the TXNRX pin of baseband processing chip BSC9132 carries out decoding, use the switching condition of result as the period of state of rf chip AD9361 of decoding, thus the output signal of the baseband processing chip BSC9132 of realization foundation tdd mode is to the correct control of the rf chip AD9361 of fdd mode.
With said method embodiment accordingly, the embodiment of the present application also discloses a kind of chip controls device, as shown in Figure 5, comprising: the first state machine 501 and the second state machine 502.
Wherein, the first state machine is used for:
If rf chip AD9361 is in the flush cycle of the second state, then after the flush cycle of described second state continues very first time value, the first control signal is sent to described rf chip AD9361, described first control signal is used for the latent period described rf chip AD9361 being switched to the first state, and described very first time value sets according to the work schedule of described rf chip AD9361;
If described rf chip AD9361 is after the latent period of described first state continues the second time value, the second control signal is sent to described rf chip AD9361, described second control signal is used for the beginning cycle described rf chip AD9361 being switched to described first state, and described second time value sets according to the work schedule of described rf chip AD9361;
If described rf chip AD9361 is at the durations of described first state, then when detecting that baseband processing chip BSC9132 is in the end period of described first state, send the 3rd control signal to described rf chip AD9361, described 3rd control signal is used for the end period described rf chip AD9361 being switched to described first state.
Particularly, first state machine is transmission state in described first state, when described second state is accepting state, the specific implementation sending the first control signal to described rf chip AD9361 can be: to the Enable pin output signal 0 of described rf chip AD9361, to the TXNRX pin output signal 0 of described rf chip AD9361; The specific implementation sending the second control signal to described rf chip AD9361 can be: to the Enable pin output signal 0 of described rf chip AD9361, to the TXNRX pin output signal 1 of described rf chip AD9361; The specific implementation sending the 3rd control signal to described rf chip AD9361 can be: to the Enable pin output signal 0 of described rf chip AD9361, to the TXNRX pin output signal 1 of described rf chip AD9361;
Be accepting state in described first state, when described second state is transmission state, the specific implementation that first state machine sends the first control signal to described rf chip AD9361 can be: to the Enable pin output signal 0 of described rf chip AD9361, to the TXNRX pin output signal 0 of described rf chip AD9361; The specific implementation sending the second control signal to described rf chip AD9361 can be: to the Enable pin output signal 1 of described rf chip AD9361, to the TXNRX pin output signal 0 of described rf chip AD9361; The specific implementation sending the 3rd control signal to described rf chip AD9361 can be: to the Enable pin output signal 1 of described rf chip AD9361, to the TXNRX pin output signal 0 of described rf chip AD9361.
Further, described first state machine can also be used for:
When described rf chip AD9361 is in the beginning cycle of described first state, if the clock signal of next clock period detected, then send the 4th control signal to described rf chip AD9361, described 4th control signal is used for the durations described rf chip AD9361 being switched to described first state;
When described rf chip AD9361 is in the end period of described first state, if the clock signal of next clock period detected, then send the 5th control signal to described rf chip AD9361, described 5th control signal is used for the flush cycle described rf chip AD9361 being switched to described first state.
Particularly, be transmission state in described first state, when described second state is accepting state, the specific implementation that first state machine sends the 4th control signal to described rf chip AD9361 can be: to the Enable pin output signal 0 of described rf chip AD9361, to the TXNRX pin output signal 1 of described rf chip AD9361; The specific implementation that first state machine sends the 5th control signal to described rf chip AD9361 can be: to the Enable pin output signal 0 of described rf chip AD9361, to the TXNRX pin output signal 1 of described rf chip AD9361;
Be accepting state in described first state, when described second state is transmission state, the specific implementation that first state machine sends the 4th control signal to described rf chip AD9361 can be: to the Enable pin output signal 1 of described rf chip AD9361, to the TXNRX pin output signal 0 of described rf chip AD9361; The specific implementation that first state machine sends the 5th control signal to described rf chip AD9361 can be: to the Enable pin output signal 1 of described rf chip AD9361, to the TXNRX pin output signal 0 of described rf chip AD9361.
Second state machine may be used for: detect the end period that described baseband processing chip BSC9132 is in described first state, the concrete grammar that described detection described baseband processing chip BSC9132 is in the end period of described first state comprises: when described baseband processing chip BSC9132 is in the durations of described first state, if detect that the output of the Enable pin of described baseband processing chip BSC9132 is rising edge, then determine that described baseband processing chip BSC9132 is switched to the end period of described first state.
Further, second state machine can also be used for: when described baseband processing chip BSC9132 is in waiting status, if detect that the output of the Enable pin of described baseband processing chip BSC9132 is rising edge and the output of TXNRX pin is high level time, determine that described baseband processing chip BSC9132 is switched to the beginning cycle of transmission state; When described baseband processing chip BSC9132 is when the beginning cycle of described transmission state, if the clock signal of next clock period detected, then determine that described baseband processing chip BSC9132 is switched to the durations of transmission state; When described baseband processing chip BSC9132 is in waiting status, if detect that the output of the Enable pin of described baseband processing chip BSC9132 is rising edge and the output of TXNRX pin is low level time, determine that described baseband processing chip BSC9132 is switched to the beginning cycle of accepting state; When the beginning cycle of described baseband processing chip BSC9132 in described accepting state, if the clock signal of next clock period detected, then determine that described baseband processing chip BSC9132 is switched to the durations of accepting state.
In the present embodiment, the concrete switching control flow of the first state machine and the second state machine can see shown in Fig. 3 and Fig. 4.
For the device described in the present embodiment can be applied in field programmable gate array (Field-Programmable Gate Array, FPGA), Fig. 5 is the connection diagram of FPGA and baseband processing chip BSC9132 and rf chip AD9361.FPGA can use more jumbo spartan-6 series.
Visible, in the present embodiment, with FPGA, decoding is carried out to the control signal that BSC9132 sends, realize the correct control to AD9361 to the control signal made new advances; Consider real work situation, nearly AD9361 side state machine compared to AD9361 internal state machine, many one of four states, and by introducing parameter, more easily Control timing sequence; The cascade of two finite state machines, realizes the docking of two different working modes in FPGA both sides.
If the function described in the embodiment of the present application method using the form of SFU software functional unit realize and as independently production marketing or use time, can be stored in a computing equipment read/write memory medium.Based on such understanding, the part of the part that the embodiment of the present application contributes to prior art or this technical scheme can embody with the form of software product, this software product is stored in a storage medium, comprising some instructions in order to make a computing equipment (can be personal computer, server, mobile computing device or the network equipment etc.) perform all or part of step of method described in each embodiment of the application.And aforesaid storage medium comprises: USB flash disk, portable hard drive, ROM (read-only memory) (ROM, Read-OnlyMemory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. various can be program code stored medium.
In this instructions, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiment, between each embodiment same or similar part mutually see.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the application.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein when not departing from the spirit or scope of the application, can realize in other embodiments.Therefore, the application can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a chip controls method, is characterized in that, comprising:
If rf chip is in the data buffering state flush cycle of the second state, then after the flush cycle of described second state continues very first time value, the first control signal is sent to described rf chip, described first control signal is used for the latent period described rf chip being switched to the first state, and described very first time value sets according to the work schedule of described rf chip;
If described rf chip is after the latent period of described first state continues the second time value, the second control signal is sent to described rf chip, described second control signal is used for the beginning cycle described rf chip being switched to described first state, and described second time value sets according to the work schedule of described rf chip;
If described rf chip is at the durations of described first state, then when detecting that baseband processing chip is in the end period of described first state, send the 3rd control signal to described rf chip, described 3rd control signal is used for the end period described rf chip being switched to described first state.
2. method according to claim 1, is characterized in that, detects the method that described baseband processing chip is in the end period of described first state and comprises:
When described baseband processing chip is in the durations of described first state, if detect that the output of the Enable pin of described baseband processing chip is rising edge, then determine that described baseband processing chip is switched to the end period of described first state.
3. method according to claim 2, is characterized in that, the method that the described baseband processing chip of described detection is in the end period of described first state also comprises:
When described baseband processing chip is in waiting status, if detect that the output of the Enable pin of described baseband processing chip is rising edge and the output of TXNRX pin is high level time, determine that described baseband processing chip is switched to the beginning cycle of transmission state;
When described baseband processing chip is when the beginning cycle of described transmission state, if the clock signal of next clock period detected, then determine that described baseband processing chip is switched to the durations of transmission state;
When described baseband processing chip is in waiting status, if detect that the output of the Enable pin of described baseband processing chip is rising edge and the output of TXNRX pin is low level time, determine that described baseband processing chip is switched to the beginning cycle of accepting state;
When the beginning cycle of described baseband processing chip in described accepting state, if the clock signal of next clock period detected, then determine that described baseband processing chip is switched to the durations of accepting state.
4. according to the method in claim 2 or 3, it is characterized in that, also comprise:
When described rf chip is in the beginning cycle of described first state, if the clock signal of next clock period detected, then send the 4th control signal to described rf chip, described 4th control signal is used for the durations described rf chip being switched to described first state;
When described rf chip is in the end period of described first state, if the clock signal of next clock period detected, then send the 5th control signal to described rf chip, described 5th control signal is used for the flush cycle described rf chip being switched to described first state.
5. method according to claim 4, is characterized in that, is transmission state in described first state, when described second state is accepting state, describedly sends the first control signal to described rf chip and comprises:
To the Enable pin output signal 0 of described rf chip, to the TXNRX pin output signal 0 of described rf chip;
Describedly send the second control signal to described rf chip and comprise:
To the Enable pin output signal 0 of described rf chip, to the TXNRX pin output signal 1 of described rf chip;
Describedly send the 3rd control signal to described rf chip and comprise:
To the Enable pin output signal 0 of described rf chip, to the TXNRX pin output signal 1 of described rf chip;
Be accepting state in described first state, when described second state is transmission state, describedly sends the first control signal to described rf chip and comprise:
To the Enable pin output signal 0 of described rf chip, to the TXNRX pin output signal 0 of described rf chip;
Describedly send the second control signal to described rf chip and comprise:
To the Enable pin output signal 1 of described rf chip, to the TXNRX pin output signal 0 of described rf chip;
Describedly send the 3rd control signal to described rf chip AD9361 and comprise:
To the Enable pin output signal 1 of described rf chip, to the TXNRX pin output signal 0 of described rf chip;
Be transmission state in described first state, when described second state is accepting state, describedly sends the 4th control signal to described rf chip and comprise:
To the Enable pin output signal 0 of described rf chip, to the TXNRX pin output signal 1 of described rf chip;
Describedly send the 5th control signal to described rf chip and comprise:
To the Enable pin output signal 0 of described rf chip, to the TXNRX pin output signal 1 of described rf chip;
Be accepting state in described first state, when described second state is transmission state, describedly sends the 4th control signal to described rf chip and comprise:
To the Enable pin output signal 1 of described rf chip, to the TXNRX pin output signal 0 of described rf chip;
Describedly send the 5th control signal to described rf chip and comprise:
To the Enable pin output signal 1 of described rf chip, to the TXNRX pin output signal 0 of described rf chip.
6. a chip controls device, is characterized in that, comprising:
First state machine, if for the flush cycle of rf chip in the second state, then after the flush cycle of described second state continues very first time value, the first control signal is sent to described rf chip, described first control signal is used for the latent period described rf chip being switched to the first state, and described very first time value sets according to the work schedule of described rf chip; If described rf chip is after the latent period of described first state continues the second time value, the second control signal is sent to described rf chip, described second control signal is used for the beginning cycle described rf chip being switched to described first state, and described second time value sets according to the work schedule of described rf chip; If described rf chip is at the durations of described first state, then when detecting that baseband processing chip is in the end period of described first state, send the 3rd control signal to described rf chip, described 3rd control signal is used for the end period described rf chip being switched to described first state.
7. chip controls device according to claim 6, also comprises:
Second state machine, the end period of described first state is in for detecting described baseband processing chip, the concrete grammar that the described baseband processing chip of described detection is in the end period of described first state comprises: when described baseband processing chip is in the durations of described first state, if detect that the output of the Enable pin of described baseband processing chip is rising edge, then determine that described baseband processing chip is switched to the end period of described first state.
8. chip controls device according to claim 7, is characterized in that, described second state machine also for:
When described baseband processing chip is in waiting status, if detect that the output of the Enable pin of described baseband processing chip is rising edge and the output of TXNRX pin is high level time, determine that described baseband processing chip is switched to the beginning cycle of transmission state; When described baseband processing chip is when the beginning cycle of described transmission state, if the clock signal of next clock period detected, then determine that described baseband processing chip is switched to the durations of transmission state; When described baseband processing chip is in waiting status, if detect that the output of the Enable pin of described baseband processing chip is rising edge and the output of TXNRX pin is low level time, determine that described baseband processing chip is switched to the beginning cycle of accepting state; When the beginning cycle of described baseband processing chip in described accepting state, if the clock signal of next clock period detected, then determine that described baseband processing chip is switched to the durations of accepting state.
9. the chip controls device according to claim 7 or 8, is characterized in that, described first state machine also for:
When described rf chip is in the beginning cycle of described first state, if the clock signal of next clock period detected, then send the 4th control signal to described rf chip, described 4th control signal is used for the durations described rf chip being switched to described first state;
When described rf chip is in the end period of described first state, if the clock signal of next clock period detected, then send the 5th control signal to described rf chip, described 5th control signal is used for the flush cycle described rf chip being switched to described first state.
10. chip controls device according to claim 9, it is characterized in that, be transmission state at described first state machine in described first state, when described second state is accepting state, described first state machine is used for sending the first control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 0, to described rf chip TXNRX pin output signal 0;
Described first state machine is used for describedly sending the second control signal to described rf chip and comprising:
Described first state machine specifically for, to described rf chip Enable pin output signal 0, to described rf chip TXNRX pin output signal 1;
Described first state machine is used for describedly sending the 3rd control signal to described rf chip and comprising:
Described first state machine specifically for, to described rf chip Enable pin output signal 0, to described rf chip TXNRX pin output signal 1;
Be accepting state in described first state, when described second state is transmission state, described first state machine is used for sending the first control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 0, to described rf chip TXNRX pin output signal 0;
Described first state machine is used for sending the second control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 1, to described rf chip TXNRX pin output signal 0;
Described first state machine is used for sending the 3rd control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 1, to described rf chip TXNRX pin output signal 0;
Be transmission state in described first state, when described second state is accepting state, described first state machine is used for sending the 4th control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 0, to described rf chip TXNRX pin output signal 1;
Described first state machine is used for sending the 5th control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 0, to described rf chip TXNRX pin output signal 1;
Be accepting state in described first state, when described second state is transmission state, described first state machine is used for sending the 4th control signal to described rf chip and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 1, to described rf chip TXNRX pin output signal 0;
Described first state machine is used for described rf chip transmission the 5th control signal and comprises:
Described first state machine specifically for, to described rf chip Enable pin output signal 1, to described rf chip TXNRX pin output signal 0.
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