CN104914914A - Circuit structure and control method thereof - Google Patents
Circuit structure and control method thereof Download PDFInfo
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- CN104914914A CN104914914A CN201510231068.5A CN201510231068A CN104914914A CN 104914914 A CN104914914 A CN 104914914A CN 201510231068 A CN201510231068 A CN 201510231068A CN 104914914 A CN104914914 A CN 104914914A
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Abstract
The invention provides a circuit structure and a control method thereof. The circuit structure comprises a power wire, a constant current generating circuit, a low dropout linear voltage regulator, a positive pump circuit, an artificial circuit and a decoupling capacitor, and the artificial circuit is connected with the power wire through a first node; the constant current generating circuit is connected with the power wire through a second node, and the input end of the constant current generating circuit is connected with a reference current; one end of the decoupling capacitor is connected between the first node and the second node, and the other end of the decoupling capacitor is connected with ground; the constant current generating circuit is connected with the low dropout linear voltage regulator and the positive pump circuit through a third node, and the input end of the low dropout linear voltage regulator is connected with a reference voltage. According to the circuit structure, the voltage and current of the second node are kept stable through the constant current generating circuit and the low dropout linear voltage regulator, and the affect to the voltage of the power line from the positive pump circuit is reduced.
Description
Technical field
The present invention relates to integrated circuit (IC) design technical field, particularly relate to a kind of circuit structure and control method thereof.
Background technology
In the circuit design of imageing sensor, shown in figure 1, usually by positive pump circuit 2 for image sensor array (Panel Array) provides a voltage higher than the voltage AVDD of power lead 3.Under the excitation of clock signal clk, electric capacity C1, C2 of positive pump circuit 2 can carry out periodic charging and discharging, a final generation output voltage values higher than supply voltage, and its course of work is as follows:
When the first clock control signal CLK is low level, second clock control signal CLKb is high level, first nmos pass transistor MN1 ends, second nmos pass transistor MN2 conducting, first PMOS transistor MP1 cut-off, second PMOS transistor MP2 conducting, power lead 3 is charged to the second electric capacity C2 by Node B, and the first electric capacity C1 is charged to the 3rd electric capacity C3 by node D, then, the voltage of the first clock control signal CLK rises gradually, second clock control signal CLKb declines gradually, the voltage rise of the top crown of the second electric capacity C2, the voltage drop of the top crown of the first electric capacity C1, the gate source voltage Vgs1 of the first nmos pass transistor MN1 is made to increase, the gate source voltage Vgs2 of the second nmos pass transistor declines, the gate source voltage Vgsp1 of the first PMOS transistor MP1 rises, the gate source voltage Vgsp2 of the second PMOS transistor MP2 declines, second nmos pass transistor MN2 ends, first nmos pass transistor MN1 conducting, first PMOS transistor MP1 conducting, second PMOS transistor MP2 cut-off, power lead 3 is charged to the first electric capacity C1 by Node B, the charging and discharging currents at Node B place rises, second electric capacity C2 is charged to the 3rd electric capacity C3 by node C, when the first clock control signal CLK rises to high level voltage, second clock control signal drops to low level, along with the carrying out of the charging of the first electric capacity C1, the voltage of the top crown of the first electric capacity C1 raises, the gate source voltage Vgs1 of the first nmos pass transistor MN1 is declined, the gate source voltage Vgsp1 of the first PMOS transistor MP1 declines, and the gate source voltage Vgsp2 of the second PMOS transistor MP2 rises, thus the charging and discharging currents at Node B place declines, afterwards, the voltage drop of the first clock control signal CLK, the voltage rise of second clock control signal CLKb, the voltage drop of the top crown of the second electric capacity C2, the voltage rise of the top crown of the first electric capacity C1, the gate source voltage Vgs2 of the second nmos pass transistor MN2 rises, the gate source voltage Vgs1 of the first nmos pass transistor MN1 declines, first nmos pass transistor MN1 ends, second nmos pass transistor MN2 conducting, first PMOS transistor MP1 cut-off, second PMOS transistor MP2 conducting, Node B is charged to the second electric capacity C2, first electric capacity C1 is charged to the 3rd electric capacity C3 by node C, the charging and discharging currents at Node B place rises, finally, when the first clock control signal CLK drops to low level, when second clock control signal CLKb rises to high level, along with the charging of the second electric capacity C2, the voltage rise of the top crown of the second electric capacity C2, the grid source current Vgs2 of transistor seconds MN2 declines, and the charging and discharging currents at Node B place declines.Along with the change of the voltage signal cycles of the first clock control signal CLK, the charging and discharging currents also periodically rise and fall at Node B place, thus produce ripple, the voltage at Node B place changes thereupon.Thus interference is produced to the voltage at node A place, affect the performance of other mimic channels such as mimic channel 1 grade be connected with node A place dramatically., can impact the performance of imageing sensor meanwhile, cause the horizontal noise (Horizontal Noise) of large image.
In existing solution, be generally for positive pump circuit 2 provide an independent power supply (I/O Pad) make positive pump circuit 2 not with mimic channel 1 common source, reduce the impact that mimic channel is produced.Independent power supply can increase cost.Can also by arranging larger electric capacity of voltage regulation on supply voltage AVDD side in prior art, the electric capacity of setting increases the area of chip, thus also can increase cost.
Summary of the invention
The object of the invention is to, a kind of circuit structure and control method thereof are provided, weaken the interference of positive pump circuit to supply voltage.
For solving the problems of the technologies described above, the invention provides a kind of circuit structure, comprise power lead, constant-current generating circuit, low pressure difference linear voltage regulator, positive pump circuit, mimic channel and decoupling capacitor, described mimic channel is connected with described power lead with first node; Described constant-current generating circuit is connected with described power lead with Section Point, and the input end of described constant-current generating circuit connects a reference current; One end of described decoupling capacitor is connected between described first node and described Section Point, other end ground connection; Described constant-current generating circuit is connected with described low pressure difference linear voltage regulator and described positive pump circuit respectively with the 3rd node, and the input end of described low pressure difference linear voltage regulator connects a reference voltage.
Optionally, described positive pump circuit comprises:
Negative circuit, the input end of described negative circuit connects the first clock control signal, and the output terminal of described negative circuit connects second clock control signal;
First nmos pass transistor, the drain electrode of described first nmos pass transistor connects described 3rd node, and source electrode connects the output terminal of described negative circuit with the 5th node, and grid connects the input end of described negative circuit with the 4th node;
First electric capacity, described first capacitances in series is between described 5th node and the output terminal of described negative circuit;
Second nmos pass transistor, the drain electrode of described second nmos pass transistor connects described 3rd node, and source electrode connects the input end of described negative circuit, and grid connects described 5th node;
Second electric capacity, described second capacitances in series is between described 4th node and the input end of described negative circuit;
First PMOS transistor, the drain electrode of described first PMOS transistor connects described 4th node, and source electrode connects positive pump circuit output terminal with the 6th node, and grid connects described 5th node;
Second PMOS transistor, the drain electrode of described second PMOS transistor connects described 5th node, and source electrode connects described 6th node, and grid connects described 4th node;
3rd electric capacity, described 3rd capacitances in series in one end connect described 6th node, other end ground connection.
Optionally, the frequency of described first clock control signal is 20MHz-200MHz.
Optionally, described low pressure difference linear voltage regulator comprises:
Amplifier, described amplifier comprises first input end and the second input end, and the first input end of described amplifier connects described reference voltage;
3rd PMOS transistor, the source electrode of described 3rd PMOS transistor connects described 3rd node, grounded drain, and grid connects the output terminal of described amplifier;
First resistance, described first resistant series is between second input end and described 3rd node of described amplifier;
Second resistance, described second resistant series is between second input end and ground end of described amplifier.
Optionally, the size of described reference voltage is 1.2V-1.4V.
Optionally, described constant-current generating circuit comprises:
4th PMOS transistor, the source electrode of described 4th PMOS transistor connects described Section Point, and drain and gate connects described reference current;
Mirrored transistor string, described mirrored transistor string is connected with the grid of described Section Point, the 3rd node and described 4th PMOS transistor respectively.
Optionally, described mirrored transistor string comprises at least three PMOS transistor in parallel.
Optionally, the source electrode of at least three PMOS transistor in parallel all connects described Section Point, and grid all connects the grid of described 4th PMOS transistor, and drain electrode all connects described 3rd node.
Optionally, the size of described reference current is 10 μ A-20 μ A.
Accordingly, the present invention also provides a kind of control method of above-mentioned circuit structure, comprising:
There is provided described reference voltage to described low pressure difference linear voltage regulator, described 3rd node exports a constant voltage, and described constant voltage is supplied to described constant-current generating circuit and described positive pump circuit, and described positive pump circuit has the charging and discharging currents of a change;
There is provided described reference current to described constant-current generating circuit, described constant-current generating circuit produces a constant output current at the 3rd node, and described constant output current is greater than the maximal value of described charging and discharging currents;
The portion of electrical current that described constant output current is greater than described charging and discharging currents is residual current, and described residual current is absorbed by described low pressure difference linear voltage regulator, and power lead is supplied to the current constant of described Section Point.
Circuit structure provided by the invention and control method thereof, low pressure difference linear voltage regulator produces a constant voltage, constant-current generating circuit produces the large steady current of charging and discharging currents maximum in a positive pump circuit of ratio to positive pump circuit, the portion of electrical current being greater than positive pump circuit charging and discharging currents is absorbed by low pressure difference linear voltage regulator, make electric current, the voltage constant of the 3rd node, thus the electric current of Section Point that is connected with constant-current generating circuit of power lead and voltage constant, to avoid in positive pump circuit current ripples to the impact of the voltage of power lead.
Accompanying drawing explanation
Fig. 1 is the circuit diagram comprising positive pump circuit of the prior art;
Fig. 2 is the schematic diagram of circuit structure in the present invention;
Fig. 3 is the schematic diagram of circuit structure in one embodiment of the invention;
Fig. 4 is the process flow diagram of circuit structure control method in one embodiment of the invention.
Embodiment
Below in conjunction with schematic diagram, circuit structure of the present invention and control method thereof are described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
Core concept of the present invention is, first, voltage condition according to power lead is configured low pressure difference linear voltage regulator, make low pressure difference linear voltage regulator produce the voltage lower than power line voltage and be supplied to the output terminal of constant-current generating circuit as its constant output current, and as the supply voltage of positive pump circuit.The electric current of positive pump circuit periodically can change along with the charge status of the size of the supply voltage of positive pump circuit, loading condition and coupling capacitance own.Current conditions according to positive pump circuit is configured constant-current generating circuit again, make constant-current generating circuit produce a constant output current, this constant output current is greater than the maximum source current that positive pump circuit provides required under particular power source voltage and loading condition.The part electric current that constant output current is greater than positive pump circuit electric current is absorbed by low pressure difference linear voltage regulator, constant output current then remains unchanged substantially, the output voltage that low pressure difference linear voltage regulator provides also remains unchanged substantially, the electric current that power lead is supplied to Section Point also can remain unchanged substantially, and the interference of so positive pump circuit to power lead also just significantly reduces.
Hereafter composition graphs 2, the control method of Fig. 3 and Fig. 4 to circuit structure of the present invention and circuit structure are specifically described.
Shown in figure 2, circuit structure provided by the invention, comprise: power lead 30, constant-current generating circuit 50, low pressure difference linear voltage regulator 40, positive pump circuit 20, mimic channel 10 and decoupling capacitor C0, described mimic channel 10 is connected with described power lead 30 with first node N1; Described constant-current generating circuit 50 is connected with described power lead 30 with Section Point B, and the input end of described constant-current generating circuit 30 connects a reference current Iref; Described decoupling capacitor C0 one end is connected between described first node N1 and described Section Point N2, the other end ground connection of described decoupling capacitor C0; Described steady current generation current 50 is connected with described low pressure difference linear voltage regulator 40 and described positive pump circuit 20 respectively with the 3rd node N3, and the input end of described low pressure difference linear voltage regulator 40 connects a reference voltage Vref.
Continue with reference to shown in figure 2, described positive pump circuit 20 comprises:
Negative circuit 21, the input end of described negative circuit 21 connects the first clock control signal CLK, and output terminal connects second clock control signal CLKb, and the frequency of described first clock control signal CLK is 20-MHz 200MHz;
The drain electrode of the first nmos pass transistor MN1, described first nmos pass transistor MN1 connects described 3rd node, and source electrode connects the output terminal of described negative circuit 21 with the 5th node, and grid connects the input end of described negative circuit 21 with the 4th node;
First electric capacity C1, described first electric capacity C1 are series between described 5th node N5 and the output terminal of described negative circuit 21;
The drain electrode of the second nmos pass transistor MN2, described second nmos pass transistor MN2 connects described 3rd node N3, and source electrode connects the input end of described negative circuit 21, and grid connects described 5th node N5;
Second electric capacity C2, described second electric capacity C2 are series between described 4th node N4 and the input end of described negative circuit 21;
The drain electrode of the first PMOS transistor MP1, described first PMOS transistor MP1 connects described 4th node N4, and source electrode connects positive pump circuit output terminal VOUT with the 6th node N6, and grid connects described 5th node N5;
The drain electrode of the second PMOS transistor MP2, described second PMOS transistor MP2 connects described 5th node N5, and source electrode connects described 6th node N6, and grid connects described 4th node N4;
One end of 3rd electric capacity C3, described 3rd electric capacity C3 connects described 6th node N6, the other end ground connection of described 3rd electric capacity C3.
Shown in figure 3, described low pressure difference linear voltage regulator 40 comprises:
Amplifier 41, described amplifier 41 comprises first input end 411 and the second input end 412, and the first input end 411 of described amplifier 41 connects described reference voltage Vref;
The source electrode of the 3rd PMOS transistor MP3, described 3rd PMOS transistor MP3 connects described 3rd node N3, grounded drain, and grid connects the output terminal of described amplifier 41;
First resistance R1, described first resistance R1 are connected between the second input end 412 of described amplifier 41 and described 3rd node N3;
Second resistance R2, described second resistance R2 are connected to the second input end 412 and the ground end of described amplifier 41.
Continue with reference to shown in figure 3, described constant-current generating circuit 50 comprises:
4th PMOS transistor MP4, the source electrode of described 4th PMOS transistor MP4 connects described Section Point N2, and drain and gate connects described reference current Iref;
Mirrored transistor string 51, described mirrored transistor string 51 is connected with the grid of described Section Point N2, the 3rd node N3 and described 4th PMOS transistor MP4 respectively, described mirrored transistor string 51 comprises at least three PMOS transistor in parallel, the source electrode of the transistor of at least three PMOS in parallel all connects described Section Point N2, grid all connects the grid of described 4th PMOS transistor MP4, drain electrode all connects described 3rd node N3, PMOS transistor in parallel is controlled by the register of outside, thus controls the output current of constant-current generating circuit 50.
Accordingly, the present invention also provides a kind of control method of circuit structure, shown in figure 4, comprises the steps:
First, perform step S1, the voltage condition according to power lead 30 is configured low pressure difference linear voltage regulator 40, and select the reference voltage Vref that suitable, the size of described reference voltage Vref is 1.2V-1.4V, and reference voltage Vref is provided by external circuit.By the amplifier 41 of low pressure difference linear voltage regulator 40 inside and the negative feedback of the first resistance R1 and the second resistance R2, low pressure difference linear voltage regulator 40 produces the constant voltage Vcp lower than power lead 30 voltage, constant voltage Vcp=R1 × (R1+R2)/R2, constant voltage Vcp is supplied to the output terminal of constant-current generating circuit 50 as its constant output current, and as the supply voltage of positive pump circuit 20.
Secondly, perform step S2, when the supply voltage of positive pump circuit 20 is Vcp, the charging and discharging currents of positive pump circuit 20 is Icp, Icp can along with the loading condition of positive pump circuit 20 and self coupling the first electric capacity C1, the second electric capacity C2 charge status periodically change, the charging and discharging currents Icp maximal value making positive pump circuit 20 is Icp_max.
Again, perform step S3, when again constant-current generating circuit 50 being configured according to the current conditions of positive pump circuit 20, according to reference current Iref and the electric current I cp being supplied to positive pump circuit of input, constant-current generating circuit 50 is made to produce a constant output current Iconst through mirrored transistor string 51, the size of described reference current Iref is 10 μ A-20 μ A, and the size of constant output current Iconst is 1mA-2mA.In the present embodiment, constant output current Iconst is greater than the maximum charging and discharging currents Icp_max being supplied to positive pump circuit 20.The part electric current that constant output current Iconst is greater than charging and discharging currents Icp is residual current Ireg, residual current Ireg is absorbed by low pressure difference linear voltage regulator 40, wherein, first resistance R1, second resistance R2 can consume one part of current, the size of this part electric current is primarily of Vcp and the first resistance R1, the size of the second resistance R2 resistance value decides, one part of current then has inner commutator tube the 3rd PMOS transistor MP1 to absorb in addition, the electric current of the upper absorption of MP1 then can change along with the charging and discharging currents Icp being supplied to positive pump circuit 20 and change, therefore, the constant output current Iconst that constant-current generating circuit 50 provides remains unchanged substantially, the output voltage Vcp that low pressure difference linear voltage regulator 40 provides also remains unchanged substantially.Because Iconst remains unchanged substantially, the electric current I supply that power lead 30 is supplied to Section Point N2 also remains unchanged substantially, the interference of the generation of positive pump circuit 20 pairs of power leads 30 is also just significantly reduced, power lead 30 substantially not by the interference of positive pump circuit 20, low pressure difference linear voltage regulator 40 and constant-current generating circuit 50, thus also can not have influence on the performance of other analog module 10.
It should be noted that, the stable of the voltage at Section Point N2 place can be maintained by low pressure difference linear voltage regulator 40 and constant-current generating circuit 50 in the present invention, thus relative to positive pump circuit of the prior art, the size of the decoupling capacitor needed in positive pump circuit of the present invention is very little, even negligible, thus the area of whole circuit can be reduced, save cost.
In sum, in circuit structure provided by the invention and control method thereof, low pressure difference linear voltage regulator produces a constant voltage, constant-current generating circuit produces the large steady current of charging and discharging currents maximum in a positive pump circuit of ratio to positive pump circuit, the portion of electrical current being greater than positive pump circuit charging and discharging currents is absorbed by low pressure difference linear voltage regulator, make the electric current of the 3rd node, voltage constant, thus the electric current of Section Point that is connected with constant-current generating circuit of power lead and voltage constant, to avoid in positive pump circuit current ripples to the impact of the voltage of power lead.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a circuit structure, is characterized in that, comprise power lead, constant-current generating circuit, low pressure difference linear voltage regulator, positive pump circuit, mimic channel and decoupling capacitor, described mimic channel is connected with described power lead with first node; Described constant-current generating circuit is connected with described power lead with Section Point, and the input end of described constant-current generating circuit connects a reference current; One end of described decoupling capacitor is connected between described first node and described Section Point, other end ground connection; Described constant-current generating circuit is connected with described low pressure difference linear voltage regulator and described positive pump circuit respectively with the 3rd node, and the input end of described low pressure difference linear voltage regulator connects a reference voltage.
2. circuit structure as claimed in claim 1, it is characterized in that, described positive pump circuit comprises:
Negative circuit, the input end of described negative circuit connects the first clock control signal, and the output terminal of described negative circuit connects second clock control signal;
First nmos pass transistor, the drain electrode of described first nmos pass transistor connects described 3rd node, and source electrode connects the output terminal of described negative circuit with the 5th node, and grid connects the input end of described negative circuit with the 4th node;
First electric capacity, described first capacitances in series is between described 5th node and the output terminal of described negative circuit;
Second nmos pass transistor, the drain electrode of described second nmos pass transistor connects described 3rd node, and source electrode connects the input end of described negative circuit, and grid connects described 5th node;
Second electric capacity, described second capacitances in series is between described 4th node and the input end of described negative circuit;
First PMOS transistor, the drain electrode of described first PMOS transistor connects described 4th node, and source electrode connects positive pump circuit output terminal with the 6th node, and grid connects described 5th node;
Second PMOS transistor, the drain electrode of described second PMOS transistor connects described 5th node, and source electrode connects described 6th node, and grid connects described 4th node;
3rd electric capacity, described 3rd capacitances in series in one end connect described 6th node, other end ground connection.
3. circuit structure as claimed in claim 2, it is characterized in that, the frequency of described first clock control signal is 20MHz-200MHz.
4. circuit structure as claimed in claim 1, it is characterized in that, described low pressure difference linear voltage regulator comprises:
Amplifier, described amplifier comprises first input end and the second input end, and the first input end of described amplifier connects described reference voltage;
3rd PMOS transistor, the source electrode of described 3rd PMOS transistor connects described 3rd node, grounded drain, and grid connects the output terminal of described amplifier;
First resistance, described first resistant series is between second input end and described 3rd node of described amplifier;
Second resistance, described second resistant series is between second input end and ground end of described amplifier.
5. circuit structure as claimed in claim 4, it is characterized in that, the size of described reference voltage is 1.2V-1.4V.
6. circuit structure as claimed in claim 1, it is characterized in that, described constant-current generating circuit comprises:
4th PMOS transistor, the source electrode of described 4th PMOS transistor connects described Section Point, and drain and gate connects described reference current;
Mirrored transistor string, described mirrored transistor string is connected with the grid of described Section Point, the 3rd node and described 4th PMOS transistor respectively.
7. circuit structure as claimed in claim 5, is characterized in that, described mirrored transistor string comprises at least three PMOS transistor in parallel.
8. circuit structure as claimed in claim 5, is characterized in that, the source electrode of at least three PMOS transistor in parallel all connects described Section Point, and grid all connects the grid of described 4th PMOS transistor, and drain electrode all connects described 3rd node.
9. circuit structure as claimed in claim 5, it is characterized in that, the size of described reference current is 10 μ A-20 μ A.
10. as a control method for the circuit structure in claim 1-9 as described in any one, it is characterized in that, comprising:
There is provided described reference voltage to described low pressure difference linear voltage regulator, described 3rd node exports a constant voltage, and described constant voltage is supplied to described constant-current generating circuit and described positive pump circuit, and described positive pump circuit has the charging and discharging currents of a change;
There is provided described reference current to described constant-current generating circuit, described constant-current generating circuit produces a constant output current at the 3rd node, and described constant output current is greater than the maximal value of described charging and discharging currents;
The portion of electrical current that described constant output current is greater than described charging and discharging currents is residual current, and described residual current is absorbed by described low pressure difference linear voltage regulator, and power lead is supplied to the current constant of described Section Point.
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| CN201510231068.5A CN104914914B (en) | 2015-05-07 | 2015-05-07 | Circuit structure and its control method |
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| CN201510231068.5A CN104914914B (en) | 2015-05-07 | 2015-05-07 | Circuit structure and its control method |
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| CN104914914B CN104914914B (en) | 2017-03-29 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108293095A (en) * | 2015-11-04 | 2018-07-17 | 三星电子株式会社 | Imaging sensor includes the electronic equipment and its operating method of the imaging sensor |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6577514B2 (en) * | 2001-04-05 | 2003-06-10 | Saifun Semiconductors Ltd. | Charge pump with constant boosted output voltage |
| US20050093614A1 (en) * | 2003-10-30 | 2005-05-05 | Dong-Uk Lee | Multi stage voltage pump circuit |
| TW200836463A (en) * | 2007-02-16 | 2008-09-01 | Richtek Techohnology Corp | Charge pump regulator and method for producing regulated voltage |
| CN101674011A (en) * | 2008-12-16 | 2010-03-17 | 昆山锐芯微电子有限公司 | Charge pump |
| US20130148456A1 (en) * | 2011-12-12 | 2013-06-13 | Electronics And Telecommunications Research Institute | Voltage regulator with improved load regulation and voltage regulating method |
| US20140084896A1 (en) * | 2012-09-26 | 2014-03-27 | Nxp B.V. | Low power low dropout linear voltage regulator |
-
2015
- 2015-05-07 CN CN201510231068.5A patent/CN104914914B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6577514B2 (en) * | 2001-04-05 | 2003-06-10 | Saifun Semiconductors Ltd. | Charge pump with constant boosted output voltage |
| US20050093614A1 (en) * | 2003-10-30 | 2005-05-05 | Dong-Uk Lee | Multi stage voltage pump circuit |
| TW200836463A (en) * | 2007-02-16 | 2008-09-01 | Richtek Techohnology Corp | Charge pump regulator and method for producing regulated voltage |
| CN101674011A (en) * | 2008-12-16 | 2010-03-17 | 昆山锐芯微电子有限公司 | Charge pump |
| US20130148456A1 (en) * | 2011-12-12 | 2013-06-13 | Electronics And Telecommunications Research Institute | Voltage regulator with improved load regulation and voltage regulating method |
| US20140084896A1 (en) * | 2012-09-26 | 2014-03-27 | Nxp B.V. | Low power low dropout linear voltage regulator |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108293095A (en) * | 2015-11-04 | 2018-07-17 | 三星电子株式会社 | Imaging sensor includes the electronic equipment and its operating method of the imaging sensor |
| US10687007B2 (en) | 2015-11-04 | 2020-06-16 | Samsung Electronics Co., Ltd. | System and method for controlling power supplied to a module of an electronic device |
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| CN104914914B (en) | 2017-03-29 |
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