CN104932368A - 485 circuit to AB phase converting circuit - Google Patents
485 circuit to AB phase converting circuit Download PDFInfo
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- CN104932368A CN104932368A CN201510303998.7A CN201510303998A CN104932368A CN 104932368 A CN104932368 A CN 104932368A CN 201510303998 A CN201510303998 A CN 201510303998A CN 104932368 A CN104932368 A CN 104932368A
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- phase
- data
- chip circuit
- fpga chip
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
Abstract
The invention relates to a 485 circuit to AB phase converting circuit, and belongs to the technical field of data communication protocol conversion of robots. The 485 circuit to AB phase converting circuit aims to solve problems that an existing glaze spraying robot needs to acquire location information when disengagement teaching is carried out on a motor and a body of one or more shafts and that an existing mode for acquiring the above location information has the problems that the location information is lost after power failure and many types of controllers are not provided with an RS485 or BISS type of digital communication interface. According to the invention, data output ends of a first path AB phase, a second path AB phase, a third path AB phase and a fourth path AB phase of an FPGA chip circuit are connected with input ends of differential converters U1-U12 respectively, and four paths of 485 digital signal input/output ends of the FPGA chip circuit are connected with digital signal output/input ends of 485 transceivers U17-U20 respectively through digital photoelectric couplers U13-U16. The circuit provided by the invention can convert RS485 signals of an absolute value encoder into AB phase signals stably and acquire location information of each shaft accurately so as to meet requirements of the robot.
Description
Technical field
The invention belongs to the technical field of the data communication protocol conversion of robot.
Background technology
The process of China's intense industrialization has led the fast development of robot application technology, and industrial robot is promptly replacing essential labour power--the people in various production line.Because glaze spraying robot needs the motor of one of them axle or several axle and body to be carried out throwing off teaching to alleviate the acting force pulled in teaching in the process pulling teaching.Thus make to pull teaching work and become light and handy smoothness, the part that these and motor are thrown off just needs to obtain position by scrambler pulling in teaching process.The existing obtain manner of acquisition for this positional information mainly contains two kinds.First kind of way is for adopting incremental encoder, and this scrambler price inexpensively, but can lose positional information after power down, and can not meet glaze spraying robot needs small change point function at the beginning of powering on.The second adopts absolute value formula scrambler, the communication interface of this kind of scrambler is generally the Interface for digital communication of RS485 or BISS type, the encoder resolution of this type is high, the position of scrambler still can be preserved after power down, but there is eurypalynous controller perhaps there is no the interface of this type, this just to need by means of driver and motor to obtain the communication interface of respective type, can increase cost and the larger spacial influence that accounts for is attractive in appearance.
Summary of the invention
The object of this invention is to provide the circuit that a kind of 485 circuit turn AB phase, be need to obtain positional information when the motor of an axle or several axle and body carry out disengagement teaching to solve existing glaze spraying robot, but the mode of the above-mentioned positional information of existing acquisition can lose positional information and be permitted the problem that eurypalynous controller does not have the Interface for digital communication of RS485 or BISS type after there is power down.
Described object is realized by following scheme: described a kind of 485 circuit turn the circuit of AB phase, and it comprises differential converter U1 ~ U12, digital light electric coupler U13 ~ U16,485 transceiver U17 ~ U20,232 transceivers 1, EPCS configuring chip circuit 2, Jtag interface 3, FPGA chip circuit 4, SM-6P-PCB socket J1 ~ J4;
Three data output ends of the first via AB phase of FPGA chip circuit 4 are connected with the input end of differential converter U1 ~ U3 respectively, three data output ends of the second road AB phase of FPGA chip circuit 4 are connected with the input end of differential converter U4 ~ U6 respectively, three data output ends of the 3rd road AB phase of FPGA chip circuit 4 are connected with the input end of differential converter U7 ~ U9 respectively, three data output ends of the 4th road AB phase of FPGA chip circuit 4 are connected with the input end of differential converter U10 ~ U12 respectively, the output terminal of differential converter U1 ~ U3 is respectively the data output A1 end of first via AB phase, data export B1 end and data export Z1 end, the output terminal of differential converter U4 ~ U6 be respectively the second road AB phase data export A2 end, data export B2 end and data export Z2 end, the output terminal of differential converter U7 ~ U9 be respectively the 3rd road AB phase data export A3 end, data export B3 end and data export Z3 end, the output terminal of differential converter U10 ~ U12 be respectively the 4th road AB phase data export A4 end, data export B4 end and data export Z4 end, the first via 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U17 by digital light electric coupler U13, second tunnel 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U18 by digital light electric coupler U14,3rd tunnel 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U19 by digital light electric coupler U15,4th tunnel 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U20 by digital light electric coupler U16, the serial date transfer output terminal of FPGA chip circuit 4 is connected with the serial data I/O of EPCS configuring chip circuit 2,232 data-signal input/output bus ends of FPGA chip circuit 4 export input bus end with the data of 232 transceivers 1 and are connected, the Jtag test data I/O of FPGA chip circuit 4 is connected on Jtag interface 3, the 485 communication data I/Os of 485 transceiver U17 ~ U20 connect SM-6P-PCB socket J1 ~ J4 respectively, 485 transceiver U17 ~ U20 adopt insulating power supply independently-powered.
The present invention can be stable the RS485 signal of absolute value encoder is converted into AB phase signals and the positional information obtaining each axle accurately meets the requirement of robot.Solve the scrambler that incremental encoder cannot read initial position and RS485 interface type and cannot carry out with controller the problem that communicates.The mode of the power acquisition insulating power supply of the power supply of main circuit and 485 transceivers is powered by the present invention respectively, adopts light-coupled isolation to reduce the noise brought in robot rig-site utilization to the signal of four tunnel 485 transceivers.The joint of 485 transceivers adopts SM-6P-PCB servo connector.Strengthened the antijamming capability of 485 transceivers by above measure, make it speed of 2.5Mbps can carry out stable transmission by the long-distance cable of 8-10m.
Accompanying drawing explanation
Fig. 1 is integrated circuit structural representation of the present invention.
Embodiment
Embodiment one: shown in composition graphs 1, it comprises differential converter U1 ~ U12, digital light electric coupler U13 ~ U16,485 transceiver U17 ~ U20,232 transceivers 1, EPCS configuring chip circuit 2, Jtag interface 3, FPGA chip circuit 4, SM-6P-PCB socket J1 ~ J4;
Three data output ends of the first via AB phase of FPGA chip circuit 4 are connected with the input end of differential converter U1 ~ U3 respectively, three data output ends of the second road AB phase of FPGA chip circuit 4 are connected with the input end of differential converter U4 ~ U6 respectively, three data output ends of the 3rd road AB phase of FPGA chip circuit 4 are connected with the input end of differential converter U7 ~ U9 respectively, three data output ends of the 4th road AB phase of FPGA chip circuit 4 are connected with the input end of differential converter U10 ~ U12 respectively, the output terminal of differential converter U1 ~ U3 is respectively the data output A1 end of first via AB phase, data export B1 end and data export Z1 end, the output terminal of differential converter U4 ~ U6 be respectively the second road AB phase data export A2 end, data export B2 end and data export Z2 end, the output terminal of differential converter U7 ~ U9 be respectively the 3rd road AB phase data export A3 end, data export B3 end and data export Z3 end, the output terminal of differential converter U10 ~ U12 be respectively the 4th road AB phase data export A4 end, data export B4 end and data export Z4 end, the first via 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U17 by digital light electric coupler U13, second tunnel 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U18 by digital light electric coupler U14,3rd tunnel 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U19 by digital light electric coupler U15,4th tunnel 485 digital signal input/output terminal of FPGA chip circuit 4 is connected with the digital signal I/O of 485 transceiver U20 by digital light electric coupler U16, the serial date transfer output terminal of FPGA chip circuit 4 is connected with the serial data I/O of EPCS configuring chip circuit 2,232 data-signal input/output bus ends of FPGA chip circuit 4 export input bus end with the data of 232 transceivers 1 and are connected, the Jtag test data I/O of FPGA chip circuit 4 is connected on Jtag interface 3, the 485 communication data I/Os of 485 transceiver U17 ~ U20 connect SM-6P-PCB socket J1 ~ J4 respectively, 485 transceiver U17 ~ U20 adopt insulating power supply independently-powered.
Described differential converter U1 ~ U12 is combined by three HEF4104BT and forms; The model that digital light electric coupler U13 ~ U16 selects is the digital CMOS photoelectrical coupler of ACPL-064L/K64L low-power consumption 10MBd; The model that 485 transceiver U17 ~ U20 select is ADM485; The model that 232 transceivers 1 are selected is MAX3232CUE; The model that EPCS configuring chip circuit 2 is selected is EPCS16SI8N; The model that FPGA chip circuit 4 is selected is EP4CE6E144 programmable logic device (PLD).
Principle of work: it comprises four tunnel 485 circuit and turns AB phase difference channel and a road RS232 read/write circuit.Wherein to turn the course of work of AB phase difference channel as follows for each road 485 circuit: FPGA chip circuit 4 sends data read command by the method for timing inquiry to scrambler and connects the data whole cycle that scrambler sends is 52us, the long 1us of minimum read cycle that whole period ratio scrambler requires, the object done like this avoids occurring that data are omitted and read/write conflict ensureing real-time property while, FPGA chip circuit 4 first sends data read command and the direction controlling pin controlling 485 transceivers is set high 5.2us, direction controlling pin sets low when sending ED and the burr introduced in order to eliminate than the long 1.2us of data transmitting time by time that sets high of direction controlling pin immediately.Controlling pins at 485 transceivers sets high after state terminates, and is set low wait-receiving mode and sends the data of returning from scrambler.After encoder data being detected, start 485 transceivers programs, after data receiver completes, data are existed in the register of FPGA chip circuit 4.By unblock assignment obtain sample period T be about to start and at the end of two positional value L
1and L
2.Sample period T is determined by speed threshold instruction, is determined by the frequency and clock number arranging system clock, and the instruction of speed threshold is obtained by 232 transceiver 1 interfaces and pulls teaching with what adapt to different product, and pull teaching speed faster, T value is less; Have that three values are optional is respectively 10.4ms, 20.8ms, 41.6ms, its default value is 41.6ms), by comparing L
1and L
2size, to determine the direction of scrambler.By calculating L
1and L
2poor thoroughly deserves the distance of passing by T time and the umber of pulse N that will transform, and will determine the clock number N of sample period T
tthe length (i.e. recurrence interval) that division obtains AB phase pulse a is done with pulse number.Be left in the basket because Verilog cannot carry out the fractional part branch that therefore floating point arithmetic obtain, therefore the present invention is increased correction verification module (being realized by counter) and changes the length of last pulse of T in the sample period to eliminate due to N
tbe divided by with N and the error obtained.Correction verification module can ensure that in one-period T, the actual pulse number sent is completely the same with the accuracy increasing system with the umber of pulse N calculated.The phase differential (90 of AB phase
.) by the shot clock of 4 double frequency pulse a as d type flip flop, using the input of pulse signal a as d type flip flop, the output signal b obtained just and between signal a has 90
.phase differential.The assignment relation between signal a and b and output signal A and B is determined according to the direction of scrambler.If L
1be less than L
2, then A=a, B=b then show that scrambler is in rotating forward, if L
1be greater than L
2, then A=b, B=a then show that scrambler is in reversion.Then A and B signal is converted to two paths of differential signals through difference chip and gives PMAC.
The course of work of 232 Transceiver Data communicating circuit parts is as follows: the data in FPGA chip circuit 4 register are become respectively its message format of self-defining response message and comprise start frame, the number of axle, scrambler individual pen number, scrambler multi-turn number and end frame.The control message format that it receives is start frame, the number of axle, speed threshold and end frame.The response message of respective shaft with individual pen number and multi-turn number is sent according to the reading command of respective shaft in message after FPGA chip circuit 4 receives the control message that host computer sends, the size of sample period T is meanwhile changed according to the numerical value of speed threshold, data are sent completely this state of rear end, thus reach the object that can read each axle current location data and speed governing.
Claims (1)
1. 485 circuit turn a circuit for AB phase, it is characterized in that it comprises differential converter U1 ~ U12, digital light electric coupler U13 ~ U16,485 transceiver U17 ~ U20,232 transceivers (1), EPCS configuring chip circuit (2), Jtag interface (3), FPGA chip circuit (4), SM-6P-PCB socket J1 ~ J4;
Three data output ends of the first via AB phase of FPGA chip circuit (4) are connected with the input end of differential converter U1 ~ U3 respectively, three data output ends of the second road AB phase of FPGA chip circuit (4) are connected with the input end of differential converter U4 ~ U6 respectively, three data output ends of the 3rd road AB phase of FPGA chip circuit (4) are connected with the input end of differential converter U7 ~ U9 respectively, three data output ends of the 4th road AB phase of FPGA chip circuit (4) are connected with the input end of differential converter U10 ~ U12 respectively, the output terminal of differential converter U1 ~ U3 is respectively the data output A1 end of first via AB phase, data export B1 end and data export Z1 end, the output terminal of differential converter U4 ~ U6 be respectively the second road AB phase data export A2 end, data export B2 end and data export Z2 end, the output terminal of differential converter U7 ~ U9 be respectively the 3rd road AB phase data export A3 end, data export B3 end and data export Z3 end, the output terminal of differential converter U10 ~ U12 be respectively the 4th road AB phase data export A4 end, data export B4 end and data export Z4 end, the first via 485 digital signal input/output terminal of FPGA chip circuit (4) is connected with the digital signal I/O of 485 transceiver U17 by digital light electric coupler U13, second tunnel 485 digital signal input/output terminal of FPGA chip circuit (4) is connected with the digital signal I/O of 485 transceiver U18 by digital light electric coupler U14,3rd tunnel 485 digital signal input/output terminal of FPGA chip circuit (4) is connected with the digital signal I/O of 485 transceiver U19 by digital light electric coupler U15,4th tunnel 485 digital signal input/output terminal of FPGA chip circuit (4) is connected with the digital signal I/O of 485 transceiver U20 by digital light electric coupler U16, the serial date transfer output terminal of FPGA chip circuit (4) is connected with the serial data I/O of EPCS configuring chip circuit (2), 232 data-signal input/output bus ends of FPGA chip circuit (4) export input bus end with the data of 232 transceivers (1) and are connected, the Jtag test data I/O of FPGA chip circuit (4) is connected on Jtag interface (3), the 485 communication data I/Os of 485 transceiver U17 ~ U20 connect SM-6P-PCB socket J1 ~ J4 respectively, 485 transceiver U17 ~ U20 adopt insulating power supply independently-powered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510303998.7A CN104932368A (en) | 2015-06-05 | 2015-06-05 | 485 circuit to AB phase converting circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510303998.7A CN104932368A (en) | 2015-06-05 | 2015-06-05 | 485 circuit to AB phase converting circuit |
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| CN104932368A true CN104932368A (en) | 2015-09-23 |
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|---|---|---|---|
| CN201510303998.7A Pending CN104932368A (en) | 2015-06-05 | 2015-06-05 | 485 circuit to AB phase converting circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105933299A (en) * | 2016-04-12 | 2016-09-07 | 珠海格力智能装备有限公司 | Data sending method, device and system of robot system |
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Address after: Yellow Sea zone haping road centralized development zone in Harbin City, Heilongjiang province 150000 No. 25 1 floor East Applicant after: HARBIN BOQIANG ROBOT TECHNOLOGY CO., LTD. Address before: 150000 room 368, 1508 Changjiang Road, Nangang District, Harbin City, Heilongjiang Province Applicant before: HARBIN BOQIANG ROBOT TECHNOLOGY CO., LTD. |
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Application publication date: 20150923 |
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