CN104994687A - Design method for improving differential routing impedance mismatching - Google Patents
Design method for improving differential routing impedance mismatching Download PDFInfo
- Publication number
- CN104994687A CN104994687A CN201510366005.0A CN201510366005A CN104994687A CN 104994687 A CN104994687 A CN 104994687A CN 201510366005 A CN201510366005 A CN 201510366005A CN 104994687 A CN104994687 A CN 104994687A
- Authority
- CN
- China
- Prior art keywords
- impedance
- signal
- resistance value
- jitter
- carry out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
Abstract
The invention improves a design method for improving differential routing impedance mismatching, and relates to the technical field of signal integrity. The concrete implementation steps of the invention comprise: 1) carrying out actual measurement of impedance of an upper PCB, and judging whether the impedance exceeds an impedance tolerance or not; 2) carrying out signal eye pattern testing of the upper PCB, and judging whether a signal Jitter is too large or not; 3) connecting an adjustable resistor between differential lines in parallel; 4) carrying out the signal eye pattern testing again, and adjusting the resistance value till Jitter meets the signal requirements. The method can effectively improve the signal quality, and a board card after impedance can be used for production function testing as scheduled, thereby enabling a plan to be carried out smoothly.
Description
Technical field
The present invention relates to signal integrity technical field, particularly relate to a kind of method for designing improving difference cabling impedance mismatching.
Background technology
Along with the fast development of the Internet and the continuous aggravation of market competition, production life cycle and product quality are also faced with more and more harsher requirement.Will experience dozens of flow process from the research and development of products design phase to volume production shipment, along with the accumulation of design experiences and the increasingly mature of emulation technology, it is more and more stronger that the problem of design phase keeps away rule ability.In PCB processing procedure, because operation is various, the high not reason of automaticity, the human negligence of operator is but unavoidable, and, the appearance of problems is random, unpredictable, and this will affect the project plan greatly, bring uncertainty to project.
Such as: when certain SAS stores backboard product development, after the processing of its EVT stage pcb board, actual measurement impedance exceeds the requirement of Spec regulation 100ohm+/-10%, its testing SA S signal Topology and resistance value.Therefore, for guaranteeing product quality, need PCB plate mill again to process a collection of pcb board.Meanwhile, this batch of bad plate is extracted out 5 carry out the upper part of PCBA processing welding after, signal testing is carried out to it, analyzes this batch of bad plate and whether can also meet demand on signal quality.
For the exploitation of Server product, the various high speed signals on mainboard have the characteristic impedance value required separately, are 40ohm etc. if PCIE Gen3 impedance be 85ohm, SATA impedance is 100ohm, DDR4 impedance.Therefore, when PCB design, we will carry out the design of layout difference live width line-spacing by this resistance value, and meanwhile, PCB factory also carries out target management and control with this resistance value.But pcb board work flow more complicated, due to the careless omission of certain link technique, usually there will be a collection of pcb board impedance and exceeds standard.Like this, this batch of pcb board just needs again to process, thus can cause the delay of PCBA factory welding component and later product functional test, has a strong impact on project development plan.
Summary of the invention
In order to solve this problem, the present invention proposes a kind of method for designing improving difference cabling impedance mismatching, the resistance value exceeded standard can be made to meet within the scope of target impedance, to start product function test according to plan, avoid the delay of project process.
The present invention proposes a kind of method for designing improving difference cabling impedance mismatching.In the exploitation of Server product, the various high speed signals on mainboard have the characteristic impedance value (such as: PCIE Gen3 signal impedance is 85ohm, SATA signal impedance be 100ohm, DDR4 signal impedance be 40ohm etc.) required separately.When PCB design, need to carry out setting emulation by carrying out difference live width line-spacing by the layout cabling of this resistance value to high speed signal, and by emulation, layout cabling is adjusted, make these high speed signals control in given scope at the resistance value of PCB cabling, PCB factory also carries out target management and control with this resistance value.But pcb board work flow more complicated, once careless omission appears in the technique of certain link, usually can cause a collection of pcb board impedance to exceed standard.Like this, this batch of pcb board just needs again to process, thus causes the delay of PCBA factory welding component and later product functional test, has a strong impact on project development plan.For this reason, a kind of method for designing improving difference cabling impedance mismatching is proposed herein: between differential lines, also engage suitable resistance, its high impedance is reduced within desired value management and control scope.The method effectively can improve signal quality, and the board after impedance matching can carry out product function test as scheduled, and guarantee plan is carried out smoothly.
Concrete implementation step is as follows:
1), upper pcb board carries out impedance actual measurement, sees and whether exceeds impedance tolerance;
2), upper pcb board carries out signal eye diagram test, whether excessively observes its signal Jitter;
3), between differential lines, adjustable resistance is connect;
4), again carry out signal eye diagram test, adjusting resistance value is until Jitter shake meets semaphore request.
Utilize resistor coupled in parallel principle, namely differential lines connecting resistance and differential lines characteristic impedance are carried out and connect, and its equivalent signal propagation path impedance can be overall on the low side; Regulate and connecting resistance value, its high impedance is reduced within desired value management and control scope.
Carry out rework debugging, and then the SAS passage that Impedance measurement exceeds standard, make resistance value meet within target impedance management and control scope, meanwhile, again carry out the test of SAS eye pattern, observe the improvement situation of its signal Jitter.
The invention has the beneficial effects as follows
The resistance value exceeded standard can be made to meet within the scope of target impedance, improve distorted signals problem, to start product function test according to plan, avoid the delay of project process.
By the eye pattern contrast between the differential lines of impedance mismatching and before and after connecting resistance, can the principal element of distorted signals be caused whether to be impedance mismatching by quick position, and need not wait for that heavy fresh processed pcb board is verified, improve board debug efficiency.
Embodiment
More detailed elaboration is carried out to content of the present invention below:
Concrete implementation step is as follows:
1), upper pcb board carries out impedance actual measurement, sees and whether exceeds impedance tolerance;
2), upper pcb board carries out signal eye diagram test, whether excessively observes its signal Jitter;
3), between differential lines, adjustable resistance is connect;
4), again carry out signal eye diagram test, adjusting resistance value is until Jitter shake meets semaphore request.
For SAS signal, carry out signal eye diagram test.Find that SAS signal jitter shake is too large.Cause the lifting of signal error rate (BER), will the use of systemic-function be had influence on.That is: hard disk is likely caused again to fall dish.It causes the excessive basic reason of SAS eye pattern Jitter exactly: SAS differential signal line impedance mismatch exceeds standard, and causes signal to reflect on propagation path.Have influence on the quality of signal code shape below, namely produce ISI intersymbol interference.
For above-mentioned situation, when bug analyzes, according to resistance connection in series-parallel principle, adopt following scheme: between differential lines and connecting resistance, its high impedance is reduced within desired value management and control scope (100ohm ± 10%).
From above-mentioned SAS Topology, utilize resistor coupled in parallel principle, i.e. differential lines connect R resistance and differential lines characteristic impedance Z carries out and connects, its equivalent signal propagation path impedance can be overall on the low side.When selecting more suitable and after connecing R resistance value, the impedance of its differential path can be reduced within target impedance management and control scope.Therefore, according to theory hypothesis, carry out relevant rework debugging, and then the SAS passage that Impedance measurement exceeds standard, its resistance value meets within target impedance management and control scope.Meanwhile, again carry out the test of SAS eye pattern, observe its signal Jitter and improve significantly.
In sum, between the differential lines of impedance mismatching, also engage suitable resistance, its high impedance is reduced within desired value management and control scope effectively can improve signal quality, and the board after impedance matching can carry out product function test as scheduled, and guarantee plan is carried out smoothly.
Claims (3)
1. improve a method for designing for difference cabling impedance mismatching, it is characterized in that,
Concrete implementation step is as follows:
1), upper pcb board carries out impedance actual measurement, sees and whether exceeds impedance tolerance;
2), upper pcb board carries out signal eye diagram test, whether excessively observes its signal Jitter;
3), between differential lines, adjustable resistance is connect;
4), again carry out signal eye diagram test, adjusting resistance value is until Jitter shake meets semaphore request.
2. method according to claim 1, is characterized in that,
Utilize resistor coupled in parallel principle, namely differential lines connecting resistance and differential lines characteristic impedance are carried out and connect, and its equivalent signal propagation path impedance can be overall on the low side; Regulate and connecting resistance value, its high impedance is reduced within desired value management and control scope.
3. method according to claim 2, is characterized in that,
Carry out rework debugging, and then the SAS passage that Impedance measurement exceeds standard, make resistance value meet within target impedance management and control scope, meanwhile, again carry out the test of SAS eye pattern, observe the improvement situation of its signal Jitter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510366005.0A CN104994687A (en) | 2015-06-29 | 2015-06-29 | Design method for improving differential routing impedance mismatching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510366005.0A CN104994687A (en) | 2015-06-29 | 2015-06-29 | Design method for improving differential routing impedance mismatching |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104994687A true CN104994687A (en) | 2015-10-21 |
Family
ID=54306401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510366005.0A Pending CN104994687A (en) | 2015-06-29 | 2015-06-29 | Design method for improving differential routing impedance mismatching |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104994687A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105808491A (en) * | 2016-03-03 | 2016-07-27 | 北京小米移动软件有限公司 | Banded differential line, intelligent equipment and method for improving USB eye pattern of intelligent equipment |
| CN106021151A (en) * | 2016-05-09 | 2016-10-12 | 浪潮电子信息产业股份有限公司 | Signal enhancing board as well as signal enhancing method and system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6052012A (en) * | 1998-06-29 | 2000-04-18 | Cisco Technology, Inc. | Method and apparatus for clock uncertainly minimization |
| CN1625875A (en) * | 2002-02-01 | 2005-06-08 | 英特尔公司 | Termination pair for a differential line with matched impedance |
| CN101313635A (en) * | 2005-12-21 | 2008-11-26 | 英特尔公司 | Apparatus and method for impedance matching in a backplane signal channel |
-
2015
- 2015-06-29 CN CN201510366005.0A patent/CN104994687A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6052012A (en) * | 1998-06-29 | 2000-04-18 | Cisco Technology, Inc. | Method and apparatus for clock uncertainly minimization |
| CN1625875A (en) * | 2002-02-01 | 2005-06-08 | 英特尔公司 | Termination pair for a differential line with matched impedance |
| CN101313635A (en) * | 2005-12-21 | 2008-11-26 | 英特尔公司 | Apparatus and method for impedance matching in a backplane signal channel |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105808491A (en) * | 2016-03-03 | 2016-07-27 | 北京小米移动软件有限公司 | Banded differential line, intelligent equipment and method for improving USB eye pattern of intelligent equipment |
| CN106021151A (en) * | 2016-05-09 | 2016-10-12 | 浪潮电子信息产业股份有限公司 | Signal enhancing board as well as signal enhancing method and system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9614703B2 (en) | Circuits and methods providing high-speed data link with equalizer | |
| CN104994687A (en) | Design method for improving differential routing impedance mismatching | |
| KR101208164B1 (en) | Receiver for recovering and retiming electromagnetically coupled data | |
| CN106598639B (en) | Logic chip upgrading method and upgrading system | |
| US20150370748A1 (en) | Signal transmission circuit and printed circuit board | |
| US9830293B2 (en) | Information processing apparatus, storage system, and computer-readable non-transitory storage medium storing communication control program | |
| CN102420462B (en) | Process-level smart terminal equipment of smart substation | |
| CN103678208B (en) | Spacecraft synchronous data transmission method | |
| CN107273602A (en) | A kind of emulation mode of lifting PCIE eye pattern allowances | |
| CN108962329A (en) | Efuse controller, Efuse system and Efuse programming method | |
| US9638750B2 (en) | Frequency-domain high-speed bus signal integrity compliance model | |
| US9548734B1 (en) | Smart impedance matching for high-speed I/O | |
| CN103517307B (en) | A kind of remote debugging system based on TD-SCDMA | |
| US8069285B2 (en) | Methods and systems for improving communication throughput of storage links | |
| CN105302686A (en) | Memory target testing method | |
| TW201311064A (en) | Printed circuit board | |
| CN2891084Y (en) | High-speed signal transmission circuit | |
| US9484967B1 (en) | Method for duty cycle distortion detection through decision feedback equalizer taps | |
| Moon et al. | Test Fixture Skew Removal for VNA Measurement | |
| Liu et al. | USB3. 1 silicon and channel design optimization using artificial neural network modeling | |
| CN103744827A (en) | Serial data frame matching method for improving chip logical time sequence | |
| DE102022119908A1 (en) | METHOD OF COMPENSATING AN INSERT LOSS VARIATION AFTER TRAINING | |
| CN101853825B (en) | Multi-load topology framework | |
| CN106685414B (en) | Crystal oscillator frequency debugging system | |
| US9384104B2 (en) | Testing a processor assembly |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20151021 |