CN105068786A - Method for processing access request and node controller - Google Patents
Method for processing access request and node controller Download PDFInfo
- Publication number
- CN105068786A CN105068786A CN201510461295.7A CN201510461295A CN105068786A CN 105068786 A CN105068786 A CN 105068786A CN 201510461295 A CN201510461295 A CN 201510461295A CN 105068786 A CN105068786 A CN 105068786A
- Authority
- CN
- China
- Prior art keywords
- processor
- access request
- node
- node controller
- controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The present invention discloses a method for processing an access request and a node controller. The method comprises the following steps: a first node controller receives the access request from a first processor; the first node controller forwards the access request to a processor corresponding to the access request, and receives an access answer returned by the processor corresponding to the access request; and the first node controller sends the access answer to the first processor, receives consistency state information returned by the first processor, and records the consistency state information from the first processor. According to the method for processing the access request, the number of the node controller can be reduced, so that a memory space occupied by the node controller is reduced, an inter-node interconnection scale is reduced, an inter-node topology is simplified, and system performance is promoted and more significant effects are achieved for the processor which is very limited in number of interconnection ports and number of supportable processor ID in a domain.
Description
Technical field
The present invention relates to field of computer technology, be specifically related to a kind of method and the Node Controller that process access request.
Background technology
Along with developing rapidly of computer technology, large-scale CC-NUMA (CacheCoherentNon-UniformMemoryAccess, the non-uniform internal storage access of buffer consistency) systematic difference is increasingly extensive.CC-NUMA system comprises multiple node, each node is made up of processor and Node Controller, and wherein, Node Controller is used for expanding system scale and safeguards the consistance of global buffer, that is, need to safeguard the buffer consistency between each node logical territory and in node between each physical domain simultaneously.
In prior art, the buffer consistency territory in each node is made up of a processor and a Node Controller.Such as, if build a CC-NUMA system be made up of the processor of 2 processor ID in 64 only support region, corresponding L the cache lines of each processor, at least 64 Node Controllers must be used, RP (the RemoteProxy of each Node Controller, remote memory is acted on behalf of) and LP (LocalProxy, local internal memory agents) directory entry be respectively: 2bit+1bit=3bit, 2bit+63bit=65bit, the directory entry of Node Controller accounts for 63*L* (3bit+65bit) * 64=274176Lbit=(267.75L) Kb altogether.Therefore, prior art adds the expense of cross-domain process and inter-domain communication, cause the remarkable decline of accessing remote memory, and system scale is larger, and the decline of access remote memory is more obvious.
Summary of the invention
The invention provides a kind of method and the Node Controller that process access request, with the defect that the expense solving cross-domain process and inter-domain communication in prior art is larger.
The invention provides a kind of method processing access request, comprise the following steps:
First node controller receives the access request from first processor;
Described access request is transmitted to the processor corresponding with described access request by described first node controller, and the memory access that the reception processor corresponding with described access request returns is replied;
Described memory access response is sent to described first processor by described first node controller, receives the coherency state information that described first processor returns, and carries out record to the coherency state information from described first processor.
Alternatively, corresponding with described access request processor is the second processor in local node;
Described access request is transmitted to the processor corresponding with described access request by described first node controller, is specially:
LP in described first node controller forwards described access request to described second processor.
Alternatively, the LP in described first node controller, to after described second processor forwards described access request, also comprises:
LP in described first node controller receives the coherency state information that described second processor returns, and carries out record to the coherency state information from described second processor.
Alternatively, corresponding with described access request processor is the 3rd processor in distant-end node;
Described access request is transmitted to the processor corresponding with described access request by described first node controller, and the memory access that the reception processor corresponding with described access request returns is replied, and is specially:
RP in described first node controller forwards described access request by Section Point controller to described 3rd processor, and by the memory access response that described 3rd processor of described Section Point controller reception returns, described Section Point controller is the Node Controller in described distant-end node.
Alternatively, described first node controller also comprises after receiving the coherency state information that described first processor returns:
Coherency state information from described first processor is sent to described Section Point controller by described first node controller.
Alternatively, described first node controller also comprises before described access request is transmitted to the processor corresponding with described access request:
The processor that described first node controller is corresponding to described access request judges.
Alternatively, the processor that described first node controller is corresponding to access request judges, is specially:
The catalogue that the inquiry of described first node controller stores self, if find information corresponding to described access request in LP, then determines that processor that described access request is corresponding is the second processor in local node; If find the information that described access request is corresponding in RP, then determine that processor that described access request is corresponding is the 3rd processor in distant-end node.
Present invention also offers a kind of Node Controller, comprising:
First receiver module, for receiving the access request from first processor;
First transceiver module, is transmitted to the processor corresponding with described access request for the described access request received by described first receiver module, and the memory access that the reception processor corresponding with described access request returns is replied;
Second transceiver module, sends to described first processor for the described memory access response received by described first transceiver module, receives the coherency state information that described first processor returns;
First logging modle, carries out record for the coherency state information from described first processor received described second transceiver module.
Alternatively, corresponding with described access request processor is the second processor in local node.
Alternatively, described Node Controller, also comprises:
Second receiver module, for receiving the coherency state information that described second processor returns;
Described logging modle, also for carrying out record to the coherency state information from described second processor.
Alternatively, corresponding with described access request processor is the 3rd processor in distant-end node;
Described first transceiver module, specifically for forwarding described access request by the Node Controller in described distant-end node to described 3rd processor, and is replied by the memory access that described 3rd processor of Node Controller reception in described distant-end node returns.
Alternatively, described Node Controller, also comprises:
First sending module, the coherency state information from described first processor for being received by described second transceiver module sends to described Section Point controller.
Alternatively, described Node Controller, also comprises:
Judge module, the processor that the access request for receiving described first receiver module is corresponding judges.
Alternatively, described Node Controller, also comprises:
Memory module, for storage directory;
Described judge module, specifically for inquiring about the catalogue that described memory module stores, if find information corresponding to described access request in LP, then determines that processor that described access request is corresponding is the second processor in local node; If find the information that described access request is corresponding in RP, then determine that processor that described access request is corresponding is the 3rd processor in distant-end node.
The present invention can reduce the quantity of Node Controller, and then memory headroom shared by minimizing Node Controller, interconnect between reduction node scale, simplify topology between node, elevator system performance, for the processor that interconnect port number is very limited with the territory inner treater ID quantity that can support, effect is more remarkable.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of node system in the embodiment of the present invention;
Fig. 2 is the structural representation of a kind of node in the embodiment of the present invention;
Fig. 3 is the structural representation of the another kind of node in the embodiment of the present invention;
Fig. 4 is a kind of method flow diagram processing access request in the embodiment of the present invention;
Fig. 5 is the structural representation of the catalogue stored in the RP in the embodiment of the present invention;
Fig. 6 is the structural representation of the catalogue stored in the LP in the embodiment of the present invention;
Fig. 7 is the structural representation of a kind of Node Controller in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
It should be noted that, if do not conflicted, each feature in the embodiment of the present invention and embodiment can be combined with each other, all within protection scope of the present invention.In addition, although show logical order in flow charts, in some cases, can be different from the step shown or described by order execution herein.
Embodiments provide a kind of method processing access request, application and the system comprising multiple node, as shown in Figure 1, each node is a domain logic, comprise a Node Controller, multiple processor and with the buffer memory belonging to each processor, each processor and the buffer memory belonging to this processor form a physics subdomain, be isolated from each other, connected by Node Controller between different physics subdomain.Each Node Controller is with physical cache coherency domains in coupled processor composition node, and each Node Controller is in same level, and carries out cascade by interconnection network between territory.Processor can access other processors in local node by Node Controller, also can be accessed the processor in distant-end node by Node Controller.
Multi-node system in the present embodiment comprises first node and Section Point, first node comprises first node controller, first processor and the second processor, as shown in Figure 2, Section Point comprises Section Point controller, the 3rd processor and four-processor, as shown in Figure 3.First node controller receives the access request from first processor, and access request is transmitted to the processor corresponding with access request, and the memory access response that the reception processor corresponding with access request returns; Memory access response is sent to first processor by first node controller, receives the coherency state information that first processor returns, and carries out record to the coherency state information from first processor.The idiographic flow of first node controller process access request, as shown in Figure 4, comprises the following steps:
Step 101, first node controller receives the access request from first processor.
Particularly, access request, when performing accessing operation, if hit buffer memory in the physics subdomain not belonging to it, is then pointed to the first node controller being positioned at Same Physical buffer consistency territory with it by first processor.
Step 102, the processor that first node controller is corresponding to access request judges, if the second processor in local node, then performs step 103; If the 3rd processor in distant-end node, then perform step 106.
Particularly, the catalogue that first node controller self is stored by inquiry, the processor corresponding to access request judges.
In the present embodiment, first node controller, by RP and LP storage directory, if find information corresponding to access request in LP, then determines that processor that access request is corresponding is the second processor in local node; If find the information that access request is corresponding in RP, then determine that processor that access request is corresponding is the 3rd processor in distant-end node.
Wherein, the catalogue stored in RP is for recording the distribution situation of far-end address data (all physical domain containing in this node domain logic) processor in local node, its catalogue list as cache lines (cacheline) corresponding to other all processors except this node domain logic, this cache lines of directory entry record of its every a line holds copy information (sharelist), coherency state information (state) and write permission owner information (owner) at other all processors except this node domain logic, as shown in Figure 5.Wherein, copy information is for all processors in minute book node logical territory to the shared state of data in this cache lines, and its length is the number of all processors in this node domain logic; Coherency state information for recording the state of data in this cache lines, as M, E, S and I etc.; Write permission owner information is the processor of M/E state or the numbering of even higher level of node current cache row data in this node to write operation authority, and its length is log
2m, m are the length of copy information.
Such as, system has N number of processor, belong to P node Nodei (i=1 respectively, 2, .., P), each node is divided into again p physics subdomain Domj (j=1, 2, .., p), corresponding L the cache lines of each processor, N/P=Q processor is had in the domain logic of then each node, N/ (P*p)=Q/p=q processor P k (k=1 is had in each physics subdomain, 2, .., q), the length of the copy information in RP is (P-1) * Q=(N-Q) position, the length of write permission owner information is log2 (N-Q) position, memory headroom shared by each RP is ((N-Q) * L) * (2+ (N-Q)+log2 (N-Q)).
The catalogue stored in LP for the data of address in each physical domain of minute book node in the distribution situation of other physical domain processors of this node and other nodes, its catalogue list as cache lines corresponding to processors all in this node domain logic, the directory entry of its every a line have recorded this cache lines and holds copy information, coherency state information and write permission owner information at other physics subdomain processors of this node and all distant-end nodes, as shown in Figure 6.Wherein, copy information is for recording the processor of other physics subdomains in distant-end node and this node domain logic to the shared state of data in this cache lines; Coherency state information for recording the state of data in this cache lines, as M, E, S and I etc.; Write permission owner information is numbering current cache row data to the distant-end node of M/E state of write operation authority, the processor of another subdomain and even higher level of node, and its length is log
2m, m are the length of copy information.
Such as, system has N number of processor, belong to P node Nodei (i=1 respectively, 2, .., P), each node is divided into again p physics subdomain Domj (j=1, 2, .., p), corresponding L the cache lines of each processor, N/P=Q processor is had in the domain logic of then each node, N/ (P*p)=Q/p=q processor P k (k=1 is had in each physics subdomain, 2, .., q), the length of the copy information of LP is (p-1) * q+ (P-1)=(P+Q-q-1) position, the length of write permission owner information is log2 (P+Q-q-1) position, memory headroom shared by each LP is (Q*L) * (2+ (P+Q-q-1)+log2 (P+Q-q-1)) position.
It should be noted that, write permission owner information is preference, and for improving the search performance of M/E state in extensive memory system, that reduces M/E state searches the time.
Step 103, first node controller forwards access request to the second processor, receives memory access response and coherency state information that the second processor returns.
Particularly, LP in first node controller forwards access request to the second processor, after second processor receives the access request from the LP in first node controller, this access request is processed, return memory access response and coherency state information to the LP in first node controller.
Step 104, the memory access response from the second processor is sent to first processor by first node controller, and carries out record to the coherency state information from the second processor.
Particularly, the memory access response from the second processor is sent to first processor by the LP in first node controller, and the coherency state information from the second processor is recorded in the catalogue self stored.
Step 105, first node controller receives the coherency state information from first processor, and carries out record to the coherency state information from first processor.
Particularly, after first processor receives the memory access response from the second processor by the LP in first node controller, update consistency status information, and the LP coherency state information after renewal returned in first node controller, the coherency state information from first processor is recorded in the catalogue self stored by the LP in first node controller.
Step 106, first node controller forwards access request to Section Point controller.
Particularly, the RP in first node controller sends access request to the LP in Section Point controller.Wherein, the Node Controller in the distant-end node that belongs to for the processor corresponding with access request of Section Point controller.
Step 107, Section Point controller forwards access request to the 3rd processor, the memory access response that reception the 3rd processor returns and coherency state information.
Particularly, LP in Section Point controller forwards access request to the 3rd processor, after 3rd processor receives the access request from the LP in Section Point controller, this access request is processed, return memory access response and coherency state information to the LP in Section Point controller.
Step 108, the memory access response from the 3rd processor is sent to first node controller by Section Point controller, and carries out record to the coherency state information from the 3rd processor.
Particularly, the RP that the LP in Section Point controller will send to from the memory access response of the 3rd processor and coherency state information in first node controller, and the coherency state information from the 3rd processor is recorded in the catalogue self stored.
Step 109, memory access response from the 3rd processor is sent to first processor by first node controller, receive the coherency state information that first processor returns, and record is carried out to the coherency state information from first processor, the coherency state information from first processor is sent to Section Point controller.
Particularly, memory access response from the 3rd processor is sent to first processor by the RP in first node controller, first processor update consistency status information, and the RP coherency state information after renewal returned in first node controller, the catalogue that RP in first node controller stores according to the coherency state information updating self from first processor, and the coherency state information from first processor is sent to the LP in Section Point controller.
Step 110, Section Point controller carries out record to the coherency state information from first processor.
Particularly, the catalogue that the LP in Section Point controller stores according to the coherency state information updating self from first processor.
The embodiment of the present invention is by there is the node in multiple buffer consistency territory, in the logical cache coherency domains that Node Controller internal build one is unified, thus comprise the multiple physical cache coherency domains be made up of some processors and this Node Controller be isolated from each other completely, directly connect by Node Controller between different node or interconnection network connection between territory, single cache coherency domains between composition node, the quantity of Node Controller can be reduced, and then memory headroom shared by minimizing Node Controller, interconnect between reduction node scale, simplify topology between node, elevator system performance, for the processor that interconnect port number is very limited with the territory inner treater ID quantity that can support, effect is more remarkable.
Such as, if build a CC-NUMA system be made up of the processor of 2 processor ID in 64 only support region, corresponding L the cache lines of each processor, only need 32 Node Controllers, the directory entry of RP and LP of each Node Controller is respectively: 2bit+2bit=4bit, 2bit+31bit+1bit=34bit, the directory entry of Node Controller accounts for (2*L*4bit+62*L*34bit) * 32=67712Lbit=(66.125L) Kb altogether, compared with prior art, the quantity of Node Controller reduces half, memory headroom shared by the directory entry of Node Controller reduces 3/4ths.
Based on the method for above-mentioned process access request, the embodiment of the present invention additionally provides a kind of Node Controller, as shown in Figure 7, comprising:
First receiver module 710, for receiving the access request from first processor.
First transceiver module 720, is transmitted to the processor corresponding with access request for the access request received by the first receiver module 710, and the memory access response that the reception processor corresponding with access request returns.
Second transceiver module 730, sends to first processor for the memory access response received by the first transceiver module 720, receives the coherency state information that first processor returns.
First logging modle 740, carries out record for the coherency state information from first processor received the second transceiver module 730.
Wherein, the above-mentioned processor corresponding with access request can be the second processor in local node.
Correspondingly, above-mentioned Node Controller, also comprises:
Second receiver module 750, for receiving the coherency state information that the second processor returns.
Above-mentioned logging modle 740, also for carrying out record to the coherency state information from the second processor.
In addition, the above-mentioned processor corresponding with access request can also be the 3rd processor in distant-end node.
Correspondingly, above-mentioned first transceiver module 720, specifically for forwarding access request by the Node Controller in distant-end node to the 3rd processor, and is replied by the memory access that Node Controller reception the 3rd processor in distant-end node returns.
Further, above-mentioned Node Controller, also comprises:
First sending module 760, sends to Section Point controller for the coherency state information from first processor received by the second transceiver module 730.
Further, above-mentioned Node Controller, also comprises:
Judge module 770, the processor that the access request for receiving the first receiver module 710 is corresponding judges.
Further, above-mentioned Node Controller, also comprises:
Memory module 780, for storage directory.
Correspondingly, above-mentioned judge module 770, specifically for the catalogue that inquiry memory module 780 stores, if find information corresponding to access request in LP, then determines that processor that access request is corresponding is the second processor in local node; If find the information that access request is corresponding in RP, then determine that processor that access request is corresponding is the 3rd processor in distant-end node.
The embodiment of the present invention is by there is the node in multiple buffer consistency territory, in the logical cache coherency domains that Node Controller internal build one is unified, thus comprise the multiple physical cache coherency domains be made up of some processors and this Node Controller be isolated from each other completely, directly connect by Node Controller between different node or interconnection network connection between territory, single cache coherency domains between composition node, the quantity of Node Controller can be reduced, and then memory headroom shared by minimizing Node Controller, interconnect between reduction node scale, simplify topology between node, elevator system performance, for the processor that interconnect port number is very limited with the territory inner treater ID quantity that can support, effect is more remarkable.
In conjunction with the software module that the step in the method that embodiment disclosed herein describes can directly use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random access memory (RAM), internal memory, ROM (read-only memory) (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should described be as the criterion with the protection domain of claim.
Claims (14)
1. process a method for access request, it is characterized in that, comprise the following steps:
First node controller receives the access request from first processor;
Described access request is transmitted to the processor corresponding with described access request by described first node controller, and the memory access that the reception processor corresponding with described access request returns is replied;
Described memory access response is sent to described first processor by described first node controller, receives the coherency state information that described first processor returns, and carries out record to the coherency state information from described first processor.
2. the method for claim 1, is characterized in that, the processor corresponding with described access request is the second processor in local node;
Described access request is transmitted to the processor corresponding with described access request by described first node controller, is specially:
LP in described first node controller forwards described access request to described second processor.
3. method as claimed in claim 2, is characterized in that, the LP in described first node controller, to after described second processor forwards described access request, also comprises:
LP in described first node controller receives the coherency state information that described second processor returns, and carries out record to the coherency state information from described second processor.
4. the method for claim 1, is characterized in that, the processor corresponding with described access request is the 3rd processor in distant-end node;
Described access request is transmitted to the processor corresponding with described access request by described first node controller, and the memory access that the reception processor corresponding with described access request returns is replied, and is specially:
RP in described first node controller forwards described access request by Section Point controller to described 3rd processor, and by the memory access response that described 3rd processor of described Section Point controller reception returns, described Section Point controller is the Node Controller in described distant-end node.
5. method as claimed in claim 4, is characterized in that, described first node controller also comprises after receiving the coherency state information that described first processor returns:
Coherency state information from described first processor is sent to described Section Point controller by described first node controller.
6. the method for claim 1, is characterized in that, described first node controller also comprises before described access request is transmitted to the processor corresponding with described access request:
The processor that described first node controller is corresponding to described access request judges.
7. method as claimed in claim 6, it is characterized in that, the processor that described first node controller is corresponding to access request judges, is specially:
The catalogue that the inquiry of described first node controller stores self, if find information corresponding to described access request in LP, then determines that processor that described access request is corresponding is the second processor in local node; If find the information that described access request is corresponding in RP, then determine that processor that described access request is corresponding is the 3rd processor in distant-end node.
8. a Node Controller, is characterized in that, comprising:
First receiver module, for receiving the access request from first processor;
First transceiver module, is transmitted to the processor corresponding with described access request for the described access request received by described first receiver module, and the memory access that the reception processor corresponding with described access request returns is replied;
Second transceiver module, sends to described first processor for the described memory access response received by described first transceiver module, receives the coherency state information that described first processor returns;
First logging modle, carries out record for the coherency state information from described first processor received described second transceiver module.
9. Node Controller as claimed in claim 8, it is characterized in that, the processor corresponding with described access request is the second processor in local node.
10. Node Controller as claimed in claim 9, is characterized in that, also comprise:
Second receiver module, for receiving the coherency state information that described second processor returns;
Described logging modle, also for carrying out record to the coherency state information from described second processor.
11. Node Controllers as claimed in claim 8, is characterized in that, the processor corresponding with described access request is the 3rd processor in distant-end node;
Described first transceiver module, specifically for forwarding described access request by the Node Controller in described distant-end node to described 3rd processor, and is replied by the memory access that described 3rd processor of Node Controller reception in described distant-end node returns.
12. Node Controllers as claimed in claim 11, is characterized in that, also comprise:
First sending module, the coherency state information from described first processor for being received by described second transceiver module sends to described Section Point controller.
13. Node Controllers as claimed in claim 8, is characterized in that, also comprise:
Judge module, the processor that the access request for receiving described first receiver module is corresponding judges.
14. Node Controllers as claimed in claim 13, is characterized in that, also comprise:
Memory module, for storage directory;
Described judge module, specifically for inquiring about the catalogue that described memory module stores, if find information corresponding to described access request in LP, then determines that processor that described access request is corresponding is the second processor in local node; If find the information that described access request is corresponding in RP, then determine that processor that described access request is corresponding is the 3rd processor in distant-end node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510461295.7A CN105068786B (en) | 2015-07-30 | 2015-07-30 | A kind of method and Node Controller for handling access request |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510461295.7A CN105068786B (en) | 2015-07-30 | 2015-07-30 | A kind of method and Node Controller for handling access request |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105068786A true CN105068786A (en) | 2015-11-18 |
| CN105068786B CN105068786B (en) | 2018-03-23 |
Family
ID=54498167
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510461295.7A Active CN105068786B (en) | 2015-07-30 | 2015-07-30 | A kind of method and Node Controller for handling access request |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105068786B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114024714A (en) * | 2021-09-30 | 2022-02-08 | 山东云海国创云计算装备产业创新中心有限公司 | Access request processing method and device, network card equipment and storage computing system |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030009635A1 (en) * | 2001-06-21 | 2003-01-09 | International Business Machines Corporation | Non-uniform memory access (NUMA) computer system having distributed global coherency management |
| US6751698B1 (en) * | 1999-09-29 | 2004-06-15 | Silicon Graphics, Inc. | Multiprocessor node controller circuit and method |
| CN101183338A (en) * | 2006-09-29 | 2008-05-21 | 美国博通公司 | Local piece loading system and method for maintaining storage coherence in the same |
| CN101539888A (en) * | 2008-03-18 | 2009-09-23 | 富士通株式会社 | Information processing device, memory control method, and memory control device |
| CN103020004A (en) * | 2012-12-14 | 2013-04-03 | 杭州华为数字技术有限公司 | Access method and device for cache coherent-non uniform memory access system |
| CN103049422A (en) * | 2012-12-17 | 2013-04-17 | 浪潮电子信息产业股份有限公司 | Method for building multi-processor node system with multiple cache consistency domains |
| CN103294611A (en) * | 2013-03-22 | 2013-09-11 | 浪潮电子信息产业股份有限公司 | Server node data cache method based on limited data consistency state |
| CN103294612A (en) * | 2013-03-22 | 2013-09-11 | 浪潮电子信息产业股份有限公司 | Method for constructing Share-F state in local domain of multi-level cache consistency domain system |
| CN103430161A (en) * | 2012-11-15 | 2013-12-04 | 华为技术有限公司 | Method, device and system based on PCIE Switch communication |
| CN103440223A (en) * | 2013-08-29 | 2013-12-11 | 西安电子科技大学 | Layering system for achieving caching consistency protocol and method thereof |
-
2015
- 2015-07-30 CN CN201510461295.7A patent/CN105068786B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6751698B1 (en) * | 1999-09-29 | 2004-06-15 | Silicon Graphics, Inc. | Multiprocessor node controller circuit and method |
| US20030009635A1 (en) * | 2001-06-21 | 2003-01-09 | International Business Machines Corporation | Non-uniform memory access (NUMA) computer system having distributed global coherency management |
| CN101183338A (en) * | 2006-09-29 | 2008-05-21 | 美国博通公司 | Local piece loading system and method for maintaining storage coherence in the same |
| CN101539888A (en) * | 2008-03-18 | 2009-09-23 | 富士通株式会社 | Information processing device, memory control method, and memory control device |
| CN103430161A (en) * | 2012-11-15 | 2013-12-04 | 华为技术有限公司 | Method, device and system based on PCIE Switch communication |
| CN103020004A (en) * | 2012-12-14 | 2013-04-03 | 杭州华为数字技术有限公司 | Access method and device for cache coherent-non uniform memory access system |
| CN103049422A (en) * | 2012-12-17 | 2013-04-17 | 浪潮电子信息产业股份有限公司 | Method for building multi-processor node system with multiple cache consistency domains |
| CN103294611A (en) * | 2013-03-22 | 2013-09-11 | 浪潮电子信息产业股份有限公司 | Server node data cache method based on limited data consistency state |
| CN103294612A (en) * | 2013-03-22 | 2013-09-11 | 浪潮电子信息产业股份有限公司 | Method for constructing Share-F state in local domain of multi-level cache consistency domain system |
| CN103440223A (en) * | 2013-08-29 | 2013-12-11 | 西安电子科技大学 | Layering system for achieving caching consistency protocol and method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114024714A (en) * | 2021-09-30 | 2022-02-08 | 山东云海国创云计算装备产业创新中心有限公司 | Access request processing method and device, network card equipment and storage computing system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105068786B (en) | 2018-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9274961B2 (en) | Method for building multi-processor system with nodes having multiple cache coherency domains | |
| US20150058570A1 (en) | Method of constructing share-f state in local domain of multi-level cache coherency domain system | |
| JP4290730B2 (en) | Tree-based memory structure | |
| US7155525B2 (en) | Transaction management in systems having multiple multi-processor clusters | |
| US20040236912A1 (en) | Methods and apparatus for providing cache state information | |
| CN108363641B (en) | Main and standby machine data transmission method, control node and database system | |
| US20150189039A1 (en) | Memory Data Access Method and Apparatus, and System | |
| CN103294611B (en) | Server node data cache method based on limited data consistency state | |
| CN106331153A (en) | Service request filtering method, service request filtering device and service request filtering system | |
| US8930640B2 (en) | Multiprocessor computer system with reduced directory requirement | |
| US10592465B2 (en) | Node controller direct socket group memory access | |
| CN114625762A (en) | Metadata acquisition method, network equipment and system | |
| CN109697127A (en) | The method and apparatus that the access operation of a kind of pair of shared resource locks | |
| US7346744B1 (en) | Methods and apparatus for maintaining remote cluster state information | |
| US9208100B2 (en) | Directory replacement method and device | |
| US7249224B2 (en) | Methods and apparatus for providing early responses from a remote data cache | |
| US20050120134A1 (en) | Methods and structures for a caching to router in iSCSI storage systems | |
| US7337279B2 (en) | Methods and apparatus for sending targeted probes | |
| US7162589B2 (en) | Methods and apparatus for canceling a memory data fetch | |
| CN105068786A (en) | Method for processing access request and node controller | |
| WO2016131175A1 (en) | Method and device for accessing data visitor directory in multi-core system | |
| WO2021238594A1 (en) | Storage medium management method and apparatus, and device and computer-readable storage medium | |
| JP2018129041A (en) | Transfer of response to snoop request | |
| KR101419379B1 (en) | Method of reducing network load and structure of node for multi processor system with distributed memory | |
| US20230418707A1 (en) | Remote Access Array |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |