CN105097661A - Semiconductor device, preparation method thereof, and electronic device - Google Patents
Semiconductor device, preparation method thereof, and electronic device Download PDFInfo
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- CN105097661A CN105097661A CN201410218843.9A CN201410218843A CN105097661A CN 105097661 A CN105097661 A CN 105097661A CN 201410218843 A CN201410218843 A CN 201410218843A CN 105097661 A CN105097661 A CN 105097661A
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Abstract
The invention relates to a semiconductor device, a preparation method thereof and an electronic device. The method comprises the steps of providing a first substrate on which components and a metal interconnecting structure above the components are formed, wherein the metal interconnecting structure is embedded into a first dielectric layer, a second dielectric layer is formed on the first dielectric layer, through-hole openings are formed in a second dielectric layer, and the through-hole openings are exposed from the metal interconnecting structure; providing a second substrate in which conical silicon through-hole trenches are formed; aligning the conical silicon through-hole trenches with the through-hole openings and integrating the second substrate with the first substrate; and grinding the second substrate for exposing the conical silicon through-hole trenches. The preparation method of the invention is advantageous in that the through-hole openings and the silicon through-hole trenches are respectively formed, thereby preventing a problem of trench etching at an interface between the second substrate and the second dielectric layer.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of semiconductor device and preparation method thereof, electronic installation.
Background technology
At consumer electronics field, multifunctional equipment is more and more subject to liking of consumer, compared to the simple equipment of function, multifunctional equipment manufacturing process will be more complicated, such as need the chip of integrated multiple difference in functionality in circuit version, thus there is 3D integrated circuit (integratedcircuit, IC) technology, 3D integrated circuit (integratedcircuit, IC) a kind of system-level integrated morphology is defined as, multiple chip is stacking in vertical plane direction, thus saving space, multiple pin can be drawn as required in the marginal portion of each chip, utilize these pins as required, by interconnected by metal wire for the chip needing to be connected to each other, but still there is a lot of deficiency in aforesaid way, such as stacked chips quantity is more, and the annexation more complicated between chip, can need to utilize many metal line, final wire laying mode is more chaotic, and volume can be caused to increase.
Therefore, at present at described 3D integrated circuit (integratedcircuit, IC) silicon through hole (ThroughSiliconVia is mostly adopted in technology, TSV), silicon through hole is a kind of perpendicular interconnection penetrating Silicon Wafer or chip, the preparation method of TSV can hole (via) with etching or laser mode on Silicon Wafer, then with electric conducting material as the materials such as copper, polysilicon, tungsten fill up, thus it is interconnected to realize between different silicon chip.
In the semiconductor device owing to passing through silicon through hole (ThroughSiliconVia between different lamination, TSV) realize interconnected, make 3D integrated circuit development, and device size constantly reduces, but still there are some problems, such as, formed again in the process of described silicon through hole TSV after forming via openings in the dielectric layer and be difficult to described via openings and described TSV to aim at, there is larger error, in addition, due to reducing of size, to in described through hole and described TSV during filled conductive material, owing to having larger depth-to-width ratio, fill and there is very large difficulty.
Therefore, need to do further improvement, to eliminate the problems referred to above to the preparation method of silicon through hole in current described semiconductor device.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of preparation method of semiconductor device, comprising:
There is provided the first substrate, described first substrate is formed components and parts and is positioned at the metal interconnection structure above described components and parts, described metal interconnection structure is embedded in the first dielectric layer; Described first dielectric layer is formed with the second dielectric layer, in described second dielectric layer, is formed with via openings, described via openings exposes described metal interconnection structure;
Second substrate is provided, in described second substrate, is formed with conical silicon via trench;
The opening of described conical silicon via trench is aimed at described via openings, and described second substrate and described first substrate joint are integrated;
Grind described second substrate, to expose described conical silicon via trench.
Alternatively, described method also comprises further:
Filled conductive material in described conical silicon via trench and described via openings, to form through hole and silicon through hole.
Alternatively, before the described silicon through hole of formation, the sidewall that described method is also included in described conical silicon via trench is formed the step of barrier layer and backing layer.
Alternatively, described second substrate and described first substrate are engaged after being integrated, described conical silicon via trench is shape wide at the top and narrow at the bottom.
Alternatively, the acute angle formed between the sidewall of described conical silicon via trench and the horizontal surface of described second substrate is less than 85 °.
Alternatively, Bosch etch process is selected to etch described second substrate, to form up-narrow and down-wide conical silicon via trench in described second substrate.
Alternatively, described components and parts comprise inertial sensor.
Alternatively, described second dielectric layer comprises oxide skin(coating).
Present invention also offers the semiconductor device that a kind of above-mentioned method prepares.
Present invention also offers a kind of electronic installation, comprise above-mentioned semiconductor device.
The present invention is in order to solve the various problems existed in prior art, provide a kind of preparation method of semiconductor device, described method prepares the first substrate and the second substrate respectively, various device and via openings is formed in described first substrate, silicon via trench is formed in described second substrate, then described silicon via trench and described via openings are aimed at, described first substrate and the second substrate are engaged and is integrated.
The advantage of the method for the invention is:
(1) via openings and silicon via trench is formed respectively, to avoid the problem of carrying out trench etch in described second substrate and described second dielectric interface place.
(2) described method can obtain enough etch quantities excessively, to ensure the stability preparing device.
(3) available silicon through hole is wide at the top and narrow at the bottom after splicing for described method, there is larger opening, acute angle between sidewall and horizontal plane is 84.9 °, and polymer can be avoided in the gathering of described silicon via bottoms, electric conducting material can be made to have better filling effect simultaneously.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-1e is the preparation process generalized section of semiconductor device in prior art;
Fig. 2 is the SEM schematic diagram of TSV in semiconductor device in prior art;
Fig. 3 a-3d is the preparation process generalized section of semiconductor device in an embodiment of the present invention;
Fig. 4 is the SEM schematic diagram of TSV in an embodiment of the present invention;
Fig. 5 is preparation technology's flow chart of semiconductor device in an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain technical scheme of the present invention.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Embodiment 1
The preparation method of current semiconductor device is as shown in Fig. 1 a-1e, wherein, first Semiconductor substrate 101 is provided, as shown in Figure 1a, wherein, described Semiconductor substrate 101 is formed with various components and parts, such as, is formed with inertial sensor etc. on the semiconductor substrate, then on described inertial sensor, form layer metal interconnection structure 102; Then in the dielectric layer of described layer metal interconnection superstructure, form through hole 103, the critical size of wherein said through hole is 2um, as shown in Figure 1 b.
Integrated in order to what realize between different chip, need to form silicon through hole on described inertial sensor, can comprise the following steps particularly: first, described substrate 101 is formed the second substrate 104, to cover described inertial sensor, as illustrated in figure 1 c, then the second substrate 104 described in patterning, to form the opening 105 with high-aspect-ratio above described through hole 103, expose described through hole 103, as shown in Figure 1 d, because described second substrate 104 has larger thickness, such as 31um, described through hole 103 has less critical size simultaneously, therefore the aligning of described through hole 103 and described opening 105 is easy to offset in this step, cause alignment error, on the interface of described dielectric layer and the second substrate 104, fluting problem is there is in the etching process of described TSV.
Finally, filled conductive material in described through hole 103 and described opening 105, as shown in fig. le, to form the interconnection structure of TSV, in order to better filled conductive material, described opening 105 needs to form tapered profiles (taperprofile), but the angle between the sidewall of described opening and horizontal plane is difficult to reach less than 88 °, as shown in figure on the left of Fig. 2, in addition, have in the process of opening 105 of high-aspect-ratio described in being formed in etching, its side effect can assemble a large amount of polymer in the bottom of described opening 105, described polymer has very large thickness, to such an extent as to be difficult to be removed by wet etching, as shown in Fig. 2 right figure, adverse effect is brought to device preparation.
Therefore, described have in opening 105 etching process of high-aspect-ratio can not form tapered opening effectively wide at the top and narrow at the bottom, and also easily cause the gathering of polymer in this process, also may cause deviation in alignment etc. simultaneously, bring very large challenge to device preparation.
The present invention, in order to solve the problem, provides a kind of preparation method of semiconductor device, is described in detail described method below in conjunction with accompanying drawing 3a-3d.
First, perform step 201, the first substrate 201 is provided, described first substrate forms components and parts.
Particularly, as shown in Figure 3 a, wherein said first substrate 201 at least comprises Semiconductor substrate, and described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
Then in described Semiconductor substrate, trap is formed, such as form adjacent N trap and P trap respectively, and on described N trap and P trap, form grid and be positioned at the source-drain area of grid both sides, particularly, form P trap window over the substrate, in described P trap window, carry out ion implantation, then perform annealing steps and advance to form P trap, same method forms N trap, does not repeat them here.
Described P trap forms grid structure, as preferably, described grid structure comprises the grid curb wall be positioned on gate lateral wall, particularly, grid structure can comprise each material, each material is including but not limited to some metal, metal alloy, metal nitride and metal silicide, and laminate and its compound.
Alternatively, gate electrode also can comprise the polysilicon of doping and polysilicon-Ge alloy material (that is, having the doping content from every cubic centimetre of about 1e18 to about 1e22 foreign atom) and polycide (polycide) material (polysilicon/metal silicide laminated material of doping).
Similarly, any one formation previous materials of several methods can also be adopted.Limiting examples comprises self-aligned metal silicate method, process for chemical vapor deposition of materials with via and physical vapor deposition methods, such as, but not limited to: method of evaporating and sputtering method.Usually, grid structure comprises and has thickness from about 50 to the polycrystalline silicon material of the doping of about 2000 dusts.
Particularly, form gate dielectric (not shown) first on a semiconductor substrate, then on gate dielectric, form gate material layers.In one embodiment, gate material layers is made up of polycrystalline silicon material, and metal, metal nitride, metal silicide or similar compound generally also can be used as gate material layers.
The formation method of gate dielectric and gate material layers comprises chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD), the general similarity method such as such as sputter and physical vapour deposition (PVD) (PVD) also can be used.The thickness of gate material layers is good to be less than about 1200 dusts.
Can form polysilicon gate construction in an embodiment of the present invention, the formation method of polysilicon layer can select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming polysilicon layer comprise: reacting gas is silane (SiH
4), the range of flow of silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350mTorr, as 300mTorr; Also can comprise buffer gas in reacting gas, buffer gas can be helium (He) or nitrogen, and the range of flow of helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8slm, 10slm or 15slm.Deposition carries out patterning, to obtain grid after forming polysilicon layer.
Then on gate lateral wall, form grid curb wall (spacer); Grid curb wall is e-SiC side wall (e-SiCspacer), and grid curb wall can be SiO
2, in SiN, SiOCN a kind of or their combinations form.As an execution mode of the present embodiment, side wall is silica, silicon nitride forms jointly, concrete technology is: form the first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer on a semiconductor substrate, then adopts engraving method to form grid curb wall 103.The thickness of grid curb wall 103 is 2-30nm, is preferably 5-25nm.
It should be noted that, sidewall structure is optional and nonessential, its be mainly used in follow-up carry out etching or ion implantation time grill-protected electrode structure sidewall injury-free.
Then ion implantation technology is performed, to form regions and source/drain in the Semiconductor substrate around grid.And then carry out rapid thermal annealing process, utilize the high temperature of 900 to 1050 DEG C to activate the doping in regions and source/drain, and repair the lattice structure of semiconductor substrate surface impaired in each ion implantation technology simultaneously.In addition, also visible product demand and functionally to consider, separately forms lightly doped drain (LDD) respectively between regions and source/drain and each grid.In this embodiment, carry out N-type ion implantation to described source-drain area, the foreign ion mixed in injection technology is one in phosphorus, arsenic, antimony, bismuth or combination.
Above described N trap, form grid structure form described grid structure above P trap while, described execution mode is only exemplary, is not limited to described method.
In addition, described first substrate is also formed with inertial sensor, described first substrate such as, is formed with the cavity of inertial sensor, and is arranged in the moving mass block etc. of cavity.
Alternatively, described first substrate can also form inertial sensor bottom electrode further, the formation method of described bottom electrode can select the conventional method in this area not repeat them here.
Wherein, in described first substrate except forming inertial sensor and various active device, other passive devices etc. can also be formed, be not limited to above-mentioned example, no longer enumerate at this.
Perform step 202, after the described various components and parts of formation, above described components and parts, form metal interconnection structure 202.
Particularly, as shown in Figure 3 a, the method for described formation metal interconnection structure 202 can select the process of similar dual damascene, first depositing first dielectric layer, and described first dielectric layer can select oxide.
Alternatively, above described components and parts, form the metal interconnect structure that through hole and metal are arranged alternately, wherein, the number of described metal level and described through hole is not limited to a certain number range, can arrange according to actual needs.
Further, what be positioned at top in described metal interconnection structure 202 is metal layer at top.
Perform step 203, at described metal interconnection structure 203 disposed thereon second dielectric layer 203, and the second dielectric layer 203 described in patterning, to form via openings in described second dielectric layer 203, expose described metal interconnection structure.
Particularly, as shown in Figure 3 a, wherein, described second dielectric layer 203 can select oxide, such as can select the combination of SiON and SiN in this embodiment, its thickness not certificate is confined to a certain number range, alternatively, the thickness of described SiON is 1-2 thousand dust, and the thickness of described SiN is 5-7 thousand dust.
Described components and parts and metal interconnection structure 202 is covered after depositing described second dielectric layer 203, then the second dielectric layer 203 described in patterning, to form via openings in described second dielectric layer 203, particularly, described second dielectric layer 203 is formed the mask layer of patterning, such as photoresist layer, through-hole pattern is formed in described mask layer, then with described mask layer for the second dielectric layer 203 described in mask etch, with by described design transfer to described second dielectric layer, form via openings 204.
Alternatively, the critical size of described via openings 204 is 2-2.5um, such as 2.2um, but is not limited to this number range.
Wherein, described via openings 204 is positioned at the top of described metal interconnection structure 202, after formation via openings 204, can expose the metal layer at top in described metal interconnection structure 202, to form electrical connection in follow-up technique.
Perform step 204, the second substrate 205 is provided, in described second substrate 205, forms conical silicon via trench 206.
Particularly, as shown in Figure 3 b, described second substrate 205 can select the material that this area is commonly used, such as silicon, polysilicon etc. in this step.In this embodiment, silicon is selected in described second substrate 205.
Further, in described second substrate 205, first form up-narrow and down-wide conical silicon via trench 206, in engaging process, need described second substrate 205 of reversing, after therefore engaging, obtain conical silicon via trench 206 wide at the top and narrow at the bottom.
Further, because described second substrate 205 is preparation separately, be not deposited on described first substrate, therefore avoid the problem forming groove at described second dielectric layer 203 and described second substrate 205 interface etching.
The method of anisotropic etching is selected to form described conical silicon via trench 206 in this step, described silicon via trench 206 has larger depth-to-width ratio, and the critical size of its opening is greater than the critical size of described via openings 204, so that can filled conductive material better in follow-up technique.
Particularly, in this step, select Bosch etch process (Boschetchingprocess) to etch and form described conical silicon via trench 206.
Alternatively, in Bosch technique etching process, be divided into etching and passivation two steps, such as, first at disposed on sidewalls one deck passivating film, pass into C
4f
8gas, C
4f
8ionic state CF is resolved under plasmoid
2base and active F base, wherein CF
2base and Si surface reaction, form (CF
2) n macromolecule passivating film.
Then etch, pass into gas SF
6, dissociate to increase F ion, etch away passivating film, then carry out the etching of Si base material.In the step of etching, be attached to the partial sidewall polymer on previous adhesion layer, under the impact of non-perpendicular ion collision sidewall, depart from sidewall and again move, again adhere on darker sidewall.Like this, the thin polymer film on sidewall is constantly driven downward attachment, thus forms the anisotropic etching of a local.
Select in this application Bosch technology by passivation/etching hocket (TMDE) realize Si deep etching.
Alternatively, in order to control described conical silicon via trench 206, there is comparatively big uncork, etching to obtain enough crossing, closing pulse function in this process, control the time of etching period slightly larger than passivation step simultaneously.
By the etching of above-mentioned processing step, up-narrow and down-wide conical silicon via trench 206 can be obtained, and the angle formed between the sidewall of described conical silicon via trench 206 and the horizontal surface of the second substrate is less than 85 °, as shown in Figure 4, the angle formed between the sidewall of described conical silicon via trench 206 and the horizontal surface of the second substrate is 84.9 °, overcomes in prior art the restriction being difficult to reach 88 °.
Owing to engaging rear described conical silicon via trench 206 for shape wide at the top and narrow at the bottom, there is enough overetched amounts, thus form larger opening, therefore can ensure in etching process can not at the congregate polymer of described conical silicon via trench 206, simultaneously can also can filled conductive material better in follow-up technique.
Further, the degree of depth of described conical silicon via trench 206 is less than the thickness of described second substrate 205, and the bottom of described conical silicon via trench 206 is positioned at the middle and lower part of described second substrate 205, does not run through described second substrate 205.
Perform step 205, the opening of described conical silicon via trench 206 is aimed at described via openings 204, and described second substrate 205 and described first substrate 201 joint are integrated.
Particularly, as shown in Figure 3 c, in this step the second substrate 205 being formed with described conical silicon via trench 206 is reversed, with by opening down for described conical silicon via trench 206, and aim at described via openings 204.
Then described second substrate 205 and described first substrate 201 are engaged and be integrated, as shown in Figure 3 d, such as, the method of eutectic joint or thermal bonding can be selected described second substrate 205 and described first substrate 201 to be engaged be integrated, but be not limited to described method, other conventional methods of this area can also be selected, do not repeat them here.
After splicing, described conical silicon via trench 206 is shape wide at the top and narrow at the bottom, has comparatively big uncork and sidewall slope.
Perform step 206, grind described second substrate 205, to expose described conical silicon via trench 206.
Particularly, grind described second substrate 205 in this step to described conical silicon via trench 206, to expose described conical silicon via trench 206, form opening, for filled conductive material in subsequent steps.
First the method that described Ginding process can select this area conventional, such as, selecting Ginding process to remove the second substrate 205 of most of thickness, carrying out cmp, to form opening when exposing described conical silicon via trench 206 soon.
Perform step 207, filled conductive material in described conical silicon via trench 206 and described via openings 204, to form through hole and silicon through hole.
Particularly, filled conductive material in described conical silicon via trench 206 and described via openings 204, described electric conducting material is formed by the deposition technique of low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD) and ald (ALD) or other advanced person.
Alternatively, described electric conducting material is tungsten material.In addition, other electric conducting material can also be selected as replacement, such as cobalt (Co), molybdenum (Mo), titanium nitride (TiN) and the electric conducting material containing tungsten or its combination.
Further, before filling described electric conducting material, can also at the deposited on sidewalls dielectric layer of described conical silicon via trench 206, described dielectric layer comprises two-layer, is respectively barrier layer and backing layer, and then forms described silicon through hole.
So far, the introduction of correlation step prepared by the semiconductor device completing the embodiment of the present invention.After the above step, other correlation step can also be comprised, repeat no more herein.Further, in addition to the foregoing steps, the preparation method of the present embodiment can also comprise other steps among each step above-mentioned or between different steps, and these steps all can be realized by various technique of the prior art, repeat no more herein.
The present invention is in order to solve the various problems existed in prior art, provide a kind of preparation method of semiconductor device, described method prepares the first substrate and the second substrate respectively, various device and via openings is formed in described first substrate, silicon via trench is formed in described second substrate, then described silicon via trench and described via openings are aimed at, described first substrate and the second substrate are engaged and is integrated.
The advantage of the method for the invention is:
(1) via openings and silicon via trench is formed respectively, to avoid the problem of carrying out trench etch in described second substrate and described second dielectric interface place.
(2) described method can obtain enough etch quantities excessively, to ensure the stability preparing device.
(3) available silicon through hole is wide at the top and narrow at the bottom after splicing for described method, there is larger opening, acute angle between sidewall and horizontal plane is 84.9 °, and polymer can be avoided in the gathering of described silicon via bottoms, electric conducting material can be made to have better filling effect simultaneously.
Fig. 5 is preparation technology's flow chart of semiconductor device in an embodiment of the present invention, comprises the following steps particularly:
Step 201 provides the first substrate, and described first substrate is formed components and parts and is positioned at the metal interconnection structure above described components and parts, described metal interconnection structure is embedded in the first dielectric layer; Described first dielectric layer is formed with the second dielectric layer, in described second dielectric layer, is formed with via openings, described via openings exposes described metal interconnection structure;
Step 202 provides the second substrate, in described second substrate, be formed with conical silicon via trench;
The opening of described conical silicon via trench is aimed at described via openings by step 203, and described second substrate and described first substrate joint is integrated;
Step 204 grinds described second substrate, to expose described conical silicon via trench.
Embodiment 2
Present invention also offers a kind of semiconductor device, described semiconductor device selects the method described in embodiment 1 to prepare.The deposition of polymer is not had bottom through-silicon via structure described in the semiconductor device prepared by the method for the invention, and there is larger opening and in pyramidal structure wide at the top and narrow at the bottom due to described silicon through hole, the filling effect of electric conducting material is good, and the semiconductor device prepared has good performance and stability.
Embodiment 3
Present invention also offers a kind of electronic installation, comprise the semiconductor device described in embodiment 2.Wherein, semiconductor device is the semiconductor device described in embodiment 2, or the semiconductor device that the preparation method according to embodiment 1 obtains.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, also can be any intermediate products comprising described semiconductor device.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has better performance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a preparation method for semiconductor device, comprising:
There is provided the first substrate, described first substrate is formed components and parts and is positioned at the metal interconnection structure above described components and parts, described metal interconnection structure is embedded in the first dielectric layer; Described first dielectric layer is formed with the second dielectric layer, in described second dielectric layer, is formed with via openings, described via openings exposes described metal interconnection structure;
Second substrate is provided, in described second substrate, is formed with conical silicon via trench;
The opening of described conical silicon via trench is aimed at described via openings, and described second substrate and described first substrate joint are integrated;
Grind described second substrate, to expose described conical silicon via trench.
2. method according to claim 1, is characterized in that, described method also comprises further:
Filled conductive material in described conical silicon via trench and described via openings, to form through hole and silicon through hole.
3. method according to claim 2, is characterized in that, before the described silicon through hole of formation, the sidewall that described method is also included in described conical silicon via trench is formed the step of barrier layer and backing layer.
4. method according to claim 1, is characterized in that, described second substrate and described first substrate are engaged after being integrated, described conical silicon via trench is shape wide at the top and narrow at the bottom.
5. method according to claim 1, is characterized in that, the acute angle formed between the sidewall of described conical silicon via trench and the horizontal surface of described second substrate is less than 85 °.
6. method according to claim 1, is characterized in that, selects Bosch etch process to etch described second substrate, to form up-narrow and down-wide conical silicon via trench in described second substrate.
7. method according to claim 1, is characterized in that, described components and parts comprise inertial sensor.
8. method according to claim 1, is characterized in that, described second dielectric layer comprises oxide skin(coating).
9. the semiconductor device prepared based on the method one of claim 1 to 8 Suo Shu.
10. an electronic installation, comprises semiconductor device according to claim 9.
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| US20030157748A1 (en) * | 2002-02-20 | 2003-08-21 | Kim Sarah E. | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
| KR100919712B1 (en) * | 2007-06-27 | 2009-10-06 | 삼성전자주식회사 | Semiconductor Integrated Circuit Device and Fabrication Method Thereof |
| US20110175215A1 (en) * | 2010-01-19 | 2011-07-21 | International Business Machines Corporation | 3d chip stack having encapsulated chip-in-chip |
| CN102237389A (en) * | 2010-05-06 | 2011-11-09 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing the same |
| CN103579114A (en) * | 2012-07-31 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Integrated semiconductor device and wafer level method of fabricating the same |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030157748A1 (en) * | 2002-02-20 | 2003-08-21 | Kim Sarah E. | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
| KR100919712B1 (en) * | 2007-06-27 | 2009-10-06 | 삼성전자주식회사 | Semiconductor Integrated Circuit Device and Fabrication Method Thereof |
| US20110175215A1 (en) * | 2010-01-19 | 2011-07-21 | International Business Machines Corporation | 3d chip stack having encapsulated chip-in-chip |
| CN102237389A (en) * | 2010-05-06 | 2011-11-09 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing the same |
| CN103579114A (en) * | 2012-07-31 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Integrated semiconductor device and wafer level method of fabricating the same |
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