CN105112972A - Method for manufacturing electroplating seed layer - Google Patents
Method for manufacturing electroplating seed layer Download PDFInfo
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- CN105112972A CN105112972A CN201510535274.5A CN201510535274A CN105112972A CN 105112972 A CN105112972 A CN 105112972A CN 201510535274 A CN201510535274 A CN 201510535274A CN 105112972 A CN105112972 A CN 105112972A
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- seed layer
- hole
- plating seed
- contact hole
- metal
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Abstract
The invention provides a method for manufacturing an electroplating seed layer. The function of the electroplating seed layer lies in that a good conducting layer is provided for the subsequent metal electroplating technology. The manufacturing method is used for a semiconductor device. At least one contact hole is formed in the surface of the semiconductor device, and the hole bottoms of the contact holes are made of metal. The manufacturing method includes the steps that the electroplating seed layer is deposited on the surface of the semiconductor device through the chemical metal coating technology, and covers the surface of the semiconductor device and the hole walls and the hole bottoms of the contact holes; the deposition thickness of the positions, located on the hole bottoms of the contact holes, of the electroplating seed layer is increased through the metal vacuum evaporation process, so that the electroplating seed layer completely covers the hole bottoms of the contact holes. In this way, the phenomenon that the hole bottoms of the contact holes of the electroplating seed layer are disconnected can be prevented.
Description
Technical field
The present invention relates to semiconductor surface field of electroplating, particularly relate to a kind of making method of plating seed layer.
Background technology
In semiconductor fabrication process, it is simple that metal electroplating process has technique, and cost is low, and sedimentation velocity is fast, the good characteristics such as good uniformity.But, existing chemical plating metal technology is when having the semiconducter device deposition plating seed layer of contact hole to the back side, plating seed layer is good in the hole wall deposition of the surface of semiconducter device and contact hole, cover evenly, but it is poor at the hole bottom sediments of contact hole, cause the poor continuity of plating seed layer, easily there is disconnection phenomenon in plating seed layer, this directly can affect follow-up metal electroplating process, cause the electric conductivity of contact hole not good, and then affect the performance of semiconducter device, yield rate and reliability.
Summary of the invention
The technical problem that the present invention mainly solves is to provide a kind of making method of plating seed layer, can prevent plating seed layer from the bottom of the hole of contact hole, occurring disconnection phenomenon.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: provide a kind of making method of electroplating plating seed layer, described making method is used for semiconducter device, the surface of described semiconducter device has at least one contact hole, it is metal at the bottom of the hole of described contact hole, described making method comprises: adopt chemical plating metal technique at the surface deposition plating seed layer of described semiconducter device, and described plating seed layer covers at the bottom of the surface of described semiconducter device and the hole wall of described contact hole and hole; Adopt vacuum evaporation smithcraft to increase the deposit thickness of described plating seed layer at the bottom of the hole of described contact hole, cover completely at the bottom of the hole of described contact hole to make described plating seed layer.
Preferably, the metal that described chemical plating metal technique adopts is palladium or nickel.
Preferably, the semiconductor material of described semiconducter device is silicon, gallium arsenide, gan or indium phosphide.
Preferably, described contact hole is positioned at the back side of described semiconducter device, is the source metal of described semiconducter device at the bottom of the hole of described contact hole.
Preferably, the metal that described vacuum evaporation smithcraft adopts is titanium or gold.
Preferably, when adopting titanium, described deposit thickness is 20-100nm; When adopting gold, described deposit thickness is 50-200nm.
Preferably, described vacuum evaporation smithcraft makes deposited by electron beam evaporation.
Be different from the situation of prior art, the invention has the beneficial effects as follows: by increasing the deposit thickness of plating seed layer at the bottom of the hole of contact hole in conjunction with vacuum evaporation smithcraft on the basis of chemical plating metal technique, thus can prevent plating seed layer from the bottom of the hole of contact hole, occurring disconnection phenomenon, continuity and the homogeneity of plating seed layer can be guaranteed, thus guarantee continuity and the homogeneity of subsequent metal electroplating technology, ensure the electric conductivity of contact hole, improve the performance of semiconducter device, yield rate and reliability.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of semiconducter device after the making method employing chemical plating metal technique of embodiment of the present invention plating seed layer.
Fig. 2 is the schematic diagram of semiconducter device after the making method employing vacuum evaporation smithcraft of embodiment of the present invention plating seed layer.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Incorporated by reference to see Fig. 1 and Fig. 2, the embodiment of the present invention provides a kind of making method of plating seed layer, in the present embodiment, making method is used for semiconducter device 1, the surface of semiconducter device 1 has at least one contact hole 2, and be metal at the bottom of the hole of contact hole 2, this making method comprises:
S1: adopt chemical plating metal technique at the surface deposition plating seed layer 3 of semiconducter device 1, plating seed layer 3 covers at the bottom of the surface of semiconducter device 1 and the hole wall of contact hole 2 and hole.
Wherein, chemical plating metal technique is a kind of when no current passes through, under the effect of metal ion reductive agent in same solution, by controllable redox reaction, be reduced into atoms metal at the semiconductor surface with catalytic surface, thus obtain the process of film metal.The plating seed layer 3 formed by chemical plating metal technique has lot of advantages, such as quick and good to the hole wall deposition on the surface of semiconducter device 1 and contact hole 2, but because the metallochemistry current potential at the bottom of the hole of contact hole 2 is higher, the surface deposition of plating seed layer 3 at the bottom of the hole of contact hole 2 is poor, so continuity is also poor.As can be seen from Figure 1, plating seed layer 3 is comparatively large at the deposit thickness of the hole wall of the surface of semiconducter device 1 and contact hole 2, and deposit thickness at the bottom of the hole of contact hole 2 is very little, hardly continuously.
In the present embodiment, the metal that chemical plating metal technique adopts is palladium or nickel.The semiconductor material of semiconducter device 1 is silicon, gallium arsenide, gan or indium phosphide.Contact hole 2 is positioned at the back side of semiconducter device 1, is the source metal of semiconducter device 1 at the bottom of the hole of contact hole 2, and the effect of plating seed layer 3 is for follow-up metal electroplating process provides good conductive layer.
S2: adopt vacuum evaporation smithcraft to increase the deposit thickness of plating seed layer 3 at the bottom of the hole of contact hole 2, cover completely at the bottom of the hole of contact hole 2 to make plating seed layer 3.
Wherein, the evaporation beam direction of vacuum evaporation smithcraft is better, and not by the impact of the semiconductor material of semiconducter device 1, chemical plating metal technique is much better than in the hole substrate covering power of contact hole 2, thus the deposit thickness of plating seed layer 3 at the bottom of the hole of contact hole 2 can be increased, plating seed layer 3 is covered at the bottom of the hole of contact hole 2 completely.
In the present embodiment, the metal that vacuum evaporation smithcraft adopts is titanium or gold, and when adopting titanium, deposit thickness is 20-100nm; When adopting gold, deposit thickness is 50-200nm.Vacuum evaporation smithcraft makes deposited by electron beam evaporation, the particle good directionality of electron beam evaporation, can provide stronger metal covering power at the bottom of the hole of contact hole 2.Certainly, vacuum evaporation smithcraft also can adopt other type of heating.
By the way, the making method of the plating seed layer of the embodiment of the present invention by increasing the deposit thickness of plating seed layer at the bottom of the hole of contact hole in conjunction with vacuum evaporation smithcraft on the basis of chemical plating metal technique, thus can prevent plating seed layer from the bottom of the hole of contact hole, occurring disconnection phenomenon, continuity and the homogeneity of plating seed layer can be guaranteed, thus guarantee continuity and the homogeneity of subsequent metal electroplating technology, ensure the electric conductivity of contact hole, improve the performance of semiconducter device, yield rate and reliability.
The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every utilize specification sheets of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (7)
1. a making method for plating seed layer, is characterized in that, described making method is used for semiconducter device, and the surface of described semiconducter device has at least one contact hole, and be metal at the bottom of the hole of described contact hole, described making method comprises:
Adopt chemical plating metal technique at the surface deposition plating seed layer of described semiconducter device, described plating seed layer covers at the bottom of the surface of described semiconducter device and the hole wall of described contact hole and hole;
Adopt vacuum evaporation smithcraft to increase the deposit thickness of described plating seed layer at the bottom of the hole of described contact hole, cover completely at the bottom of the hole of described contact hole to make described plating seed layer.
2. the making method of plating seed layer according to claim 1, is characterized in that, the metal that described chemical plating metal technique adopts is palladium or nickel.
3. the making method of plating seed layer according to claim 1, is characterized in that, the semiconductor material of described semiconducter device is silicon, gallium arsenide, gan or indium phosphide.
4. the making method of plating seed layer according to claim 1, is characterized in that, described contact hole is positioned at the back side of described semiconducter device, is the source metal of described semiconducter device at the bottom of the hole of described contact hole.
5. the making method of plating seed layer according to claim 1, is characterized in that, the metal that described vacuum evaporation smithcraft adopts is titanium or gold.
6. the making method of plating seed layer according to claim 5, is characterized in that, when adopting titanium, described deposit thickness is 20-100nm; When adopting gold, described deposit thickness is 50-200nm.
7. the making method of plating seed layer according to claim 5, is characterized in that, described vacuum evaporation smithcraft makes deposited by electron beam evaporation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510535274.5A CN105112972A (en) | 2015-08-27 | 2015-08-27 | Method for manufacturing electroplating seed layer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510535274.5A CN105112972A (en) | 2015-08-27 | 2015-08-27 | Method for manufacturing electroplating seed layer |
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| CN105112972A true CN105112972A (en) | 2015-12-02 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6139700A (en) * | 1997-10-01 | 2000-10-31 | Samsung Electronics Co., Ltd. | Method of and apparatus for forming a metal interconnection in the contact hole of a semiconductor device |
| CN102087994A (en) * | 2009-12-04 | 2011-06-08 | 无锡华润上华半导体有限公司 | Contact hole filling method |
| CN102915957A (en) * | 2012-09-17 | 2013-02-06 | 北京大学 | Method for making air bridge and inductance |
| CN103187364A (en) * | 2011-12-31 | 2013-07-03 | 中国科学院上海微系统与信息技术研究所 | Method for preparing seed layer in deep hole with high depth-to-width ratio |
| CN103346122A (en) * | 2013-07-22 | 2013-10-09 | 华进半导体封装先导技术研发中心有限公司 | High depth-to-width ratio TSV seed layer manufacturing method |
-
2015
- 2015-08-27 CN CN201510535274.5A patent/CN105112972A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6139700A (en) * | 1997-10-01 | 2000-10-31 | Samsung Electronics Co., Ltd. | Method of and apparatus for forming a metal interconnection in the contact hole of a semiconductor device |
| CN102087994A (en) * | 2009-12-04 | 2011-06-08 | 无锡华润上华半导体有限公司 | Contact hole filling method |
| CN103187364A (en) * | 2011-12-31 | 2013-07-03 | 中国科学院上海微系统与信息技术研究所 | Method for preparing seed layer in deep hole with high depth-to-width ratio |
| CN102915957A (en) * | 2012-09-17 | 2013-02-06 | 北京大学 | Method for making air bridge and inductance |
| CN103346122A (en) * | 2013-07-22 | 2013-10-09 | 华进半导体封装先导技术研发中心有限公司 | High depth-to-width ratio TSV seed layer manufacturing method |
Non-Patent Citations (1)
| Title |
|---|
| 张珠文 等: ""化学镀金在GaN基发光二极管电极制备上的应用"", 《光学与光电技术》 * |
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Address after: 610000 Sichuan, Shuangliu County, Southwest Airport Economic Development Zone, the Internet of things industry park Applicant after: CHENGDU HIWAFER TECHNOLOGY CO., LTD. Address before: 610000 Sichuan, Shuangliu County, Southwest Airport Economic Development Zone, the Internet of things industry park Applicant before: CHENGDU GASTONE TECHNOLOGY CO., LTD. |
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Application publication date: 20151202 |