CN105244367A - Substrate structure and manufacturing method thereof - Google Patents
Substrate structure and manufacturing method thereof Download PDFInfo
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- CN105244367A CN105244367A CN201410287674.4A CN201410287674A CN105244367A CN 105244367 A CN105244367 A CN 105244367A CN 201410287674 A CN201410287674 A CN 201410287674A CN 105244367 A CN105244367 A CN 105244367A
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- electric conducting
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- substrat structure
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Abstract
The invention relates to a substrate structure which comprises an insulating substrate, wherein the insulating substrate is provided with a first surface and a second surface which is opposite to the first surface; the insulating substrate comprises a first trench which is formed from the first surface to the internal part of the insulating substrate, and the first trench is composed of first side walls and a first bottom part. The substrate structure further comprises a first conductive material, wherein at least part of the first conductive material is located in the first trench, the first conductive material is provided with a first surface, and the first surface is not contacted with the first bottom part and the first side walls.
Description
Technical field
The present invention relates to a kind of substrat structure and manufacture method thereof.
Background technology
Flourish along with semiconductor technology, the functional density (number of the interconnection device in per unit chip area) of integrated circuit (IntegratedCircuit, IC) constantly increases.In addition, under the requirement of the volume or size microminiaturization that face integrated circuit, how to be integrated on semiconductor device by high-performance passive element (as inductor) is a major challenge that current semiconductor industry faces.Particularly compared to active device, the volume of passive component is comparatively large, and therefore passive component is integrated in semiconductor device by relative difficult.
Therefore, need a kind of semiconductor device and manufacture method thereof, under the condition not increasing volume, high performance passive component can be integrated in semiconductor device.
Summary of the invention
Embodiments of the invention are about a kind of substrat structure, comprise: dielectric substrate, described dielectric substrate has first surface and the second surface relative with described first surface, described dielectric substrate has the first groove formed from first surface to second surface, and described first groove is formed by bottom the first side wall and first; And first electric conducting material, described first electric conducting material is positioned at the first groove at least partly, and wherein said first electric conducting material has first surface, bottom described first surface does not contact first and the first side wall.
Another embodiment of the present invention relates to a kind of manufacture method of substrat structure, comprising: provide dielectric substrate, and described dielectric substrate has first surface and the second surface relative with described first surface; From first surface to second surface, form the first groove on the first surface, described first groove is formed by bottom the first side wall and first; And the first electric conducting material is inserted in the first groove, make described first electric conducting material at least partly be positioned at the first groove, wherein the first electric conducting material has first surface, bottom described first surface does not contact first and the first side wall.
Accompanying drawing explanation
Figure 1A is the schematic top plan view of substrat structure according to an embodiment of the invention.
Figure 1B is the generalized section of the A-A' line segment of substrat structure along Figure 1A.
Fig. 2 A-2F is the schematic diagram of the manufacture method of substrat structure according to another embodiment of the present invention.
Fig. 3 is the thickness of inductor and the graph of a relation of quality factor according to an embodiment of the invention.
Fig. 4 is the schematic diagram of substrat structure according to another embodiment of the present invention.
Fig. 5 is the schematic diagram of substrat structure according to another embodiment of the present invention.
Fig. 6 is the schematic diagram of substrat structure according to another embodiment of the present invention.
Fig. 7 is the schematic diagram of substrat structure according to another embodiment of the present invention.
Embodiment
Figure 1A is the schematic top plan view of the substrat structure 10 according to one embodiment of the invention.Substrat structure 10 can comprise dielectric substrate 100, groove 103, metal material 106 and capacitor 107.
Dielectric substrate has first surface 101 and the second surface 102 relative with described first surface.Although Figure 1A does not illustrate, those skilled in the art should be able to understand, the surface of dielectric substrate 100 or wherein can including but not limited to drive circuit, trace (trace), weld pad (pad) etc.The weld pad being positioned at first surface 101 can be electrically connected the drive circuit of dielectric substrate 100.
Dielectric substrate 100 can including but not limited to glass, quartz, silicon dioxide or other suitable insulating material.
Dielectric substrate 100 has the groove 103 formed from first surface 101 to second surface 102.Groove 103 is formed on sidewall 104 and bottom 105.The width of groove 103, such as, distance between groove 103 two side 104 is W.The degree of depth of groove 103, groove 103 opening is H to the distance of bottom 105.The shape of groove 103 can be helical form (spiral/helix) groove.Groove 103 can be but is not limited to square, circular arc, polygon or other geometry spiral groove.
Metal material 106 is comprised in groove 103.The side of metal material 106 and bottom contact with the sidewall 104 of groove 103 and bottom 105 respectively, but the upper surface of metal material 106 does not contact with the sidewall 104 of groove 103 and bottom 105.Metal material 106 can be copper or other suitable material.Because metal material 106 is arranged in spiral groove 103, therefore metal material 106 can be and is formed at inductor in dielectric substrate 100 or embedded inductor.
Capacitor 107 is positioned on the first surface 101 of dielectric substrate 100.Although capacitor 107 is not connected with metal material 106 in figure ia, those skilled in the art should understand and can be electrically connected with metal material 106 by capacitor 107 according to the design requirement of circuit.Bottom electrode and the metal material 106 of capacitor 107 is such as electrically connected through the interlayer metal layer (not shown) of trace (not shown) or dielectric substrate 100.According to another embodiment of the present invention, the first surface 101 of dielectric substrate 100 can comprise the active element and/or passive component that are different from capacitor 107.
Figure 1B is the generalized section of the A-A' line segment of substrat structure 10 along Figure 1A.The depth H of groove 103 and width W can determine width and the thickness D (not shown) of the metal material 106 being positioned at groove 103.Groove 103 can have but be not limited to the depth H from 30 μm to 280 μm, and has but be not limited to the width W from 15 μm to 100 μm.The depth H of groove 103 and the ratio of width W can be but be not limited to from 1:1 to 7:1.According to another embodiment of the present invention, the depth H of groove 103 and the ratio of width W can be 6:1.
Fig. 2 F is the schematic diagram of substrat structure 20 according to another embodiment of the present invention.The substrat structure 20 of Fig. 2 F is similar to the substrat structure 10 of Figure 1A and Figure 1B, has passivation layer 108, metal material layer 109 and passivation layer 110 above the first surface 101 that its difference is the dielectric substrate 100 of Fig. 2 F.
Passivation layer 108 can have multiple through hole (viahole) 108h.Metal material can be filled in through hole 108h from metal material layer 109 to downward-extension, to be electrically connected with the metal material 106 of the groove 103 being positioned at dielectric substrate 100 further.Passivation layer 110 is positioned on passivation layer 108 and metal material layer 109, and covers passivation layer 108 and the metal material layer 109 of a part.109 layers, the metal material not being passivated layer 110 covering can be electrically connected (not shown) with other circuit or other element.Passivation layer 108 covering capacitor 107, and metal material layer 109 is electrically connected with the top electrode of capacitor 107.
Passivation layer 108 and 110 can be polyimides (polyimide) or other is suitable as the material of passivation layer.Metal material layer 109 can be copper or other suitable electric conducting material.
Fig. 2 A-2F is the schematic diagram of the manufacture method of substrat structure according to another embodiment of the present invention.In fig. 2, dielectric substrate 100 is provided.Dielectric substrate 100 has first surface 101 and the second surface 102 relative with first surface 101.The first surface 101 of dielectric substrate 100 can comprise trace (trace), wire bonds weld pad (wirebondpad) and/or via (via).The material that dielectric substrate 100 can be used as dielectric substrate 100 known to those skilled in the art forms.For example, dielectric substrate 100 can be maybe to comprise glass, quartz, silicon dioxide or other suitable insulating material.
Groove 103 is formed to second surface 102 from described first surface 101.Groove 103 does not run through dielectric substrate 100, and in other words, groove 103 does not extend to second surface 102.Groove 103 can laser, etching or other technology be formed.Groove 103 has sidewall 104 and bottom 105.Distance between groove 103 two sidewalls 104 is width W and the opening of groove 103 is depth H to the distance of bottom 105.
According to one embodiment of the invention, the depth H of groove 103 can be 30 μm to 280 μm, and width W can be 15 μm to 100 μm.The depth H of groove 103 and the ratio of width W can be 1:1 to 7:1.According to another embodiment of the present invention, the depth H of groove 103 and the ratio of width W can be 6:1.
In fig. 2b, on the first surface 101 of described dielectric substrate 100 and in groove 103, metal material 106 is formed.Metal material 106 can be copper or other suitable material.Can use but be not limited to plating or other technology metal material 106 is formed on first surface 101 and in groove 103.
In fig. 2 c, grinding technique can be used to be removed by the metal material 106 on first surface 101, and the metal material 106 stayed in groove 103, make metal material 106 in the groove 103 of dielectric substrate 100 in fact with first surface 101 copline of dielectric substrate 100.Sidewall 104 and the bottom 105 of the side of metal material 106 and bottom and groove 103 contact.The upper surface of metal material 106 does not contact with the sidewall 104 of groove 103 and bottom 105.
Metal-insulator-metal type (MIM) capacitor 107 or other active or passive component can be formed on the first surface 101 of dielectric substrate 100.
In figure 2d, on the first surface 101 of dielectric substrate 100 and on described capacitor 107, passivation layer 108 is formed.Passivation layer 108 can comprise multiple through hole 108h.Through hole 108h runs through passivation layer 108 and expose portion metal material 106 and capacitor 107.Passivation layer 108 can be polyimides or other protective material be applicable to.Can use but be not limited to press mold (printing) or other technology formation passivation layer 108.Can use but be not limited to laser, etching or other technology and form through hole 108h.
In Fig. 2 E, metal material layer 109 can be formed on passivation layer 108 and in through hole 108h.The metal material layer 109 that part is positioned at through hole 108h can be electrically connected with metal material 106.The metal material layer 109 that part is positioned at through hole 108h can be electrically connected with capacitor 107.Plating or other technology can be used on passivation layer 108 and in through hole 108h to form metal material layer 109.Metal material layer 109 can including but not limited to copper or other suitable electric conducting material.
In fig. 2f, passivation layer 108 and metal material layer 109 form passivation layer 110.Passivation layer 110 cover part passivation layer 108 and metal material layer 109.Passivation layer 110 can comprise multiple through hole 109h.Through hole 109h exposing metal material layer 109.Passivation layer 110 can be polyimides or other protective material be applicable to.Can use but be not limited to press mold (printing) or other technology formation passivation layer 110.Can use but be not limited to laser, etching or other technology and form through hole 109h.Be not passivated layer 110 to cover or can be electrically connected with other circuit or other element by the metal material layer 109 that through hole 109h exposes.
Although do not draw in graphic, but in another embodiment of the invention, in the manufacture process shown in Fig. 2 A-2F, multiple, at least one row/row or substrat structure 20 of at least one array can be formed simultaneously, re-use cutting technique and be cut to multiple single substrat structure 20 as shown in Figure 2 F.
In fig. 2f, because metal material 106 is arranged in spiral groove 103, therefore metal material 106 can be and is formed at inductor in dielectric substrate 100 or embedded inductor.The quality factor (qualityfactor/Qfactor) of inductor is the important parameter determining inductor quality.The quality factor of inductor can be expressed in the following manner:
Q=Es/El formula (1)
Wherein Es is the gross energy of the reactive moieties being stored in inductor, and El is the gross energy of the reactive moieties being lost in inductor.
With regard to high-frequency circuit application, the quality requirements for inductor is relatively high.Namely the inductor used in circuit must have higher quality factor.When in the circuit of the narrow-band relevant with frequency, the inductor of high-quality-factor is even more important.Such as increase the inductor quality factor in oscillator, the phase noise of oscillator can be reduced, and the frequency of oscillator can be limited in narrower frequency band relatively accurately.
In semiconductor circuit or integrated circuit, the main cause causing inductor quality factor to decline has conductor losses, dielectric loss and substrate loss.The quality factor of inductor can be expressed in the following manner:
Q=ω × L/R formula (2)
Wherein, ω is angular frequency (angularfrequency), L is inductance value (inductance) and R is equiva lent impedance inductance loss being listed in consideration under characteristic frequency.From formula (2), by reducing or reduce the equiva lent impedance of inductor to reduce conductor losses, and then increase the quality factor of inductor.For example, the metallic circuit after can using high conductivity metal or thickness relatively to manufacture inductor, to reduce the impedance of inductor.
In another embodiment of the invention, metal level or the inductor layer (not shown) of predetermined thickness is formed on a surface of the substrate by gold-tinted technology and electroplating technology.But, owing to being subject to the restriction of passivation material characteristic, make by passivation layer protection single-layer metal layer thickness cannot more than 8-10 μm.Therefore, if the metal level that predetermined thickness is greater than such as more than 10 μm will be formed, so need to utilize more than twice gold-tinted technique to form the metal level with predetermined thickness at types of flexure.Although aforesaid mode can reduce inductive impedance to promote the quality factor of inductor, the gold-tinted technique of more than twice is used relatively to add manufacturing cost.In addition, the volume that the multilayer passivation layer of types of flexure and metal level/inductor layer inevitably significantly can increase semiconductor integrated circuit is sequentially formed in.Moreover, although passivation layer can protect metal/inductor layer, also can increase dielectric loss, and then the quality factor of inductor is declined.
In the substrat structure 10/20 that Figure 1A, 1B and 2F disclose, the depth H of groove 103 and the ratio of width W can be 1:1 to 7:1.For example, width can be formed be 15 μm and the degree of depth is the groove 103 of 90 μm in dielectric substrate 100.In other words, the metal material/inductor 106 not needing gold-tinted technique can form thickness in groove 103 to be greater than more than 30 μm, significantly reduces the cost of gold-tinted technique.Metal material/the inductor 106 of substrat structure 10/20 has relatively low conductor losses and relatively high quality factor.
In addition, the metal material 106 forming inductor due to major part is positioned at dielectric substrate 100, but not is positioned at passivation layer, therefore can reduce dielectric loss.And the mutual inductance effect that dielectric substrate 100 can effectively be avoided in groove 103 between metal material 106 and/or and dielectric substrate 100 in mutual inductance effect between other metallic circuit/element, and then increase the quality factor of inductor.
According to one embodiment of the invention, Fig. 3 is disclosed in (0.5GHz to 10GHz) under different frequency of operation, is arranged in the relation between the metal thickness of the inductor of substrat structure 10/20 shown in Figure 1A, 1B and 2F 106 and quality factor.As shown in Figure 3, under identical frequency of operation, the thickness of metal material/inductor 106 is larger, and so the quality factor of inductor is higher.
Fig. 4 is the schematic diagram of substrat structure according to another embodiment of the present invention.The substrat structure 40 of Fig. 4 is similar to the substrat structure 10 shown in Figure 1A and 1B, and its difference is that the thickness of metal material 106 is greater than the depth H of the groove 103 of dielectric substrate 100.That is, the metal material 106 inserting groove 103 can protrude the first surface 101 of dielectric substrate 100, to increase the thickness of metal material 106 further.According to another embodiment of the present invention, in order to meet the different needs, the thickness of metal material 106 also can be less than the depth H (not shown) of the groove 103 of dielectric substrate 100.That is, metal material 106 indent of described groove 103 or the first surface 101 lower than dielectric substrate 100 is inserted.
Fig. 5 is the schematic diagram of substrat structure according to another embodiment of the present invention.The substrat structure 50 that Fig. 5 discloses is similar to the substrat structure 20 that Fig. 2 F discloses, and its difference is that substrat structure 50 comprises groove 103', metal material 106', passivation layer 108', metal material layer 109' and passivation layer 110' further.Groove 103', metal material 106', passivation layer 108', metal material layer 109' and passivation layer 110' are similar to groove 103, metal material 106, passivation layer 108, metal material layer 109 and passivation layer 110.
The structure of groove 103' and generation type are similar to structure and the generation type of groove 103.Groove 103' can be formed to first surface 101 from the second surface 102 of dielectric substrate 100.Groove 103' has sidewall 104' and bottom 105'.Distance between the two side 104' of groove 103' be width W ' and the opening of described groove 103' to the distance of bottom 105' be depth H '.
Metal material 106' is comprised in groove 103'.Sidewall 104' and the bottom 105' of the side of metal material 106' and bottom and groove 103' contact, but the lower surface of metal material 106' with the sidewall 104' or bottom 105' of groove 103' does not contact.
Passivation layer 108' to be positioned on second surface 102 and to comprise multiple through hole 108h'.Metal material can extend from metal material layer 109' and be filled in through hole 108h', to be electrically connected with the metal material 106' of the groove 103' being positioned at dielectric substrate 100 further.Passivation layer 110' is positioned on passivation layer 108' and metal material layer 109', and covers passivation layer 108' and the metal material layer 109' of a part.Be not passivated a layer metal material 109' layer for 110' covering and can be electrically connected (not shown) with other circuit or other element.
According to one embodiment of the invention, the width W of groove 103' ' and depth H ' can be identical with the width W of groove 103 and depth H respectively.According to another embodiment of the present invention, groove 103' width W ' and depth H ' can respectively with the width W of groove 103 and depth H different.According to one embodiment of the invention, described metal material 106' and 109' can be copper or other suitable material.According to one embodiment of the invention, described passivation layer 108' and 110' can be polyimides (polyimide) or other is suitable as the protective material of passivation layer.
Substrat structure 50 can comprise two inductors, is namely positioned at electric conducting material 106 and the 106' of groove 103 and groove 103'.The relative position of groove 103 groove 103' can adjust according to design requirement or change.Groove 103 can be mutual dislocation, i.e. groove 103' not overlapping with any portion of groove 103 (shown in dotted line) on the direction of vertical first surface 101 with the position relationship of 103'.The channel layout of dislocation mutually can reduce the mutual inductance effect between the metal material 106 in groove 103 and the metal material 106' in groove 103' up and down, affects each other to avoid contained signal in two inductors.According to another embodiment of the present invention, groove 103 and 103' can partial transposition, i.e. part of trench 103' (not shown) overlapping with part of trench 103 on the direction of vertical first surface 101.
Fig. 6 is the schematic diagram of substrat structure according to another embodiment of the present invention.The substrat structure 50 that substrat structure 60 and Fig. 5 that Fig. 6 discloses disclose is similar, and its difference is that the groove 103 of substrat structure 60 is overlapping on the direction of vertical first surface 101 with 103', and namely the position of groove 103' and groove 103 is symmetrical mutually up and down.
According to one embodiment of the invention, the substrat structure 50,60 of Fig. 5 and Fig. 6 respectively comprises two inductors, is namely positioned at electric conducting material 106 and the 106' of groove 103 and groove 103'.Spacing between the geometrical pattern of groove 103,103', width W, W', depth H, H' and two groove all can adjust arbitrarily according to different designs and demand and change.The power-on and power-off sensor 106 that substrat structure 50,60 comprises and 106' can form transformer.The coupling coefficient of transformer and magnetizing inductance device etc. decide by the degree of depth (or thickness of electric conducting material 106 and 106') of adjustment groove 103/103', the primary coil (inductor 106) of described transformer and the relative position of secondary coil (inductor 106') and coil number (inductor number).
Fig. 7 is the schematic diagram of substrat structure according to another embodiment of the present invention.The substrat structure 70 that Fig. 7 discloses is similar to the substrat structure 20 that Fig. 2 F discloses, and its difference is that Fig. 7 comprises two inductor 70a and 70b.Two inductor 70a and 70b are connected in series with electric conducting material 109a, and inductor 70b is electrically connected with metal material 109 with the bottom electrode of capacitor 107.According to one embodiment of the invention, Fig. 7 is that two inductors are connected in series and are connected in series with capacitor 107.According to another embodiment of this case, the connected mode of inductor and capacitor can change arbitrarily according to the design requirement of circuit, to form required passive circuit (such as: filter).
Above-described embodiment is only and principle of the present invention and effect thereof is described, and is not used to limit the present invention.In addition, above-mentioned used " can be ", " can comprise ", " can use " etc., word was all not used to limit the present invention.Those skilled in the art still without departing the teaching of the invention with under announcement can carry out many changes and amendment.Therefore, scope of the present invention is not defined in the embodiment that disclosed and comprises and do not deviate from other change of the present invention and amendment, its for as following claims the scope that contained.
Claims (15)
1. a substrat structure, it comprises:
Dielectric substrate, described dielectric substrate has first surface and the second surface relative with described first surface, described dielectric substrate has the first groove be formed into from described first surface described second surface, and described first groove is formed by bottom the first side wall and first; And
First electric conducting material, described first electric conducting material is positioned at described first groove at least partly, and wherein said first electric conducting material has first surface, bottom described first surface does not contact described first and described the first side wall.
2. substrat structure according to claim 1, it comprises passivation layer further, the first surface of dielectric substrate described in described passivation layer cover part and the first surface of described first electric conducting material of part.
3. substrat structure according to claim 1, wherein said first electric conducting material has the first thickness, and described first groove has first degree of depth, and described first thickness can be less than, be equal to or greater than described first degree of depth.
4. substrat structure according to claim 1, wherein said first groove has first degree of depth and the first width, and described first degree of depth is essentially six times of described first width.
5. substrat structure according to claim 1, wherein said first electric conducting material has the first thickness, by adjusting described first thickness to control inductance value and the inductance characteristic of described substrat structure.
6. the substrat structure according to claim arbitrary in claim 1 to 5, it comprises the second electric conducting material further, wherein said dielectric substrate comprises the second groove be formed into from described second surface described first surface further, described second groove is formed by bottom the second sidewall and second, and described second electric conducting material is positioned at described second groove at least partly.
7. substrat structure according to claim 6, wherein said second electric conducting material has second surface, bottom described second surface does not contact described second and described second sidewall.
8. substrat structure according to claim 6, it comprises the second passivation layer further, the second surface of dielectric substrate described in described second passivation layer cover part and the second surface of described second electric conducting material of part.
9. substrat structure according to claim 6, wherein said second electric conducting material has the second thickness, and described second groove has second degree of depth, and described second thickness can be greater than, be equal to or less than described second degree of depth.
10. substrat structure according to claim 6, wherein said second groove has second degree of depth and the second width, and described second degree of depth is essentially six times of described second width.
11. substrat structures according to claim 6, wherein said second electric conducting material has the second thickness, by described second thickness of described first thickness and described second electric conducting material that adjust described first electric conducting material to control mutual inductance value and the coefficient of mutual inductance of described substrat structure.
12. substrat structures according to claim 6, wherein by adjusting the relative position of described first groove and described second groove to control mutual inductance value and the coefficient of mutual inductance of described substrat structure.
The manufacture method of 13. 1 kinds of substrat structures, it comprises:
There is provided dielectric substrate, described dielectric substrate has first surface and the second surface relative with described first surface;
From described first surface to described second surface, form the first groove on the first surface, described first groove is formed by bottom the first side wall and first; And
At least part of first electric conducting material is inserted in described first groove,
Wherein said first electric conducting material has first surface, bottom described first surface does not contact described first and described the first side wall.
14. methods according to claim 13, it comprises further:
Form the first passivation layer on the first surface, the first surface of dielectric substrate described in described first passivation layer cover part and the first surface of described first electric conducting material of part; And
One or more electrical connection is not formed by the part that described passivation layer covers from the first surface of described first electric conducting material.
15. methods according to claim 13, wherein comprise further by the step that described first electric conducting material is inserted in described first groove:
Described first electric conducting material is coated on the described first surface with described first groove; And
Described first electric conducting material protruding described first groove is removed from described first surface.
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| CN201410287674.4A CN105244367A (en) | 2014-06-24 | 2014-06-24 | Substrate structure and manufacturing method thereof |
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| CN201410287674.4A CN105244367A (en) | 2014-06-24 | 2014-06-24 | Substrate structure and manufacturing method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105977240A (en) * | 2016-05-17 | 2016-09-28 | 电子科技大学 | Monolithic integration miniature transformer |
| CN106653728A (en) * | 2016-11-23 | 2017-05-10 | 无锡吉迈微电子有限公司 | Integrated inductor structure and manufacturing method thereof |
| CN110098739A (en) * | 2019-05-08 | 2019-08-06 | 宁波大学 | A kind of DC-DC decompression converting circuit based on on-chip inductors |
| CN114157257A (en) * | 2021-12-03 | 2022-03-08 | 电子科技大学 | Integrated LC filter and manufacturing method thereof |
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| US5519582A (en) * | 1992-10-05 | 1996-05-21 | Fuji Electric Co., Ltd. | Magnetic induction coil for semiconductor devices |
| US20010002060A1 (en) * | 1998-10-26 | 2001-05-31 | Leonard Forbes | Monolithic inductance-enhancing integrated circuits, complementary metal oxide semiconductor (CMOS) inductance-enhancing integrated circuits, inductor assemblies, and inductance-multiplying methods |
| CN1292628C (en) * | 2001-10-10 | 2006-12-27 | St微电子公司 | Method for forming induction and through-hole in single chip circuit |
| US20090039999A1 (en) * | 2007-08-06 | 2009-02-12 | Shinko Electric Industries Co., Ltd. | Inductor device and method of manufacturing the same |
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| JPH02208909A (en) * | 1989-02-08 | 1990-08-20 | Matsushita Electric Ind Co Ltd | Inductance element and transformer |
| US5519582A (en) * | 1992-10-05 | 1996-05-21 | Fuji Electric Co., Ltd. | Magnetic induction coil for semiconductor devices |
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| CN105977240A (en) * | 2016-05-17 | 2016-09-28 | 电子科技大学 | Monolithic integration miniature transformer |
| CN106653728A (en) * | 2016-11-23 | 2017-05-10 | 无锡吉迈微电子有限公司 | Integrated inductor structure and manufacturing method thereof |
| CN110098739A (en) * | 2019-05-08 | 2019-08-06 | 宁波大学 | A kind of DC-DC decompression converting circuit based on on-chip inductors |
| CN114157257A (en) * | 2021-12-03 | 2022-03-08 | 电子科技大学 | Integrated LC filter and manufacturing method thereof |
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