CN105279127A - FPGA program downloading system based on PCI or PCIe bus, and method - Google Patents
FPGA program downloading system based on PCI or PCIe bus, and method Download PDFInfo
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- CN105279127A CN105279127A CN201510829561.7A CN201510829561A CN105279127A CN 105279127 A CN105279127 A CN 105279127A CN 201510829561 A CN201510829561 A CN 201510829561A CN 105279127 A CN105279127 A CN 105279127A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
Abstract
The invention relates to an FPGA program downloading system based on a PCI or PCIe bus, and a method and solves problems that FPGA program downloading efficiency through a traditional JTAG mode is low, and system reliability deceases as a circuit board or external cables are dismounted during update of the FPGA program. The FPGA program downloading system based on the PCI/the PCIe bus comprises a host, an FPGA and an EPCS configuration chip, the host is connected with the FPGA through the PCI/the PCIe bus, the FPGA comprises a PCI/the PCIe bus controller, an Avalon bus, an EPCS controller and a function assembly customized by a user, inner assemblies of the FPGA are connected through the Avalon bus, and the EPCS configuration chip is connected with the FPGA. The FPGA program downloading system based on the PCI or PCIe bus is applied to the FPGA program downloading field.
Description
Technical field
The present invention relates to FPGA program downloading system and the method for Based PC I or PCIe bus.
Background technology
Traditional field programmable gate array (FieldProgrammableGateArray, FPGA) device due to it, there is architecture and logical block is flexible, integrated level is high and the scope of application is wide etc., exploitation flexibly, the feature such as high speed, all there is widespread use in many fields such as electronics, communication, Industry Control.The framework of main flow FPGA mainly contains SRAMBase and Anti-fuse two kinds of Design Modes, wherein the feature of SRAMBase be can overprogram, low-power consumption, can system reconfiguration be carried out; Anti-fuse, owing to having the characteristic of a burning, cannot carry out repeating amendment.The most of FPGA used in the market are based on SRAMBase technique, and because SRAM has power down obliterated data, the logic of its inside of FPGA power down also will disappear.Therefore, generally need in FPGA product design to adopt nonvolatile memory such as EPROM, FLASH outside sheet to carry out storage program, after powering on, FPGA therefrom reads configuration data.In order to by download program in configuring chip, often need external interface and cable, such as JTAG and the corresponding interface download.In actual applications, FPGA product may be inconvenient to dismantle or external cable, to upgrade or when safeguarding, if use classic method refresh routine, will seem very complicated with difficulty, even serve unnecessary problem to system band.
PCI (PeripheralComponentInterconnect) bus be 1992 by peripheral parts interconnected professional association (PeripheralComponentInterconnectSpecialInterestGroup, PCI-SIG) a kind of local bus standard proposed, which replacing previous isa bus becomes second generation IO bus.From data width, pci bus has dividing of 32bit, 64bit; From bus speed point, have 33MHz, 66MHz two kinds, what extensively adopt at present is the pci bus of 32-bit, 33MHz.Pci bus has the advantages such as transmission speed is high, stability is high, compatibility is good, is widely used in digital figure, image and speech processes, and the field such as high-speed real data acquisition and process.PCIe (PeripheralComponentInterconnectExpress) bus is in the advantage inheriting second generation bus architecture, adopt the technology such as serial transmission and Delamination Transmission, and development a kind of third generation IO bus out, be the bus interface of current main flow.It can realize the communication of serial between equipment, point-to-point, and the single channel theoretical peak bandwidth of the PCIe bus of the third generation reaches 984MB/s.Due to PCIe bus provide high speed bandwidth, easily extensible, high-level efficiency, high stability, with the many advantages such as PCI is compatible, its range of application, from traditional PC and graphics workstation field to external expansion, calculates at server, storage, route, multi-display and is obtained for application widely in industrial embedded system.
At present, the download program of traditional FPGA is all adopt jtag interface download program in the configuring chip of FPGA.This downloading mode is suitable for the production phase of laboratory debugging and product.But, after also installing after product is paid, if need to carry out FPGA program updates, then need circuit board to disassemble, then connect download cable at jtag interface and carry out download program.When systematic comparison is complicated, the dismounting of circuit board can cause the decline of system reliability, even can cause new problem.In addition, the installation environment of equipment may not allow entering of personnel, as high temperature, strong radiation environment.When product quantity is larger, sending someone to process produced human cost to the FPGA program of equipment will be very huge.
Summary of the invention
The object of the invention is in order to solve prior art carry out FPGA program updates time, need circuit board to disassemble, then connect download cable at jtag interface and carry out download program; When systematic comparison is complicated, the dismounting of circuit board can cause the decline of system reliability, the installation environment of equipment may not allow entering of personnel, and when product quantity is larger, send someone to process to the FPGA program of equipment the problem that produced human cost will be very huge, and the FPGA program downloading system of a kind of Based PC I proposed or PCIe bus and method.
Above-mentioned goal of the invention is achieved through the following technical solutions:
A FPGA program downloading system for Based PC I/PCIe bus, comprises host computer, FPGA and EPCS configuring chip;
Data transmission is carried out by PCI/PCIe bus between host computer and FPGA; FPGA comprises PCI/PCIe bus controller, Avalon bus, EPCS controller and user-defined functional module;
Host computer is connected with PCI/PCIe bus controller by PCI/PCIe bus, PCI/PCIe bus controller is connected with Avalon bus, Avalon bus is connected with user-defined functional module and EPCS controller respectively, and EPCS controller is connected with EPCS configuring chip;
FPGA is field programmable gate array;
Pci bus is PCI (peripheral component interconnect) bus;
PCIe bus is peripheral parts interconnected high-speed bus;
EPCS is erasable serial storage able to programme.
A kind of FPGA program down-loading method of Based PC I/PCIe bus is specifically prepared according to following steps:
Step one, beginning;
Step 2, the fopen function of C language is utilized to open the FPGA configuration file of flash form to be downloaded and the NiosII project file of flash form to be downloaded;
Step 3, convert the NiosII project file data of the FPGA configuration file of flash form to be downloaded and flash form to be downloaded to binary data after both are merged into a binary format file, draw the binary format file after merging;
Step 4, utilize the fread function of C language by merge after binary format file read calculator memory;
Binary format file in calculator memory is write EPCS configuring chip by the EPCS controller that step 5, host computer call in the alt_epcs_flash_write function control FPGA in Altera function library;
Step 6, host computer call the alt_epcs_flash_memcmp function in Altera function library, are read the binary format file after merging in binary format file and step 3 in EPCS configuring chip and carried out contrast to verify by EPCS controller in control FPGA; Verification makes mistakes, and performs step 7; Verification is correct, performs step 8;
Perform step 5 when step 7, number of times of makeing mistakes are 1, when being more than or equal to 2, perform step 9;
The success of step 8, download program; Perform step 10;
The failure of step 9, download program; Perform step 10;
Step 10, end;
FPGA is field programmable gate array;
Pci bus is PCI (peripheral component interconnect) bus;
PCIe bus is peripheral parts interconnected high-speed bus;
EPCS is erasable serial storage able to programme.
Invention effect
For above problem, this programme proposes FPGA program downloading system and the method for a kind of Based PC I or PCIe bus, mainly be applicable to the FPGA board adopting the interfaces such as PCI/PXI/CPCI/PC104 or PCIe/PXIE, this programme is according to the feature of PCI and PCIe board, achieve directly by pci bus or PCIe bus directly from host computer by FPGA download program to the configuring chip of FPGA, and without the need to carrying out board dismounting and external JATG download cable, therefore the inconvenience of traditional JTAG downloading mode can be solved well, avoid the decline of the system reliability that the dismounting of circuit board or external download cable cause, the installation environment solving equipment may not allow entering of personnel or when product quantity is larger, send someone to carry out to the FPGA program of equipment the problem that human cost that update process produces will be very huge, the maintenance of the FPGA product of practical application and upgrading are provided convenience.Test according to reality, this downloading mode is utilized to carry out the time of program updates cost to FPGA board, Billy upgrades FPGA program with traditional JTAG downloading mode and shortens 80%, the efficiency that improve system update and maintenance of high degree, avoids the system stability caused because of refresh routine simultaneously and declines.The hardware block diagram of system as shown in Figure 1, is described in detail for FPGA and EPCS of altera corp (ErasableProgrammableConfigurableSerial) Flash configuring chip in figure.
Accompanying drawing explanation
Fig. 1 is the FPGA program downloading system hardware structure diagram of Based PC I/PCIe bus;
Fig. 2 is the upper computer software surface chart of the FPGA program downloading system of Based PC I/PCIe bus;
Fig. 3 is process flow diagram of the present invention;
Fig. 4 changes the process display figure that sof file is flash file;
Fig. 5 changes the process display figure that elf file is flash file;
Fig. 6 is the display figure after opening upper computer software success;
Fig. 7 is the FPGA configuration file selection interface display figure of flash form to be downloaded;
Fig. 8 is that the FPGA configuration file of flash form to be downloaded opens host computer interface display figure successfully;
Host computer interface display figure when Fig. 9 is for choosing " NiosII program " option;
Figure 10 is the NiosII program file display figure opening flash form to be downloaded;
Figure 11 is that the NiosII program file of flash form to be downloaded opens host computer interface display figure successfully;
Figure 12 is information columns display routine download state figure;
Figure 13 is that download program completes backed off after random upper computer software display figure.
Embodiment
Embodiment one: the FPGA program downloading system of a kind of Based PC I/PCIe bus of present embodiment, comprises host computer, FPGA and EPCS configuring chip; As shown in Figure 1, FPGA and the EPCSFlash configuring chip for altera corp in figure is described in detail the hardware block diagram of system;
Data transmission is carried out by PCI/PCIe bus between host computer and FPGA; Host computer in native system is computing machine; FPGA comprises PCI/PCIe bus controller, Avalon bus, EPCS controller and user-defined functional module (user adds according to actual development needs oneself, such as analog acquisition function, switch acquisition function, 1553B monitoring bus function etc.);
Host computer is connected with PCI/PCIe bus controller by PCI/PCIe bus, PCI/PCIe bus controller is connected with Avalon bus, Avalon bus is connected with user-defined functional module and EPCS controller respectively, and EPCS controller is connected with EPCS configuring chip;
FPGA is field programmable gate array;
Pci bus is PCI (peripheral component interconnect) bus;
PCIe bus is peripheral parts interconnected high-speed bus;
EPCS is erasable serial storage able to programme;
Avalon bus is a kind of bus on chip of altera corp's definition, realizes the interconnected of the inner each assembly of FPGA;
EPCS configuring chip stores FPGA configuration file and NiosII project file, and EPCS configuring chip connects EPCS controller; FPGA configuration file and NiosII project file are for configuring FPGA, and FPGA passes through the realization of EPCS controller to the access of EPCS configuring chip and control.
Upper computer software interface is as Fig. 2, and the function that this host computer mainly realizes has: some the important information displays etc. selecting the Read-write Catrol of fpga program file to EPCS to be downloaded, EPCS chip, the display of board state and system.
Embodiment two: composition graphs 3 illustrates present embodiment, the FPGA program down-loading method of a kind of Based PC I/PCIe bus of present embodiment, specifically prepare according to following steps:
Step one, beginning;
Step 2, the fopen function of C language is utilized to open the FPGA configuration file of flash form to be downloaded and the NiosII project file of flash form to be downloaded;
Step 3, convert the NiosII project file data of the FPGA configuration file of flash form to be downloaded and flash form to be downloaded to binary data after both are merged into a binary format file, draw the binary format file after merging;
Step 4, utilize the fread function of C language by merge after binary format file read calculator memory;
Binary format file in calculator memory is write EPCS configuring chip by the EPCS controller that step 5, host computer call in the alt_epcs_flash_write function control FPGA in Altera function library;
Step 6, host computer call the alt_epcs_flash_memcmp function in Altera function library, are read the binary format file after merging in binary format file and step 3 in EPCS configuring chip and carried out contrast to verify by EPCS controller in control FPGA; Verification makes mistakes, and performs step 7; Verification is correct, performs step 8;
Perform step 5 when step 7, number of times of makeing mistakes are 1, when being more than or equal to 2, perform step 9;
The success of step 8, download program; Perform step 10;
The failure of step 9, download program; Perform step 10;
Step 10, end;
FPGA is field programmable gate array;
PCI (PeripheralComponentInterconnect) bus is PCI (peripheral component interconnect) bus;
PCIe (PeripheralComponentInterconnectExpress) bus is peripheral parts interconnected high-speed bus;
EPCS (ErasableProgrammableConfigurableSerial) is erasable serial storage able to programme.
Embodiment three: present embodiment and embodiment two unlike: utilize the fopen function of C language to open the FPGA configuration file of flash form to be downloaded and the NiosII project file of flash form to be downloaded in described step 2; Detailed process is:
Due to will by download program in EPCSFlash in the design, so the program file to be downloaded selected must be the fixed file format being applicable to Flash device, the design of this host computer have employed conventional .flash formatted file, usually the instrument in NiosII Integrated Development software such as Flash downloader (FlashProgrammer) or command Window (ShellCommand) can be utilized to convert the FPGA configuration file of .sof form to be downloaded and the NiosII project file of .elf form FPGA configuration file and the NiosII project file of corresponding flash form to, then in host computer, utilize the fopen function of C language to open the FPGA configuration file of flash form to be downloaded and the NiosII project file of flash form to be downloaded, described host computer is computing machine.
Other step and parameter identical with embodiment two.
Embodiment four: present embodiment and embodiment two or three unlike: after converting the NiosII project file of the FPGA configuration file of flash form to be downloaded and flash form to be downloaded to binary data in described step 3, both are merged into a binary format file, draw the binary format file after merging; Detailed process is:
Data in the FPGA configuration file of flash form to be downloaded and the NiosII project file of flash form to be downloaded are character format, in host computer, utilize the fopen function of C language to open these two files respectively and utilize fread function to read FPGA configuration file data and NiosII project file data, then according to the corresponding relation of character data and binary data in ASCII character table, the FPGA configuration file data read and NiosII project file data are converted into binary format data respectively, finally both are merged, data are write a new binary format file by recycling fwrite function, draw the binary format file after merging.
Other step and parameter identical with embodiment two or three.
Embodiment five: present embodiment and embodiment two, three or four unlike: the binary format file in calculator memory is write EPCS configuring chip by the EPCS controller in the alt_epcs_flash_write function control FPGA that in described step 5, host computer calls in Altera function library; Detailed process is:
Host computer calls the alt_epcs_flash_write function in the function library (carrying when installing NiosII Integrated Development software) that altera corp provides, host computer by by the EPCS controller in PCI/PCIe bus marco FPGA by the binary format file write EPCS configuring chip in calculator memory.
After download program success, obtain the board after refresh routine, restart the board FPGA after refresh routine and just the configurator after reading renewal from EPCS configuring chip is completed the configuration to FPGA, now user just can see the ruuning situation upgrading rear program.
Other step and parameter and embodiment two, three or four identical.
Other step and parameter and embodiment two, three, four or five identical.
Following examples are adopted to verify beneficial effect of the present invention:
Embodiment one:
Adopt the FPGA program down-loading method of a kind of Based PC I of the present invention or PCIe bus, specifically prepare according to following steps:
Step one: the elf file (Test.elf in this example) that the .sof file (Test.sof in this example) utilizing NiosIIShellCommand to be generated by required QuartusII and NiosIIIDE generate is converted to .flash formatted file, and Fig. 4 changes the process that sof file is flash file; Fig. 5 changes the process that elf file is flash file;
Step 2: open upper computer software, opens successfully as Fig. 6;
Step 3: click " opening file " button in " FPGA configurator (.flash) " a line, occurs that interface selected by file, finds and need the flash form FPGA file of download and open, as shown in Figure 7; After File Open success, host computer interface is as Fig. 8;
Step 4: choose the square frame before " NiosII program (.flash) " in interface, after choosing, " open file button " of this row is available, clicks this button to open NiosII program file, as shown in Figure 9; After occurring that interface selected by file, select need the NiosII program file of the flash form downloaded and open, as Figure 10; After File Open success, host computer interface display is as Figure 11;
Step 5: click " starting to download " button, software starts execution and downloads, and in host computer interface, all buttons are by unavailable, information columns display routine download state, as Figure 12:
Step 6: wait routine has been downloaded, when the information columns of host computer interface points out " download program completes " and button reverts to state before program starts to download, representation program has been downloaded, and now can exit upper computer software, as shown in figure 13.Now restart FPGA board and FPGA just will be imported the configurator of up-to-date download from EPCS.
The present invention also can have other various embodiments; when not deviating from the present invention's spirit and essence thereof; those skilled in the art are when making various corresponding change and distortion according to the present invention, but these change accordingly and are out of shape the protection domain that all should belong to the claim appended by the present invention.
Claims (5)
1. a FPGA program downloading system for Based PC I/PCIe bus, comprises host computer, FPGA and EPCS configuring chip;
Data transmission is carried out by PCI/PCIe bus between host computer and FPGA; FPGA comprises PCI/PCIe bus controller, Avalon bus, EPCS controller and user-defined functional module;
Host computer is connected with PCI/PCIe bus controller by PCI/PCIe bus, PCI/PCIe bus controller is connected with Avalon bus, Avalon bus is connected with user-defined functional module and EPCS controller respectively, and EPCS controller is connected with EPCS configuring chip;
FPGA is field programmable gate array;
Pci bus is PCI (peripheral component interconnect) bus;
PCIe bus is peripheral parts interconnected high-speed bus;
EPCS is erasable serial storage able to programme.
2. a FPGA program down-loading method for Based PC I/PCIe bus, is characterized in that what a kind of FPGA program down-loading method of Based PC I/PCIe bus was specifically prepared according to following steps:
Step one, beginning;
Step 2, the fopen function of C language is utilized to open the FPGA configuration file of flash form to be downloaded and the NiosII project file of flash form to be downloaded;
Step 3, convert the NiosII project file data of the FPGA configuration file of flash form to be downloaded and flash form to be downloaded to binary data after both are merged into a binary format file, draw the binary format file after merging;
Step 4, utilize the fread function of C language by merge after binary format file read calculator memory;
Binary format file in calculator memory is write EPCS configuring chip by the EPCS controller that step 5, host computer call in the alt_epcs_flash_write function control FPGA in Altera function library;
Step 6, host computer call the alt_epcs_flash_memcmp function in Altera function library, are read the binary format file after merging in binary format file and step 3 in EPCS configuring chip and carried out contrast to verify by EPCS controller in control FPGA; Verification makes mistakes, and performs step 7; Verification is correct, performs step 8;
Perform step 5 when step 7, number of times of makeing mistakes are 1, when being more than or equal to 2, perform step 9;
The success of step 8, download program; Perform step 10;
The failure of step 9, download program; Perform step 10;
Step 10, end;
FPGA is field programmable gate array;
Pci bus is PCI (peripheral component interconnect) bus;
PCIe bus is peripheral parts interconnected high-speed bus;
EPCS is erasable serial storage able to programme.
3. the FPGA program down-loading method of a kind of Based PC I/PCIe bus according to claim 2, is characterized in that: utilize the fopen function of C language to open the FPGA configuration file of flash form to be downloaded and the NiosII project file of flash form to be downloaded in described step 2; Detailed process is:
The FPGA configuration file of .sof form to be downloaded and the NiosII project file of .elf form are converted to FPGA configuration file and the NiosII project file of corresponding flash form, in host computer, then utilize the fopen function of C language to open the FPGA configuration file of flash form to be downloaded and the NiosII project file of flash form to be downloaded.
4. the FPGA program down-loading method of a kind of Based PC I/PCIe bus according to claim 3, it is characterized in that: after converting the NiosII project file of the FPGA configuration file of flash form to be downloaded and flash form to be downloaded to binary data in described step 3, both are merged into a binary format file, draw the binary format file after merging; Detailed process is:
Data in the FPGA configuration file of flash form to be downloaded and the NiosII project file of flash form to be downloaded are character format, in host computer, utilize the fopen function of C language to open these two files respectively and utilize fread function to read FPGA configuration file data and NiosII project file data, then according to the corresponding relation of character data and binary data in ASCII character table, the FPGA configuration file data read and NiosII project file data are converted into binary format data respectively, finally both are merged, data are write a new binary format file by recycling fwrite function, draw the binary format file after merging.
5. the FPGA program down-loading method of a kind of Based PC I/PCIe bus according to claim 4, is characterized in that: the EPCS controller in the alt_epcs_flash_write function control FPGA that in described step 5, host computer calls in Altera function library is by the binary format file write EPCS configuring chip in calculator memory; Detailed process is:
Host computer calls the alt_epcs_flash_write function in the function library that altera corp provides, host computer by by the EPCS controller in PCI/PCIe bus marco FPGA by the binary format file write EPCS configuring chip in calculator memory.
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| CN106528217A (en) * | 2016-10-26 | 2017-03-22 | 武汉船舶通信研究所 | FPGA (Field Programmable Gate Array) program loading system and method |
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| CN110955620A (en) * | 2019-12-13 | 2020-04-03 | 中国兵器装备集团自动化研究所 | 1553B bus protocol system based on PCIE |
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| CN106528217A (en) * | 2016-10-26 | 2017-03-22 | 武汉船舶通信研究所 | FPGA (Field Programmable Gate Array) program loading system and method |
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| CN109542478A (en) * | 2018-11-09 | 2019-03-29 | 中电科仪器仪表有限公司 | A kind of system and method updating FPGA program in SPI Flash |
| CN109599048A (en) * | 2019-01-09 | 2019-04-09 | 惠科股份有限公司 | A kind of display device and its driving method and display |
| CN109918325A (en) * | 2019-03-06 | 2019-06-21 | 苏州浪潮智能科技有限公司 | Interface conversion bridge, interface conversion method and system based on Avalon bus |
| CN109918325B (en) * | 2019-03-06 | 2020-12-04 | 苏州浪潮智能科技有限公司 | Interface conversion bridge based on Avalon bus, interface conversion method and system |
| CN109901506A (en) * | 2019-03-19 | 2019-06-18 | 浙江中控研究院有限公司 | A kind of configurable PLC based on PCIe bus |
| CN110955620A (en) * | 2019-12-13 | 2020-04-03 | 中国兵器装备集团自动化研究所 | 1553B bus protocol system based on PCIE |
| CN110955620B (en) * | 2019-12-13 | 2023-06-13 | 中国兵器装备集团自动化研究所 | 1553B bus protocol system based on PCIE |
| CN111414325A (en) * | 2020-02-29 | 2020-07-14 | 苏州浪潮智能科技有限公司 | Method for converting Avalon bus into Axi4 bus |
| US11657011B2 (en) | 2020-02-29 | 2023-05-23 | Inspur Suzhou Intelligent Technology Co., Ltd. | Avalon-to-Axi4 bus conversion method |
| CN111414325B (en) * | 2020-02-29 | 2021-09-17 | 苏州浪潮智能科技有限公司 | Method for converting Avalon bus into Axi4 bus |
| CN114328342A (en) * | 2020-09-29 | 2022-04-12 | 中国船舶重工集团公司第七二四研究所 | Novel program control configuration method for PCIe heterogeneous accelerator card |
| CN114328342B (en) * | 2020-09-29 | 2023-09-26 | 中国船舶集团有限公司第七二四研究所 | Novel program control configuration method for PCIe heterogeneous accelerator card |
| CN117692344A (en) * | 2024-02-02 | 2024-03-12 | 成都大征创智科技有限公司 | Network equipment simulation method based on FPGA code compiling |
| CN117692344B (en) * | 2024-02-02 | 2024-04-16 | 成都大征创智科技有限公司 | Network equipment simulation method based on FPGA code compiling |
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