CN105405918A - Method for preparing photodiode - Google Patents
Method for preparing photodiode Download PDFInfo
- Publication number
- CN105405918A CN105405918A CN201410459546.3A CN201410459546A CN105405918A CN 105405918 A CN105405918 A CN 105405918A CN 201410459546 A CN201410459546 A CN 201410459546A CN 105405918 A CN105405918 A CN 105405918A
- Authority
- CN
- China
- Prior art keywords
- semiconductor substrate
- mask layer
- type ion
- implanted region
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention discloses a method for preparing a photodiode, and belongs to the technical field of CIS manufacture. The method comprises the steps of providing a semiconductor substrate provided with a P-type well region; depositing a mask layer on the semiconductor substrate, and then etching the upper surface of the semiconductor substrate; taking the remaining mask layer as a mask, carrying out ion implantation process for the exposed semiconductor substrate by a groove, and forming an N-type ion implantation region in the semiconductor substrate; preparing a side wall on the side wall of the groove, and then continuing a non-crystallizing ion implantation process; removing the side wall and the partial mask located on the remaining N-type ion implantation region; etching the exposed semiconductor substrate located in the remaining N-type ion implantation region to form a trench; filling the trench with an epitaxial layer; and removing the mask layer and the epitaxial layer to form a pining layer, and then etching to form a transmission gate located on the semiconductor substrate. The above technical scheme has the beneficial effects of increasing the working current, improving the working speed and enhancing the responsiveness and pixel capability.
Description
Technical field
The present invention relates to CIS manufacturing technology field, particularly relate to a kind of photodiode preparation method.
Background technology
In prior art, contact-type image sensor (ContactImageSensor, CIS) is generally used in scanner, is by photosensitive unit close-packed arrays, directly collects by a kind of imageing sensor of the light information of scanning contribution reflection.
After the operation principle of CIS imageing sensor is mapped to lens by illumination in simple terms exactly, through the pinning layer (pinninglayer) of lens reflection to lower floor's surface of silicon, pinning layer and the diode layer be positioned at below pinning layer form PN junction, thus can be formed corresponding around PN junction depletion region.Under the radiation of external light source, can be equal to and apply a voltage on pinning layer, thus increase the electric charge in PN junction depletion region.And when control gate (transfergate) is opened, the electric charge being arranged in PN junction depletion region can be pulled away, to form the operating current of CIS.
In prior art, under the prerequisite not increasing design size, the area of PN junction depletion region can not be increased usually, thus larger CIS device operation current cannot be obtained, the less CIS device operation current meeting responding ability of limiting device and the pixel ability of synthetic image, and reduce the operating rate of device.
Summary of the invention
According to problems of the prior art, namely the PN junction depletion region in CIS device is large not, thus causes its operating current less, reduces the pixel ability of the operating rate of CIS device, responding ability and synthetic image, a kind of preparation method of photodiode is now provided, specifically comprises:
A kind of photodiode preparation method, is applicable to, in CIS imageing sensor preparation technology, wherein, comprising:
Step S1, provides the Semiconductor substrate that is provided with P type trap zone;
Step S2, deposits after a mask layer covers described Semiconductor substrate, etches the upper surface of described mask layer to described Semiconductor substrate, to form groove on a semiconductor substrate;
Step S3, with remaining mask layer for mask, carries out ion implantation technology to the described Semiconductor substrate that described groove exposes, in the described Semiconductor substrate of contiguous described P type trap zone, form N-type ion implanted region;
Step S4, after preparing side wall, proceeds amorphous ion injection process on the sidewall of described groove, to form amorphized areas in described N-type ion implanted region;
Step S5, the mask layer removed described side wall and be partly positioned on remaining N-type ion implanted region;
Step S6, the described Semiconductor substrate being arranged in remaining described N-type ion implanted region that etching exposes, to form groove;
Step S7, fills formation one epitaxial loayer in described groove;
Step S8, removes remaining described mask layer and the described epitaxial loayer of part, and to form a pinning layer, and etching forms the transmission grid be positioned in described Semiconductor substrate.
Preferably, this photodiode preparation method, wherein, in described step S1, before the described mask layer of formation, forms a shallow trench isolation of being filled by silicon nitride in described P type trap zone.
Preferably, this photodiode preparation method, wherein, in described step S3, after carrying out ion implantation technology, carries out annealing process to described Semiconductor substrate to described Semiconductor substrate.
Preferably, this photodiode preparation method, wherein, in described step S4, described side wall is made up of silica.
Preferably, this photodiode preparation method, wherein, in described step S5, the step removing described side wall specifically comprises:
Step S51, adopts wet etching to remove described side wall;
Step S52, adopts wet etching to remove the remaining described mask layer of part, to expand the area of the described N-type ion implanted region that described groove exposes.
Preferably, this photodiode preparation method, wherein, in described step S6, etching is carried out crystallization again to the ion of described amorphized areas, and is carried out annealing process after forming described groove.
Preferably, this photodiode preparation method, wherein, in described step S7, adopts the mode of P type ion doping or P type ion implantation to form described epitaxial loayer.
Preferably, this photodiode preparation method, wherein, in described step S1, prepares layer of oxide layer between described Semiconductor substrate and described mask layer, to isolate described mask layer and described Semiconductor substrate.
Preferably, this photodiode preparation method, wherein, described step S8 specifically comprises:
Step S81, removes described mask layer;
Step S82, removes the described epitaxial loayer of part being positioned at described oxide layer, to form described pinning layer;
Step S83, etching forms the described transmission grid being positioned at side, described N-type ion implanted region, and removes the described oxide layer being positioned at described N-type ion implanted region opposite side.
Preferably, this photodiode preparation method, is characterized in that, in described step S82, adopts CMP process to remove the described epitaxial loayer of part being positioned at described oxide layer.
The beneficial effect of technique scheme is: the area increasing PN junction depletion region, thus the operating current increasing CIS device, the operating rate of boost device, the pixel ability of enhance device responding ability and synthetic image.
Accompanying drawing explanation
Fig. 1 is in preferred embodiment of the present invention, the schematic flow sheet of a kind of photodiode preparation method;
Fig. 2 is in preferred embodiment of the present invention, on the basis of Fig. 1, and the idiographic flow schematic diagram of step S5;
Fig. 3 is in preferred embodiment of the present invention, on the basis of Fig. 1, and the idiographic flow schematic diagram of step S8;
Fig. 4-12 is in preferred embodiment of the present invention, on the basis of Fig. 1-3, and the schematic flow sheet solution of photodiode preparation method.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as limiting to the invention.
As shown in Figure 1, in preferred embodiment of the present invention, a kind of photodiode preparation method as shown in Figure 1, specifically comprises:
Step S1, provides the Semiconductor substrate that is provided with P type trap zone;
In preferred embodiment of the present invention, as shown in Figure 4, first arrange semi-conductive substrate 21, further, this Semiconductor substrate 21 is N type semiconductor substrate.
Subsequently, in preferred embodiment of the present invention, as shown in Figure 4, above-mentioned Semiconductor substrate 21 arranges a P type trap zone 22.
Further, in preferred embodiment of the present invention, as shown in Figure 4, in aforementioned p-type well region, form a shallow trench isolation 221 (shallowtrenchisolation, STI).
In preferred embodiment of the present invention, above-mentioned shallow trench isolation 221 is made up of silicon nitride (SiN).
In preferred embodiment of the present invention, above-mentioned Semiconductor substrate 21 is N-type substrate.
Step S2, deposits a mask layer and covers after Semiconductor substrate, etching mask layer to the upper surface of Semiconductor substrate, to form groove on a semiconductor substrate;
In preferred embodiment of the present invention, as shown in Figure 4, after step S1, Semiconductor substrate 21 deposits the mask layer (PhotoMask) 24 that one deck has etching pattern.
In preferred embodiment of the present invention, above-mentioned mask layer 24 is formed by nitride deposition equally.
In preferred embodiment of the present invention, as shown in Figure 4, etched portions mask layer 24, until above Semiconductor substrate 21, is positioned at groove 25 above Semiconductor substrate 21 to form one.Further, in preferred embodiment of the present invention, this groove 25 with remaining mask layer 24 for sidewall.This groove may be used for limiting the surface that Semiconductor substrate 21 is exposed to mask layer 24 outside.
In preferred embodiment of the present invention, between Semiconductor substrate 21 and mask layer 24, also comprise an oxide layer 222, for isolated p-well region 22 and mask layer 24.
Step S3, with remaining mask layer for mask, carries out ion implantation technology to the Semiconductor substrate that groove exposes, in the Semiconductor substrate of contiguous P type trap zone, form N-type ion implanted region;
In preferred embodiment of the present invention, still as shown in Figure 4, N-type ion is injected by groove 25 to Semiconductor substrate 21 inside, the N-type ion implanted region 23 subsequently through diffuseing to form as shown in Figure 4.
Further, in preferred embodiment of the present invention, as shown in Figure 4, above-mentioned N-type ion implanted region 23 is formed at the position of contiguous P type trap zone 22.
Further, in preferred embodiment of the present invention, in above-mentioned steps S3, after completing ion implantation technology, annealing process is carried out to Semiconductor substrate 21.
Step S4, after preparing side wall, proceeds amorphous ion injection process on the sidewall of groove, to form amorphized areas in N-type ion implanted region;
In preferred embodiment of the present invention, as shown in Figure 4, after over etching, mask layer 24 is physically located in the both sides of groove 25.Then as shown in Figure 5, the mask layer 24 being positioned at groove 25 both sides forms two side walls 31 respectively.
Further, in preferred embodiment of the present invention, as shown in Figure 5, above-mentioned side wall 31 is semicircular structure, and the N-type ion implanted region 23 being positioned at the Semiconductor substrate 21 that groove 25 exposes adopts above-mentioned side wall 31 to limit an injection zone 32.
Further, in preferred embodiment of the present invention, in above-mentioned injection zone 32, in N-type ion implanted region 23, inject amorphizing ion.Specifically, the mode of pre-amorphous injection (PAI) is adopted to inject amorphizing ion to N-type ion implanted region 23.In preferred embodiment of the present invention, the above-mentioned amorphizing ion being positioned at N-type ion implanted region 23 is limited with injection zone 32.Therefore, in preferred embodiment of the present invention, as shown in Figure 6, in N-type ion implanted region 23, an amorphized areas 41 is formed by above-mentioned steps.
Further, in preferred embodiment of the present invention, the amorphizing ion injecting to be formed amorphized areas 41 in advance can be silicon ion (Si) or chromium ion (Ge).
Further, in preferred embodiment of the present invention, above-mentioned side wall 31 by silica (can be silicon dioxide, SiO
2) form.
Step S5, the mask layer removed side wall and be partly positioned on remaining N-type ion implanted region;
In preferred embodiment of the present invention, above-mentioned steps S5 is concrete as shown in Figure 2, comprising:
Step S51, adopts wet etching to remove side wall;
Step S52, adopts wet etching part to remove the mask layer being positioned at both sides, described N-type ion implanted region, to expand the surface area of exposed region.
In preferred embodiment of the present invention, specifically, first adopt wet etching to remove above-mentioned side wall 31, the photoelectric diode structure after removing as shown in Figure 7.
Subsequently, in preferred embodiment of the present invention, as shown in Figure 8, adopt wet etching part to remove the mask layer 24 being positioned at both sides, N-type ion implanted region 23, increase to make the surface area of the N-type ion implanted region 23 exposed by groove 25.
Step S6, the Semiconductor substrate being arranged in remaining N-type ion implanted region that etching exposes, to form groove;
In preferred embodiment of the present invention, as shown in Figure 9, based on amorphized areas 41, in the N-type ion implanted region 23 of both sides, amorphized areas 41, etching forms groove 61 respectively.Further, in preferred embodiment of the present invention, above-mentioned groove 61 is limited with groove 25, namely can not etch in the N-type injection region 23 below mask layer 24.
In preferred embodiment of the present invention, after etching forms groove 61, crystallization again (re-crystallize) is carried out to the amorphizing ion in amorphized areas 41, and carries out annealing in process.
In preferred embodiment of the present invention, the above-mentioned groove 61 of formation, its degree of depth should be positioned at the degree of depth of N-type ion implanted region 23 slightly larger than amorphized areas 41.
Step S7, fills formation one epitaxial loayer in groove;
In preferred embodiment of the present invention, as shown in figs. 10-11, in groove 61, formation epitaxial loayer (EPILayer) 71 is filled.Epitaxial loayer 71 fills up groove 61, and protrudes from N-type ion implanted region 23, is in particular the top being positioned at amorphized areas 41.
Further, in preferred embodiment of the present invention, form epitaxial loayer 71 till protruding from above mask layer 24.
In preferred embodiment of the present invention, as shown in Figure 10, the surface of above-mentioned epitaxial loayer 71 has certain radian.
Further, in preferred embodiment of the present invention, adopt the mode of P+ ion diffuse (P+Doping) or P+ ion implantation (Implant, IMP) in groove 61, form above-mentioned epitaxial loayer 71.
In preferred embodiment of the present invention, above-mentioned epitaxial loayer 71 is made up of silicon nitride.
Step S8, removes remaining mask layer and portion of epi layer, and to form a pinning layer, and etching forms the transmission grid be positioned in Semiconductor substrate.
In preferred embodiment of the present invention, as shown in figure 11, etch away above-mentioned mask layer 24 and epitaxial loayer 71, thus form the pinning layer (PinningLayer) 81 being filled in groove 61 and being also partly positioned at above N-type ion implanted region 23.
Further, in preferred embodiment of the present invention, as shown in Figure 3, above-mentioned steps S8 specifically comprises:
Step S81, removes mask layer;
Step S82, removes the portion of epi layer being positioned at oxide layer, to form pinning layer;
Step S83, etching forms the transmission grid being positioned at side, N-type ion implanted region, and removes the oxide layer being positioned at N-type ion implanted region opposite side.
Further, in preferred embodiment of the present invention, according to above-mentioned steps, and as shown in figure 11, first remove mask layer 24, remove the epitaxial loayer 71 be exposed to above oxide layer 222 subsequently, to form a pinning layer 81.Further, in preferred embodiment of the present invention, above-mentioned pinning layer 81 is partially filled in groove 61, and part protrudes from above N-type ion implanted region 23.。
Further, in preferred embodiment of the present invention, CMP (Chemical Mechanical Polishing) process (ChemicalMechanicalPolishing, CMP) is adopted to remove above-mentioned epitaxial loayer 71, to form above-mentioned pinning layer 81.
Further, in preferred embodiment of the present invention, as shown in figure 12, above-mentioned pinning layer 81 is prepared other one deck mask layer (not shown), and etching forms the transmission grid 91 being positioned at side, N-type ion implanted region 23.
Correspondingly, in preferred embodiment of the present invention, as shown in figure 12, the oxide layer 222 being positioned at N-type ion implanted region 23 opposite side is removed.
In preferred embodiment of the present invention, retain the portion of oxide layer 222 below transmission grid 91, to isolate transmission grid 91 and Semiconductor substrate 21.
Preferably, in preferred embodiment of the present invention, as shown in figure 12, above-mentioned transmission grid 91 is positioned at the right side of N-type ion implanted region 23, therefore removes the oxide layer 222 being positioned at the left side of N-type ion implanted region 23.
In preferred embodiment of the present invention, because the contact-making surface now between pinning layer 81 and N-type ion implanted region 23 is curved surface, larger than the area of flat contact surface of the prior art, and through the process of above-mentioned steps S52, the area of N-type ion implanted region 23 itself is increased, thus increases the area (contact area namely between pinning layer 81 and N-type ion implanted region 23) of the PN junction depletion region of photodiode.Therefore the present invention can realize when the design size of not increased device, the operating current increasing when promoting CIS devices function by making the contact area between pinning layer and N-type ion implanted region, thus accelerate CIS device operating rate, strengthen the responding ability of CIS device and the pixel ability of synthetic image.
The foregoing is only preferred embodiment of the present invention; not thereby embodiments of the present invention and protection range is limited; to those skilled in the art; should recognize and all should be included in the scheme that equivalent replacement done by all utilizations specification of the present invention and diagramatic content and apparent change obtain in protection scope of the present invention.
Claims (10)
1. a photodiode preparation method, is applicable to, in CIS imageing sensor preparation technology, it is characterized in that, comprising:
Step S1, provides the Semiconductor substrate that is provided with P type trap zone;
Step S2, deposits after a mask layer covers described Semiconductor substrate, etches the upper surface of described mask layer to described Semiconductor substrate, to form groove on a semiconductor substrate;
Step S3, with remaining mask layer for mask, carries out ion implantation technology to the described Semiconductor substrate that described groove exposes, in the described Semiconductor substrate of contiguous described P type trap zone, form N-type ion implanted region;
Step S4, after preparing side wall, proceeds amorphous ion injection process on the sidewall of described groove, to form amorphized areas in described N-type ion implanted region;
Step S5, the mask layer removed described side wall and be partly positioned on remaining N-type ion implanted region;
Step S6, the described Semiconductor substrate being arranged in remaining described N-type ion implanted region that etching exposes, to form groove;
Step S7, fills formation one epitaxial loayer in described groove;
Step S8, removes remaining described mask layer and the described epitaxial loayer of part, and to form a pinning layer, and etching forms the transmission grid be positioned in described Semiconductor substrate.
2. photodiode preparation method as claimed in claim 1, is characterized in that, in described step S1, before the described mask layer of formation, forms a shallow trench isolation of being filled by silicon nitride in described P type trap zone.
3. photodiode preparation method as claimed in claim 1, is characterized in that, in described step S3, after carrying out ion implantation technology, carry out annealing process to described Semiconductor substrate to described Semiconductor substrate.
4. photodiode preparation method as claimed in claim 1, it is characterized in that, in described step S4, described side wall is made up of silica.
5. photodiode preparation method as claimed in claim 1, it is characterized in that, in described step S5, the step removing described side wall specifically comprises:
Step S51, adopts wet etching to remove described side wall;
Step S52, adopts wet etching to remove the remaining described mask layer of part, to expand the area of the described N-type ion implanted region that described groove exposes.
6. photodiode preparation method as claimed in claim 1, is characterized in that, in described step S6, etching is carried out crystallization again to the ion of described amorphized areas, and carried out annealing process after forming described groove.
7. photodiode preparation method as claimed in claim 1, is characterized in that, in described step S7, adopts the mode of P type ion doping or P type ion implantation to form described epitaxial loayer.
8. photodiode preparation method as claimed in claim 1, is characterized in that, in described step S1, between described Semiconductor substrate and described mask layer, prepare layer of oxide layer, to isolate described mask layer and described Semiconductor substrate.
9. photodiode preparation method as claimed in claim 8, it is characterized in that, described step S8 specifically comprises:
Step S81, removes described mask layer;
Step S82, removes the described epitaxial loayer of part being positioned at described oxide layer, to form described pinning layer;
Step S83, etching forms the described transmission grid being positioned at side, described N-type ion implanted region, and removes the described oxide layer being positioned at described N-type ion implanted region opposite side.
10. photodiode preparation method as claimed in claim 9, is characterized in that, in described step S82, adopts CMP process to remove the described epitaxial loayer of part being positioned at described oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410459546.3A CN105405918B (en) | 2014-09-10 | 2014-09-10 | A kind of photodiode preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410459546.3A CN105405918B (en) | 2014-09-10 | 2014-09-10 | A kind of photodiode preparation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105405918A true CN105405918A (en) | 2016-03-16 |
| CN105405918B CN105405918B (en) | 2017-06-06 |
Family
ID=55471296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410459546.3A Active CN105405918B (en) | 2014-09-10 | 2014-09-10 | A kind of photodiode preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105405918B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994044A (en) * | 2017-12-15 | 2018-05-04 | 上海华力微电子有限公司 | Cmos image sensor and preparation method thereof |
| CN109119507A (en) * | 2018-09-05 | 2019-01-01 | 南京大学 | A kind of graphene infrared detector preparation method based on integrated circuit technology |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5880495A (en) * | 1998-01-08 | 1999-03-09 | Omnivision Technologies, Inc. | Active pixel with a pinned photodiode |
| US20040262646A1 (en) * | 2003-06-16 | 2004-12-30 | Inna Patrick | Pixel design to maximize photodiode capacitance and method of forming same |
| US20050051702A1 (en) * | 2003-09-08 | 2005-03-10 | Hong Sungkwon Chris | Image sensor with photo diode gate |
| US20050151218A1 (en) * | 2004-01-12 | 2005-07-14 | Chandra Mouli | Using high-k dielectrics in isolation structures method, pixel and imager device |
| US20080079043A1 (en) * | 2006-09-29 | 2008-04-03 | Mi Jin Kim | Light sensing pixel of image sensor with low operating voltage |
| CN103346161A (en) * | 2013-06-24 | 2013-10-09 | 上海华力微电子有限公司 | Method for improving picture signal quality of overlapping backside illuminated CMOS imaging sensor |
-
2014
- 2014-09-10 CN CN201410459546.3A patent/CN105405918B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5880495A (en) * | 1998-01-08 | 1999-03-09 | Omnivision Technologies, Inc. | Active pixel with a pinned photodiode |
| US20040262646A1 (en) * | 2003-06-16 | 2004-12-30 | Inna Patrick | Pixel design to maximize photodiode capacitance and method of forming same |
| US20050051702A1 (en) * | 2003-09-08 | 2005-03-10 | Hong Sungkwon Chris | Image sensor with photo diode gate |
| US20050151218A1 (en) * | 2004-01-12 | 2005-07-14 | Chandra Mouli | Using high-k dielectrics in isolation structures method, pixel and imager device |
| US20080079043A1 (en) * | 2006-09-29 | 2008-04-03 | Mi Jin Kim | Light sensing pixel of image sensor with low operating voltage |
| CN103346161A (en) * | 2013-06-24 | 2013-10-09 | 上海华力微电子有限公司 | Method for improving picture signal quality of overlapping backside illuminated CMOS imaging sensor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994044A (en) * | 2017-12-15 | 2018-05-04 | 上海华力微电子有限公司 | Cmos image sensor and preparation method thereof |
| CN109119507A (en) * | 2018-09-05 | 2019-01-01 | 南京大学 | A kind of graphene infrared detector preparation method based on integrated circuit technology |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105405918B (en) | 2017-06-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5389317B2 (en) | Image sensor and manufacturing method thereof | |
| KR100657143B1 (en) | Image sensor, and method for fabricating the same | |
| US8440540B2 (en) | Method for doping a selected portion of a device | |
| CN104517976A (en) | CMOS (complementary metal oxide semiconductor) image sensor pixel structure and forming method thereof | |
| CN106783899A (en) | A kind of method for reducing cmos image sensor dark current | |
| CN104505394A (en) | Compatible ranging CMOS (Complementary Metal Oxide Semiconductor) image sensor pixel unit and manufacturing method thereof | |
| CN109950268A (en) | PDAF imaging sensor and forming method thereof | |
| CN105185747A (en) | Integrated technology of reducing CMOS image sensor white pixels | |
| KR101030300B1 (en) | Method for fabricating of CMOS Image sensor | |
| CN109244097A (en) | Imaging sensor and forming method thereof | |
| CN101599499A (en) | The dot structure of non-image lag CMOS image sensor and manufacture method | |
| CN108899335A (en) | Back side illumination image sensor and preparation method thereof | |
| CN105405918A (en) | Method for preparing photodiode | |
| CN104201182B (en) | A kind of back side illumination image sensor pixel and preparation method thereof | |
| JP2012049466A5 (en) | ||
| CN109817651A (en) | The forming method of imaging sensor, semiconductor structure | |
| CN103413816B (en) | Dot structure of cmos image sensor and forming method thereof | |
| CN108258004A (en) | Imaging sensor and forming method thereof | |
| CN104332481B (en) | Imaging sensor and forming method thereof | |
| CN107195646B (en) | Image sensor and manufacturing method thereof | |
| CN106257646B (en) | It is embedded in the CMOS production method of PIP capacitor | |
| KR100654056B1 (en) | Image sensor and method for manufacturing the same | |
| CN204179082U (en) | A kind of back side illumination image sensor dot structure | |
| KR100850859B1 (en) | Image Sensor and The Fabricating Method thereof | |
| CN108281442A (en) | Imaging sensor and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |