CN105632888A - Removing method of native oxide layer of FinFet device before source-drain epitaxy - Google Patents
Removing method of native oxide layer of FinFet device before source-drain epitaxy Download PDFInfo
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- CN105632888A CN105632888A CN201410601931.7A CN201410601931A CN105632888A CN 105632888 A CN105632888 A CN 105632888A CN 201410601931 A CN201410601931 A CN 201410601931A CN 105632888 A CN105632888 A CN 105632888A
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- natural oxidizing
- oxide layer
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Abstract
The invention provides a removing method of a native oxide layer of a FinFet device before source-drain epitaxy. The method comprises the steps: performing RCA cleaning, and removing the native oxide layer through diluted BOE solution wet etching. According to the removing method, a stable etching rate is easy to maintain. The native oxide layer is effectively removed, loss of other area medium layers is reduced at the same time, and a mushroom defect in a subsequent selectivity epitaxial process is prevented from generation at the same time.
Description
Technical field
The present invention relates to field of semiconductor device preparation, particularly to the minimizing technology of natural oxidizing layer before a kind of FinFet device source and drain extension.
Background technology
Fin-FET is the transistor with fin channel structure, and it utilizes several surfaces of thin fin as raceway groove, such that it is able to prevent the short-channel effect in conventional transistor, can increase operating current simultaneously.
At present, in the device fabrication of FinFet, in order to increase the mobility of carrier to meet the requirement of device speed, in the source and drain areas of NMOS and PMOS transistor, generally introduce different materials, so that pressure is introduced raceway groove. Common practice is, for PMOS device, the source and drain areas Epitaxial growth at fin goes out the stressor layers of SiGe, and owing to SiGe lattice paprmeter is more than Si, therefore channel region can be applied pressure by this stressor layers; For nmos device, the source and drain areas Epitaxial growth at fin goes out the stressor layers of Si:C, and owing to the lattice paprmeter of Si:C is less than Si, therefore channel region is provided tension force by this stressor layers.
Epitaxy technique is the method growing the strain gauge materials such as SiGe, Ge, SiC, GeSn on semi-conducting material. In the source-drain area epitaxy technique of FinFet, it is selective epitaxial stress thin film on the source and drain areas of fin, before carrying out extension, it is necessary to the natural oxidizing layer of epi region (the Si region of exposure) is removed.
At present, before the source-drain area epitaxy technique of FinFet, HF-last is adopted to process technique, namely, before entering epitaxial reaction chamber room, silicon chip is positioned in the HF dilute solution of certain proportioning, erosion removal natural oxidizing layer, then with deionized water rinsing and dry, and quickly put into reaction chamber and carry out epitaxy technique.
But, remove in the technique of natural oxidizing layer, with reference to shown in Fig. 1 and Fig. 3, the region being exposed to has: the silicon nitride material side wall (spacer) 110 of 3-D solid structure, the SiO that top portions of gates plasma enhancing (PE) deposits2Mask layer 109 (Fig. 1 is not shown), the shallow trench of high compactness isolates 104 silicon dioxide (STISiO2) and the source-drain area at SiFin102 two ends. Process in technique at HF-last, usually by controlling etch period, thoroughly remove natural oxidizing layer, if but problematically, rinsing time is too short, will improve epitaxy technique heat budget; If rinsing time is long, the loss that can make side wall 110 and mask layer 109 is too much so that grid 108 exposes, and can form the defect of " mushroom (mushroom) " 120 in selective epitaxial process, with reference to shown in Fig. 3, in turn result in the inefficacy of device.
Summary of the invention
In view of this, the invention provides the minimizing technology of natural oxidizing layer before a kind of FinFet device source and drain extension, effectively remove natural oxidizing layer, reduce defect and produce.
The minimizing technology of natural oxidizing layer before the source and drain extension of a kind of FinFet device, including step:
Carry out RCA cleaning;
Natural oxidizing layer is removed with the BOE solution wet etching of dilution.
Optionally, after carrying out the removal of natural oxidizing layer, further comprise the steps of: with high-purity H2Or N2Or noble gas carries out the purging of wafer and dries.
Optionally, the BOE solution of dilution is by the BOE reagent dilutions of 7:1.
Optionally, the ratio being diluted is 1/20.
Optionally, etching time is 60s.
Optionally, the ratio being diluted is 1/10,1/30 or 1/40.
Optionally, the step carrying out RCA cleaning includes: carry out the cleaning of SPM and SC2.
The minimizing technology of natural oxidizing layer before FinFet device source and drain extension provided by the invention, adopts the mode of the BOE wet etching of dilution, carries out the removal of natural oxidizing layer, the Etch selectivity that silicon nitride spacer has been had by this solution, and the NH in solution4F composition can control pH-value, and the shortage of supplementary F ion, so maintains stable etch rate, effectively removes while natural oxidizing layer, reduce the loss of other Region Medium layer, it is to avoid the generation of " mushroom " defect in subsequent selective epitaxial process. Additionally containing more H ion in solution, in fin surface adsorption after corrosion, it is suppressed that the fast-growth of natural oxidizing layer after rinsing.
Accompanying drawing explanation
Fig. 1 is the structural representation before FinFet device source and drain extension;
Fig. 2 is the structural representation after FinFet device source and drain extension;
Fig. 3 is the schematic cross-section of the FinFet device producing " mushroom " defect in prior art;
Fig. 4 is the flow chart of the minimizing technology of natural oxidizing layer before the FinFet device source and drain extension according to the present invention.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of invention, feature and advantage to become apparent from, below the specific embodiment of the present invention is described in detail.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention can also adopt other to be different from alternate manner described here to be implemented, those skilled in the art can do similar popularization when without prejudice to intension of the present invention, and therefore the present invention is not by the restriction of following public specific embodiment.
Providing the minimizing technology of natural oxidizing layer before a kind of FinFet device source and drain extension in the present invention, namely before needs carry out source and drain epitaxy technique, remove the natural oxidizing layer on the surface of the fin exposed, common, in this step, device includes: fin; Isolation between fin; Grid on fin; Side wall on gate lateral wall; And, the mask layer at the top of fin. Now, the two ends of fin are the formation region of source and drain, in subsequent steps, it is necessary to carry out selective epitaxial at this source and drain areas, to strengthen the stress effect of raceway groove, before this, it is necessary to got rid of by the natural oxidizing layer of source and drain areas silicon face.
In order to be better understood from technical scheme and technique effect, it is described in detail below with reference to flow chart 1 and specific embodiment.
Before carrying out the removal of natural oxidizing layer, first, it is provided that FinFet device architecture, with reference to shown in Fig. 1.
In the present embodiment, as shown in Figure 1, concrete, first, substrate 100 is provided, substrate 100 can be Si substrate, Ge substrate, SiGe substrate, SOI (silicon-on-insulator, SiliconOnInsulator) or GOI (germanium on insulator, GermaniumOnInsulator) etc. In other embodiments, described Semiconductor substrate can also be the substrate including other elemental semiconductors or compound semiconductor, such as GaAs, InP or SiC etc., it can also be laminated construction, such as Si/SiGe etc., other epitaxial structures all right, for instance SGOI (silicon germanium on insulator) etc. In the present embodiment, substrate 100 is body silicon substrate.
Then, lithographic technique is adopted, for instance the method for RIE (reactive ion etching), etched substrate 100 forms fin 102.
Then, being filled with the isolated material of silicon dioxide, and carry out flatening process, it is possible to use wet etching, use the certain thickness isolated material of Fluohydric acid. erosion removal, the isolated material of member-retaining portion is between fin 102, thus defining isolation 104.
Then, deposit gate dielectric material and grid material respectively, gate dielectric material can be thermal oxide layer or high K medium material, high K medium material such as hafnio oxide, HFO2, HfSiO, HfSiON, HfTaO, HfTiO etc., grid material can include metal gates or polysilicon, for instance may include that Ti, TiAlx��TiN��TaNx��HfN��TiCx��TaCx��HfCx��Ru��TaNx��TiAlN��WCN��MoAlN��RuOx, polysilicon or other suitable materials, or their combination. Then, deposit mask layer (not shown go out), such as the mask layer of the silicon dioxide of plasma enhancing (PE), and perform etching, be formed across gate dielectric layer 106 and the grid 108 of fin 102. Finally, it is possible to by deposit silicon nitride, then carry out RIE (reactive ion etching), thus forming the side wall 110 of silicon nitride.
So, the device architecture before FinFet device source and drain extension it is the formation of.
Then, it is possible to carry out the removal of natural oxidizing layer before FinFet device source and drain extension.
First, in step S01, carry out RCA cleaning.
In this step, carry out RCA cleaning, to remove staining of wafer surface. In the present embodiment, first carry out SC1 (or claim APM, H2SO4/H2O2/H2O) clean, to remove staining of wafer surface carbon containing, such as organic residue etc.; Then, removing the oxide that the strong oxidizer in SC1 solution is formed in HF (DHF) solution of dilution, rinsing time depends on the concentration of HF solution, and rinsing time is less than 10s in one embodiment; Then, SC2 (HCl/H is carried out2O2/H2O) cleaning, to remove the metallic of wafer surface trace, and it is dry to carry out drying.
Then, in step S02, natural oxidizing layer is removed with the BOE solution wet etching of dilution.
In the present embodiment, Selection parameter is the BOE reagent of 7:1, and dilution ratio is 1/20, i.e. the BOE reagent of the 7:1 of 1 volume, the high purity water (deionized water) adding 20 volumes is diluted, and the time that the solution after dilution carries out corroding can set that as 60s. Under this proportioning, the removal amount of natural oxidizing layer is right at 50 Izods, maintains stable etch rate, and the loss of other Region Medium layer is less.
In other embodiments, dilution ratio and etching time can be changed to reach identical removal amount, as still Selection parameter is the BOE reagent of 7:1, dilution ratio can be 1/10,1/30 or 1/40, reduces accordingly or increases etching time, to remove natural oxidizing layer, simultaneously as containing more H ion in solution, the source drain region surface at fin adsorbs, form the passivation layer of hydrogen bond, it is suppressed that the fast-growth of natural oxidizing layer after rinsing.
After corroding, it is also possible to the purging carrying out wafer with noble gas dries, for instance with substantial amounts of high-purity H2Or N2Or the inert gas purge wafer surface such as Ar, with starvation, playing suppression native oxide layer and again generate, high-purity gas refers to that in gas, oxygen content is less than 1ppb herein.
Then, it is possible to carry out source and drain epitaxial growth, form the epitaxial layer 112 of source-drain area, with reference to shown in Fig. 2.
In one embodiment, it is possible to carry out the selective epitaxial growth of SiGe or Si:C, grow epitaxial layer with the source and drain areas at the two ends at fin, to strengthen the stress effect of raceway groove, improve the carrier mobility of device.
The minimizing technology of the natural oxidizing layer of the present invention, effectively removes the natural oxidizing layer of fin source drain region surface, decrease the loss of other Region Medium material, efficiently avoid the generation of mushroom in source-drain area selective epitaxial growth process, it is to avoid the inefficacy of device.
Although the present invention is described in conjunction with above example, but the present invention is not limited to above-described embodiment, and it being only limited by the restriction of claims, it easily can be modified and change by those of ordinary skill in the art, but and without departing from the essential idea of the present invention and scope.
Claims (7)
1. the minimizing technology of natural oxidizing layer before a FinFet device source and drain extension, it is characterised in that include step:
Carry out RCA cleaning;
Natural oxidizing layer is removed with the BOE solution wet etching of dilution.
2. minimizing technology according to claim 1, it is characterised in that after carrying out the removal of natural oxidizing layer, further comprises the steps of: with high-purity H2Or N2Or noble gas carries out the purging of wafer and dries.
3. minimizing technology according to claim 1, it is characterised in that the BOE solution of dilution is by the BOE reagent dilutions of 7:1.
4. minimizing technology according to claim 3, it is characterised in that the ratio being diluted is 1/20.
5. minimizing technology according to claim 4, it is characterised in that etching time is 60s.
6. minimizing technology according to claim 3, it is characterised in that the ratio being diluted is 1/10,1/30 or 1/40.
7. minimizing technology according to claim 1, it is characterised in that the step carrying out RCA cleaning includes: carry out the cleaning of HF and the SC2 of SC1, dilution.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112382555A (en) * | 2020-11-12 | 2021-02-19 | 广东先导先进材料股份有限公司 | Method for cleaning indium phosphide substrate |
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Patent Citations (7)
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| US20020176984A1 (en) * | 2001-03-26 | 2002-11-28 | Wilson Smart | Silicon penetration device with increased fracture toughness and method of fabrication |
| US20040150029A1 (en) * | 2003-02-04 | 2004-08-05 | Lee Jong-Ho | Double-gate FinFET device and fabricating method thereof |
| CN101191252A (en) * | 2006-11-20 | 2008-06-04 | 上海华虹Nec电子有限公司 | Method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth |
| US20130178031A1 (en) * | 2007-05-25 | 2013-07-11 | Cypress Semiconductor Corporation | Integration of non-volatile charge trap memory devices and logic cmos devices |
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