CN106647914A - Linear voltage regulator - Google Patents
Linear voltage regulator Download PDFInfo
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- CN106647914A CN106647914A CN201710068638.2A CN201710068638A CN106647914A CN 106647914 A CN106647914 A CN 106647914A CN 201710068638 A CN201710068638 A CN 201710068638A CN 106647914 A CN106647914 A CN 106647914A
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- Prior art keywords
- nmos tube
- circuit
- pmos
- difference
- grid
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
The invention discloses a linear voltage regulator which comprises an error amplifier, a voltage regulation component, a feedback network and an accelerating starting circuit, wherein the accelerating starting circuit comprises a first part circuit, a second part circuit and a first switch; the first part circuit and the second part circuit are respectively mirror image circuits for a first difference active load and tail current of the error amplifier and are connected with a current comparator; on the basis of the characteristics that the current of the first difference active load can gradually decrease till reaching a stable value in a starting process but the tail current is kept constant, the current comparator formed by the two mirror image circuits can switch on the first switch in the starting process and quickly increase the voltage at a control end of the voltage regulation component, so that the starting speed can be increased; after the starting is ended, the first switch is switched off and the voltage regulation component is not influenced. The linear voltage regulator can increase the starting speed and can maintain the performance of the linear voltage regulator after the starting is ended.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of linear voltage regulator.
Background technology
Linear voltage regulator is widely used in integrated circuits, as shown in figure 1, being the circuit diagram of existing linear voltage regulator；
Existing linear voltage regulator includes error amplifier, Voltage Cortrol device and feedback network.
Error amplifier includes the amplifier body being made up of NMOS tube MN1, MN2, MN3 and MN4, and amplifier body is
The differential amplifier arrangements of cascade, PMOS MP1, MP2, MP3 and MP4 composition active load, NMOS tube MN5 composition tail electricity
Stream source；Bias voltage VB1 is connected to the grid of NMOS tube MN5, and bias voltage VB2 is connected to the grid of NMOS tube MN2 and MN4,
Bias voltage VB3 is connected to the grid of PMOS MP2 and MP4, and bias voltage VB4 is connected to the grid of PMOS MP1 and MP3.
Voltage Cortrol device is made up of NMOS tube MDRV, the source electrode of NMOS tube MDRV as output voltage OUT output end,
Feedback network is connected by resistance R1 and R2 and is formed.The grid of NMOS tube MN1 meets reference voltage VREF, and the grid of NMOS tube MN2 connects
The feedback voltage formed by resistance R1 and R2 partial pressure.
The comparison that existing linear voltage regulator passes through feedback voltage and reference voltage, adjusts the unlatching size of NMOS tube MDRV,
So as to maintain stablizing for output voltage OUT when output current changes.
Although existing linear voltage regulator can realize the output of burning voltage, when upper electric, can there is DC operation
The slower problem of setup time of point.
The content of the invention
The technical problem to be solved is to provide a kind of linear voltage regulator, can improve toggle speed.
To solve above-mentioned technical problem, the linear voltage regulator that the present invention is provided includes：Error amplifier, Voltage Cortrol device
And feedback network.
The error amplifier includes amplifier body, tail current source and active load.
The amplifier body is differential configuration and including first difference channel and second difference channel, described first
The source of the source of individual difference channel and second difference channel all connects the tail current source, and the active load includes
The first difference active load and the second difference active load of mirror image each other, the first difference active load connection described first
The load end of individual difference channel, the second difference active load connects the load end of second difference channel；Described
The input connection reference voltage of one difference channel, the input of second difference channel connects the feedback network output
Feedback voltage；The load end of second difference channel also exports the first control signal and adjusts to the voltage as output end
The control end of whole device.
The linear voltage regulator also includes the acceleration start-up circuit for accelerating linear voltage regulator to start, and the acceleration starts
Circuit includes Part I circuit, Part II circuit and first switch.
The Part I circuit is the mirror image circuit of the first difference active load, and the Part II circuit is institute
The mirror image circuit of tail current source is stated, the Part I circuit is connected and constitutes electric current and compares with the Part II circuit
Device, the output end of the current comparator is connected to the control end of the first switch.
The electric current of the first difference active load described in the size of current of the tail current source and second difference are active negative
The sum of the electric current of load；When the linear voltage regulator is stable, the electric current of the first difference active load and second difference have
The electric current of source load is equal.
In the linear voltage regulator start-up course, the electric current of the first difference active load has more than second difference
The electric current of source load, and the electric current of the first difference active load gradually drops from the size of electric current equal to the tail current source
It is low to stablize when value, the curent change of the curent change mode of the Part I circuit and the first difference active load
Mode is consistent, and the electric current of the Part II circuit keeps the size of current of constant and described Part II circuit to be set to start
During the Part I circuit electric current maximum and the median of minimum of a value so that start the incipient stage described in second
The electric current of partial circuit is more than the electric current of the Part I circuit so that current comparator output first voltage value；
Startup terminates the electric current of the rear Part II circuit and is less than the electric current of the Part I circuit so that the electric current compares
Device exports second voltage value.
The first switch is connected between supply voltage and first control signal, when current comparator output
During the first voltage value, the first switch conducting makes first control signal connect the supply voltage so that described
First control signal rapid increase starts so as to accelerate the linear voltage regulator；When current comparator output it is described second electric
During pressure value, the first switch disconnects, so that described accelerate start-up circuit not produce shadow to the output of the linear voltage regulator
Ring.
Further improvement is that first difference channel and second difference channel are all cascade amplification
Circuit.
Further improvement is that first difference channel includes the first NMOS tube and the second NMOS tube, the amplification
Second difference channel of device body includes the 3rd NMOS tube and the 4th NMOS tube.
The source electrode of the source electrode of first NMOS tube and the 3rd NMOS tube is connected together as the amplifier sheet
The source of two difference channels of body.
The source electrode of drain electrode connection second NMOS tube of first NMOS tube, the drain electrode conduct of second NMOS tube
The load end of first difference channel.
The source electrode of drain electrode connection the 4th NMOS tube of the 3rd NMOS tube, the drain electrode conduct of the 4th NMOS tube
The load end and the output end as the amplifier body of second difference channel.
Input of the grid of first NMOS tube as first difference channel.
Input of the grid of the 3rd NMOS tube as second difference channel.
The grid of second NMOS tube connects the grid of the 4th NMOS tube and all connects the second bias voltage.
Further improvement be, the first difference active load includes the first PMOS and the second PMOS, described the
Two difference active loads include the 3rd PMOS and the 4th PMOS.
The source electrode of the source electrode of first PMOS and the 3rd PMOS all connects supply voltage.
The source electrode of drain electrode connection second PMOS of first PMOS, the drain electrode connection of the 3rd PMOS
The source electrode of the 4th PMOS.
The grid of first PMOS, the drain electrode of the grid and second PMOS of the 3rd PMOS all connect
The drain electrode of second NMOS tube.
The drain electrode of drain electrode connection the 4th NMOS tube of the 4th PMOS.
The grid of the grid of second PMOS and the 4th PMOS all connects the 3rd bias voltage.
Further improvement is that the tail current source includes the 5th NMOS tube, the source ground of the 5th NMOS tube, institute
The source electrode of drain electrode connection first NMOS tube of the 5th NMOS tube is stated, the grid of the 5th NMOS tube connects the first biased electrical
Pressure.
Further improvement be, the Part I circuit includes the 5th PMOS and the 6th PMOS, the described 5th
The source electrode of PMOS connects supply voltage, and draining for the 5th PMOS connects the source electrode of the 6th PMOS, and the described 5th
The grid of PMOS connects the grid of first PMOS, and the grid of the 6th PMOS connects second PMOS
Grid, the drain electrode of the 6th PMOS connects the Part II circuit.
Further improvement be, the Part II circuit includes the 6th NMOS tube and the 7th NMOS tube, the described 6th
The source ground of NMOS tube, the grid of the 6th NMOS tube and the grid connection of the 5th NMOS tube.
The source electrode of the 7th NMOS tube connects the drain electrode of the 6th NMOS tube, the grid of the 7th NMOS tube and institute
State the grid connection of the first NMOS tube.
The drain electrode of the 7th NMOS tube connects the Part I circuit.
Further improvement is that the Voltage Cortrol device includes the 8th NMOS tube, and the drain electrode of the 8th NMOS tube connects
Supply voltage is connect, the grid of the 8th NMOS tube connects the drain electrode of the 4th NMOS tube, the source electrode of the 8th NMOS tube
As the output end of the linear voltage regulator.
Further improvement is that the feedback network is by the electricity being connected between the output end of the linear voltage regulator and ground
Resistance string composition.
Further improvement is that the first switch is made up of the 9th NMOS tube, and the grid of the 9th NMOS tube is institute
State the control end of first switch, the drain electrode connection supply voltage of the 9th NMOS tube, the source electrode connection of the 9th NMOS tube
First control signal.
Further improvement is that the electric current of the Part I circuit is equal to the electric current of the first difference active load.
Further improvement is that the size ratio of the electric current of the Part II circuit and the electric current of the tail current source is
3：4.
The acceleration start-up circuit of the present invention can be in power up, can be from being equal to using the electric current of the first difference active load
The feature of the value when size of the electric current of tail current source is gradually lowered to stablize, by the current mirror of mirror image the first difference active load
As in Part I circuit, so that the electric current of Part I circuit also can be with active in the first difference in power up
The electric current of load and change, so by existing by the electric current of Part I circuit and size of current, for Part I circuit
The electric current of the electric current of the Part II circuit of the median of electric current is compared during upper Electrical change, and compared by electric current
As a result controlling the break-make of first switch, so as to realize enabling the first control signal of the control end for being input to Voltage Cortrol device
Rapid increase and impact of the releasing acceleration start-up circuit to the first control signal after startup terminates on startup, so this
The bright toggle speed that can realize linear voltage regulator, and maintained the performance of linear voltage regulator after startup terminates.
Description of the drawings
With reference to the accompanying drawings and detailed description the present invention is further detailed explanation：
Fig. 1 is the circuit diagram of existing linear voltage regulator；
Fig. 2 is the circuit diagram of present pre-ferred embodiments linear voltage regulator；
Fig. 3 is the size of current schematic diagram of present pre-ferred embodiments linear voltage regulator each branch road when starting and being stable；
Fig. 4 is the startup simulation curve of present pre-ferred embodiments and existing linear voltage regulator.
Specific embodiment
Embodiment of the present invention linear voltage regulator includes：Error amplifier, Voltage Cortrol device and feedback network.
The error amplifier includes amplifier body, tail current source and active load.
The amplifier body is differential configuration and including first difference channel and second difference channel, described first
The source of the source of individual difference channel and second difference channel all connects the tail current source, and the active load includes
The first difference active load and the second difference active load of mirror image each other, the first difference active load connection described first
The load end of individual difference channel, the second difference active load connects the load end of second difference channel；Described
The input connection reference voltage of one difference channel, the input of second difference channel connects the feedback network output
Feedback voltage；The load end of second difference channel also exports the first control signal and adjusts to the voltage as output end
The control end of whole device.
The linear voltage regulator also includes the acceleration start-up circuit for accelerating linear voltage regulator to start, and the acceleration starts
Circuit includes Part I circuit, Part II circuit and first switch.
The Part I circuit is the mirror image circuit of the first difference active load, and the Part II circuit is institute
The mirror image circuit of tail current source is stated, the Part I circuit is connected and constitutes electric current and compares with the Part II circuit
Device, the output end of the current comparator is connected to the control end of the first switch.
The electric current of the first difference active load described in the size of current of the tail current source and second difference are active negative
The sum of the electric current of load；When the linear voltage regulator is stable, the electric current of the first difference active load and second difference have
The electric current of source load is equal.
In the linear voltage regulator start-up course, the electric current of the first difference active load has more than second difference
The electric current of source load, and the electric current of the first difference active load gradually drops from the size of electric current equal to the tail current source
It is low to stablize when value, the curent change of the curent change mode of the Part I circuit and the first difference active load
Mode is consistent, and the electric current of the Part II circuit keeps the size of current of constant and described Part II circuit to be set to start
During the Part I circuit electric current maximum and the median of minimum of a value so that start the incipient stage described in second
The electric current of partial circuit is more than the electric current of the Part I circuit so that current comparator output first voltage value；
Startup terminates the electric current of the rear Part II circuit and is less than the electric current of the Part I circuit so that the electric current compares
Device exports second voltage value.
The first switch is connected between supply voltage and first control signal, when current comparator output
During the first voltage value, the first switch conducting makes first control signal connect the supply voltage so that described
First control signal rapid increase starts so as to accelerate the linear voltage regulator；When current comparator output it is described second electric
During pressure value, the first switch disconnects, so that described accelerate start-up circuit not produce shadow to the output of the linear voltage regulator
Ring.
As shown in Fig. 2 being the circuit diagram of present pre-ferred embodiments linear voltage regulator；In present pre-ferred embodiments：
First difference channel and second difference channel are all cascade amplifying circuit.
First difference channel includes the first NMOS tube MN1 and the second NMOS tube MN2, the of the amplifier body
Two difference channels include the 3rd NMOS tube MN3 and the 4th NMOS tube MN4.
The source electrode of the source electrode of first NMOS tube MN1 and the 3rd NMOS tube MN3 is connected together as described putting
The source of two difference channels of big device body.
The source electrode of drain electrode connection second NMOS tube MN2 of first NMOS tube MN1, second NMOS tube MN2
Drain electrode as first difference channel load end.
The source electrode of drain electrode connection the 4th NMOS tube MN4 of the 3rd NMOS tube MN3, the 4th NMOS tube MN4
Drain electrode as second difference channel load end and the output end as the amplifier body.
Input of the grid of first NMOS tube MN1 as first difference channel.
Input of the grid of the 3rd NMOS tube MN3 as second difference channel.
The grid of second NMOS tube MN2 connects the grid of the 4th NMOS tube MN4 and all connects the second bias voltage
VB2。
The first difference active load includes the first PMOS MP1 and the second PMOS MP2, and second difference is active
Load includes the 3rd PMOS MP3 and the 4th PMOS MP4.
The source electrode of the source electrode of first PMOS MP1 and the 3rd PMOS MP3 all meets supply voltage VDD.
The source electrode of drain electrode connection second PMOS MP2 of first PMOS MP1, the 3rd PMOS MP3
Drain electrode connection the 4th PMOS MP4 source electrode.
The grid of first PMOS MP1, the grid of the 3rd PMOS MP3 and second PMOS MP2
Drain electrode all connects the drain electrode of second NMOS tube MN2 and connects the 4th bias voltage VB4.
The drain electrode of drain electrode connection the 4th NMOS tube MN4 of the 4th PMOS MP4.
The grid of the grid of second PMOS MP2 and the 4th PMOS MP4 all connects the 3rd bias voltage
VB3。
The tail current source include the 5th NMOS tube MN5, the source ground of the 5th NMOS tube MN5, the described 5th
The source electrode of drain electrode connection first NMOS tube MN1 of NMOS tube MN5, the grid connection first of the 5th NMOS tube MN5 is inclined
Put voltage VB1.
The Part I circuit includes the 5th PMOS MPa1 and the 6th PMOS MPa2, the 5th PMOS MPa1
Source electrode meet supply voltage VDD, the source electrode of drain electrode connection the 6th PMOS MPa2 of the 5th PMOS MPa1 is described
The grid of the 5th PMOS MPa1 connects the grid of first PMOS MP1, the grid connection of the 6th PMOS MPa2
The grid of second PMOS MP2, the drain electrode of the 6th PMOS MPa2 connects the Part II circuit.
The Part II circuit includes the 6th NMOS tube MNa1 and the 7th NMOS tube MNa2, the 6th NMOS tube MNa1
Source ground, the grid connection of the grid of the 6th NMOS tube MNa1 and the 5th NMOS tube MN5.
The source electrode of the 7th NMOS tube MNa2 connects the drain electrode of the 6th NMOS tube MNa1, the 7th NMOS tube
The grid connection of the grid of MNa2 and first NMOS tube MN1.
The drain electrode of the 7th NMOS tube MNa2 connects the Part I circuit.Understand as shown in Figure 2, the described 7th
The drain electrode of NMOS tube MNa2 and the drain electrode of the 6th PMOS MPa2 connect.
The Voltage Cortrol device includes the 8th NMOS tube MDRV, the drain electrode connection power supply electricity of the 8th NMOS tube MDRV
Pressure VDD, the grid of the 8th NMOS tube MDRV connects the drain electrode of the 4th NMOS tube MN4, the 8th NMOS tube MDRV
Source electrode as the linear voltage regulator output end OUT.
The feedback network is made up of the resistance string being connected between output end OUT of the linear voltage regulator and ground.Fig. 2
In, resistance string is in series by resistance R1 and resistance R2, and feedback voltage V FB is formed at both link positions.
The first switch is made up of the 9th NMOS tube MNa3, and the grid of the 9th NMOS tube MNa3 is opened for described first
Control end DET of pass, the drain electrode connection supply voltage VDD of the 9th NMOS tube MNa3, the source of the 9th NMOS tube MNa3
Pole connects first control signal NGATE.
As shown in figure 3, being the size of current of present pre-ferred embodiments linear voltage regulator each branch road when starting and being stable
Schematic diagram；
In present pre-ferred embodiments, the channel dimensions of PMOS MPa1, MP1 and MP3 are set to it is identical, so, institute
The electric current for stating Part I circuit is equal to the electric current of the first difference active load；And when linear voltage regulator is stable, it is described
Electric current all phases of the electric current of Part I circuit, the electric current of the first difference active load and the second difference active load
Deng.Size of current after above-mentioned 3 branch roads being shown in Fig. 3 when linear voltage regulator just starts and being stable.Such as described first
The size of current of partial circuit is that the implication of 2 × IB/IB is：The electricity of the Part I circuit when linear voltage regulator just starts
Flow for 2 × IB, linear voltage regulator stably after the electric current of the Part I circuit be IB；The electricity of the first difference active load
Stream size is also 2 × IB/IB, and the size of current of the second difference active load is 0/IB.
In present pre-ferred embodiments, the size such as channel width ratio of the raceway groove of NMOS tube MNa1 and NMOS tube MN5 sets
It is set to 3:4, so, the channel current size ratio of NMOS tube MNa1 and NMOS tube MN5 under identical gate source voltage is 3:4,
Namely the size ratio of the electric current of the electric current and the tail current source of the Part II circuit is 3：4.Can be seen that in Fig. 3
The electric current of the Part II circuit is fixed as 1.5 × IB, and the electric current of the tail current source is fixed as 2 × IB.The tail current
The electric current in source is the sum of the electric current of the electric current of the first difference active load and the second difference active load.And described
2 × IB when the electric current of two partial circuits is the firm startup of the electric current that 1.5 × IB is the Part I circuit and when stablizing
The middle value of IB；In other embodiments, the electric current of the Part II circuit being capable of its between 2 × IB to IB of fetch bit
Its median such as 1.4 × IB, 1.6 × IB etc., namely be not necessarily and to be worth middle value.
A kind of size of current of each branch road of preferred case, in other embodiments, PMOS MPa1 are only show in Fig. 3
Arranging with the channel dimensions of MP1 can be set to other ratios, at this moment the ratio of the channel dimensions of NMOS tube MNa1 and NMOS tube MN5
Value will do corresponding adjustment.
As shown in figure 4, be the startup simulation curve of present pre-ferred embodiments and existing linear voltage regulator, simulated conditions
For：Under conditions of power input 0 to 3.3V, the stabilization time from 0 to 1.5V is exported：Wherein curve 101 is supply voltage
Change curve, curve 102 is the change curve of output signal OUT of present pre-ferred embodiments, and curve 103 is shown in Fig. 1
The change curve of output signal OUT of available circuit, it can be seen that the starting time of present pre-ferred embodiments is 6.47 microseconds,
The starting time of available circuit framework is 16.66 microseconds.
The present invention has been described in detail above by specific embodiment, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (12)
1. a kind of linear voltage regulator, it is characterised in that include：Error amplifier, Voltage Cortrol device and feedback network；
The error amplifier includes amplifier body, tail current source and active load；
The amplifier body is for differential configuration and including first difference channel and second difference channel, first difference
The source of the source of parallel circuit and second difference channel all connects the tail current source, and the active load is included each other
The first difference active load and the second difference active load of mirror image, the first difference active load connects first difference
The load end of parallel circuit, the second difference active load connects the load end of second difference channel；Described first
The input connection reference voltage of difference channel, the input of second difference channel connects the anti-of the feedback network output
Feedthrough voltage；The load end of second difference channel also exports the first control signal to the voltage adjuster as output end
The control end of part；
Linear voltage regulator also includes the acceleration start-up circuit for accelerating linear voltage regulator to start, and the acceleration start-up circuit includes
Part I circuit, Part II circuit and first switch；
The Part I circuit is the mirror image circuit of the first difference active load, and the Part II circuit is the tail
The mirror image circuit of current source, the Part I circuit is connected with the Part II circuit and constitutes current comparator, institute
The output end for stating current comparator is connected to the control end of the first switch；
The electric current of the first difference active load described in the size of current of the tail current source and the second difference active load
The sum of electric current；When the linear voltage regulator is stable, the electric current of the first difference active load and second difference are active negative
The electric current of load is equal；
In the linear voltage regulator start-up course, the electric current of the first difference active load is active more than second difference negative
The electric current of load, and the electric current of the first difference active load from equal to the tail current source electric current size be gradually lowered for
The curent change mode of value when stable, the curent change mode of the Part I circuit and the first difference active load
Unanimously, the electric current of the Part II circuit keeps the size of current of constant and described Part II circuit to be set to start-up course
Described in Part I circuit electric current maximum and the median of minimum of a value so that start the incipient stage described in Part II
The electric current of circuit is more than the electric current of the Part I circuit so that current comparator output first voltage value；Starting
The electric current of the Part II circuit is less than the electric current of the Part I circuit so that the current comparator is defeated after end
Go out second voltage value；
The first switch is connected between supply voltage and first control signal, when described in current comparator output
During first voltage value, the first switch conducting makes first control signal connect the supply voltage so that described first
Control signal rapid increase starts so as to accelerate the linear voltage regulator；When the current comparator exports the second voltage value
When, the first switch disconnects, so that described accelerate start-up circuit not produce impact to the output of the linear voltage regulator.
2. linear voltage regulator as claimed in claim 1, it is characterised in that：First difference channel and second difference
Parallel circuit is all cascade amplifying circuit.
3. linear voltage regulator as claimed in claim 2, it is characterised in that：First difference channel includes the first NMOS tube
With the second NMOS tube, second difference channel of the amplifier body is including the 3rd NMOS tube and the 4th NMOS tube；
The source electrode of the source electrode of first NMOS tube and the 3rd NMOS tube is connected together as the amplifier body
The source of two difference channels；
The source electrode of drain electrode connection second NMOS tube of first NMOS tube, the drain electrode of second NMOS tube is used as described
The load end of first difference channel；
The source electrode of drain electrode connection the 4th NMOS tube of the 3rd NMOS tube, the drain electrode of the 4th NMOS tube is used as described
The load end of second difference channel and the output end as the amplifier body；
Input of the grid of first NMOS tube as first difference channel；
Input of the grid of the 3rd NMOS tube as second difference channel；
The grid of second NMOS tube connects the grid of the 4th NMOS tube and all connects the second bias voltage.
4. linear voltage regulator as claimed in claim 3, it is characterised in that：The first difference active load includes a PMOS
Pipe and the second PMOS, the second difference active load includes the 3rd PMOS and the 4th PMOS；
The source electrode of the source electrode of first PMOS and the 3rd PMOS all connects supply voltage；
The source electrode of drain electrode connection second PMOS of first PMOS, the drain electrode connection of the 3rd PMOS is described
The source electrode of the 4th PMOS；
The drain electrode of the grid of first PMOS, the grid of the 3rd PMOS and second PMOS all connects described
The drain electrode of the second NMOS tube；
The drain electrode of drain electrode connection the 4th NMOS tube of the 4th PMOS；
The grid of the grid of second PMOS and the 4th PMOS all connects the 3rd bias voltage.
5. the linear voltage regulator as described in claim 3 or 4, it is characterised in that：The tail current source includes the 5th NMOS tube, institute
The source ground of the 5th NMOS tube is stated, draining for the 5th NMOS tube connects the source electrode of first NMOS tube, the described 5th
The grid of NMOS tube connects the first bias voltage.
6. linear voltage regulator as claimed in claim 4, it is characterised in that：The Part I circuit include the 5th PMOS and
6th PMOS, the source electrode of the 5th PMOS connects supply voltage, the drain electrode connection the described 6th of the 5th PMOS
The source electrode of PMOS, the grid of the 5th PMOS connects the grid of first PMOS, the grid of the 6th PMOS
Pole connects the grid of second PMOS, and the drain electrode of the 6th PMOS connects the Part II circuit.
7. linear voltage regulator as claimed in claim 5, it is characterised in that：The Part II circuit include the 6th NMOS tube and
7th NMOS tube, the source ground of the 6th NMOS tube, the grid of the 6th NMOS tube and the grid of the 5th NMOS tube
Pole connects；
The source electrode of the 7th NMOS tube connects the drain electrode of the 6th NMOS tube, the grid of the 7th NMOS tube and described the
The grid connection of one NMOS tube；
The drain electrode of the 7th NMOS tube connects the Part I circuit.
8. the linear voltage regulator as described in claim 3 or 4, it is characterised in that：The Voltage Cortrol device includes the 8th NMOS
Pipe, the drain electrode connection supply voltage of the 8th NMOS tube, the grid of the 8th NMOS tube connects the 4th NMOS tube
Drain electrode, the output end of the source electrode of the 8th NMOS tube as the linear voltage regulator.
9. linear voltage regulator as claimed in claim 8, it is characterised in that：The feedback network is by being connected on the linear voltage stabilization
Resistance string composition between the output end and ground of device.
10. linear voltage regulator as claimed in claim 1 or 2 or 3 or 4, it is characterised in that：The first switch is by the 9th NMOS
Pipe is constituted, and the grid of the 9th NMOS tube is the control end of the first switch, the drain electrode connection electricity of the 9th NMOS tube
Source voltage, the source electrode of the 9th NMOS tube connects first control signal.
11. linear voltage regulators as claimed in claim 1, it is characterised in that：The electric current of the Part I circuit is equal to described
The electric current of the first difference active load.
12. linear voltage regulators as claimed in claim 11, it is characterised in that：The electric current and the tail of the Part II circuit
The size ratio of the electric current of current source is 3：4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710068638.2A CN106647914B (en) | 2017-02-08 | 2017-02-08 | Linear voltage regulator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710068638.2A CN106647914B (en) | 2017-02-08 | 2017-02-08 | Linear voltage regulator |
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| Publication Number | Publication Date |
|---|---|
| CN106647914A true CN106647914A (en) | 2017-05-10 |
| CN106647914B CN106647914B (en) | 2017-12-05 |
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| CN201710068638.2A Active CN106647914B (en) | 2017-02-08 | 2017-02-08 | Linear voltage regulator |
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Cited By (8)
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| CN107168432A (en) * | 2017-05-31 | 2017-09-15 | 成都锐成芯微科技股份有限公司 | Low-power dissipation power supply power supply circuit |
| CN107179797A (en) * | 2017-05-27 | 2017-09-19 | 上海华虹宏力半导体制造有限公司 | Linear voltage regulator |
| CN108287588A (en) * | 2018-01-30 | 2018-07-17 | 上海华虹宏力半导体制造有限公司 | Voltage adjuster |
| CN109062308A (en) * | 2018-09-29 | 2018-12-21 | 上海华虹宏力半导体制造有限公司 | Voltage-regulating circuit |
| CN112034924A (en) * | 2020-08-10 | 2020-12-04 | 唯捷创芯(天津)电子技术股份有限公司 | Self-adaptive fast response LDO (low dropout regulator) circuit and chip thereof |
| CN112099560A (en) * | 2020-09-25 | 2020-12-18 | 上海华虹宏力半导体制造有限公司 | Linear voltage stabilizer |
| CN113885650A (en) * | 2021-10-18 | 2022-01-04 | 上海华虹宏力半导体制造有限公司 | Band-gap reference source circuit |
| CN115309218A (en) * | 2021-05-07 | 2022-11-08 | 浙江驰拓科技有限公司 | Current reference circuit and power supply system |
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| CN107179797A (en) * | 2017-05-27 | 2017-09-19 | 上海华虹宏力半导体制造有限公司 | Linear voltage regulator |
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| CN115309218A (en) * | 2021-05-07 | 2022-11-08 | 浙江驰拓科技有限公司 | Current reference circuit and power supply system |
| CN113885650A (en) * | 2021-10-18 | 2022-01-04 | 上海华虹宏力半导体制造有限公司 | Band-gap reference source circuit |
| CN113885650B (en) * | 2021-10-18 | 2023-03-07 | 上海华虹宏力半导体制造有限公司 | Band-gap reference source circuit |
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