CN1070052A - Semiconductor devices and manufacture method thereof - Google Patents

Abstract

A kind of isolated-gate field effect transistor (IGFET) that is applicable to active matrix type liquid crystal display.Its channel length, promptly the spacing in source region and drain region is made into greater than grid along the vertical shared length of raceway groove.In channel region, be formed with skew (offset) district on the side in source region and drain region.These deviate regions are not subjected to or are subjected to the atomic weak electric field action from grid.

Description

Semiconductor devices and manufacture method thereof

The present invention relates to the active matric electro-optical device, more particularly, relate to a kind of field effect transistor that can be applicable to active matric (active-matrix) liquid crystal electro-optical and so on and have the optimized switch characteristic.The invention still further relates to the method for making this field effect transistor.

Prior art is used for the structure of the film-insulated grid field effect transistor of active matrix type liquid crystal electro-optical, as shown in Figure 2.On insulating substrate 9, be formed with restraining barrier 8.Have source region 4, the semiconductor layer of drain region 5 and channel region 3 is formed on the restraining barrier 8.On this semiconductor layer, be laminated with gate insulating film 2 and grid 1.Interlayer dielectric 12 is formed on gate insulating film 2 and the grid 1.Source electrode 6 and drain electrode 7 are formed on interlayer dielectric 12 and the semiconductor layer.

The manufacturing of the insulated gate FET of this prior art is described below according to the order of sequence: at first, and by using SiO ₂Sputtering method as rake produces restraining barrier 8 on glass substrate 9.Then, the CVD method of quickening by plasma forms semiconductor layer and has the source for constituting, and leaks and the semiconductor layer of channel region and composition.Then, the sputter monox is to form gate insulating film 2.Then, utilize the low pressure chemical vapor deposition method, produce by the high conductive layer of mixing phosphorus and being used to constitute grid.Then, for forming grid 1 to conductive layer body plan pattern.After this make mask with this grid, implant the ion of adulterant, thereby make source region 4 and drain region 5.Then, this laminate is heat-treated, to activate it.

The insulated gate FET that makes by this way, its grid 1 is identical with the represented channel length of label 10 basically along the vertically shared length of raceway groove.Under n structure road structure situation, electric current one voltage characteristic of the FET of this structure is shown in Fig. 3.The shortcoming of this FET is: in anti-district 13 partially, leakage current is along with being added in the voltage rising between source and drain region and increasing.When this device is used for active matrix type liquid crystal electro-optical, if the words that leakage current increases in this this mode, then during non-write cycle time, be stored in electric charge in the liquid crystal 29 by write current 30 and resemble shown in Fig. 5 (A) and by the leakage current 31 of this element leakage part, be released.After this manner, be impossible obtain good contrast.

The traditional method that addresses this problem is shown in Fig. 5 (B), an additional capacitor 32 in order to the maintenance electric charge.Yet,, the capacitance electrode of being made by metal interconnected must be arranged for constituting this capacitor.This causes aperture reducing than (aperture ratio).Also have, it is said, the aperture ratio is to be improved by make this electric capacity with the transparency electrode of ITO.Yet this method needs a unnecessary operation (excess process), thereby is out of favour.

In the source of this insulated gate FET and drain electrode, have only one of them a same capacitive device or a capacitor to link to each other, and this transistor is as under the occasion of switching device, for example, under the situation of the dynamic RAM (DRAM) of well-known one transistor/haplotype (1 transistor/cell type), its each pixel have as Fig. 5 (A) or the situation of the active-matrix liquid crystal display of circuit 5(B) under, people know: the voltage on the capacitor can change because have stray capacitance between grid and drain electrode or the source electrode.

The variable V of this voltage and grid voltage V _GBe directly proportional with stray capacitance, and be inversely proportional to the electric capacity sum of capacitor and stray capacitance.Therefore, when making this transistor, go to reduce parasitic capacitance usually, thereby suppress the variation of voltage by automatic adjustment technologies.But, when size of devices reduces, adopt automatic regulating method also not allow the degree of ignoring even the influence of stray capacitance then increases to.

With regard to managing to reduce variable V, a kind of new method has been proposed now.Specifically, shown in Fig. 5 (B), except that the capacitive device of itself, also be parallel with a capacitor, to increase the apparent capacity of this capacitive device.Yet, state as preceding, for DRAM, the area of this capacitor increases to be left in the basket to be disregarded.For LCD, the reducing of the numerical aperture of can not ignoring.

One object of the present invention just provides a kind of insulated gate FET that does not have above-mentioned all problems.

The realization approach of above-mentioned purpose is with the channel length among the insulated gate FET, it is the spacing in source region and drain region, be made into the length of being got along vertical (orientation) of raceway groove, thereby skew (offset) district is formed at respectively in the position of contacted those channel regions of homologous region and drain region greater than grid.Described deviate region is not subjected to the electric field action of grid, or is subjected to atomic weak grid effect of electric field.Electric current one voltage characteristic of this device is shown among Fig. 4.

Another object of the present invention provides the job operation of the described this insulated gate FET of leading portion.

Other purpose of the present invention and feature will manifest in following explanation to it.

Fig. 1 is the cross sectional view according to a kind of semiconductor devices of the present invention;

Fig. 2 is the cross sectional view of conventional semiconductor devices;

Fig. 3 is the current-voltage characteristic curve figure of expression traditional semiconductor devices shown in Figure 2;

Fig. 4 is the current-voltage characteristic curve figure that shows novel semi-conductor device shown in Figure 1;

Fig. 5 (A) and 5(B) be the partial circuit figure of traditional active matrix type liquid crystal electro-optical;

Fig. 6 is a part of circuit diagram of the active matrix type liquid crystal electro-optical of the example 1 according to the present invention;

Fig. 7 is that part of plan view of novel active matrix type liquid crystal electro-optical shown in Figure 6;

Fig. 8 (A) is to 8(F) be the partial cross section view of novel active matrix type liquid crystal electro-optical shown in Fig. 6 and 7, show the step of making this device;

Fig. 9 is the current-voltage characteristic curve figure of the P-channel TFT (thin film transistor (TFT)) of expression example 2 of the present invention;

Figure 10 is the current-voltage characteristic curve figure of the n channel TFT of expression example 2 of the present invention;

Figure 11 is the graph of relation of thickness of the drain current antianode film of illustrated example 2;

Figure 12 is the graph of relation of thickness of the threshold voltage antianode film of illustrated example 2;

Figure 13 is the graph of relation of thickness of the electric field mobility antianode film of illustrated example 2;

Figure 14 (A) is to 14(D) be the partial cross section diagrammatic sketch of the thin film transistor (TFT) of example 2, show the order of making this device;

Figure 15 (A) is to 15(C), be that Figure 14 (A) is to 14(D) shown in the top view of thin film transistor (TFT), show the manufacturing order of this device;

Figure 16 (A) is to 16(F) be the partial cross section view of the active matrix type liquid crystal electro-optical of example 1 of the present invention;

Figure 17 (a) and 17(b) be the expression tft characteristics curve map;

Figure 17 (c) is to 17(5) be the synoptic diagram that the principle of work of thin film transistor (TFT) of the present invention is described;

Figure 18 (A) is to 18(D) be the cross sectional view of the thin film transistor (TFT) of example 5 of the present invention, show the order of making this device;

Figure 19 (A) is to 19(D) be the cross sectional view of the thin film transistor (TFT) of example 6 of the present invention; Show the order of making this device;

Figure 20 is the plan view of the active matrix type liquid crystal electro-optical of example 6 of the present invention;

Figure 21 is a part of circuit diagram of the active matrix type liquid crystal electro-optical of example 7 of the present invention;

Figure 21 (A) and 21(B) be the explanation active matrix type liquid crystal electro-optical shown in Figure 21 work principle figure;

Figure 22 (A) is to 22(C) be the top view of the thin film transistor (TFT) of example 6 of the present invention, show the order of making this device.

Referring to Fig. 1, the figure shows the basic structure of field-effect transistor of the present invention. This transistor has insulating substrate 105 and the barrier layer 104 that is based upon on this substrate 105. Become source region 100, the semiconductor layer of drain region 101 and channel region 109 is based upon on the barrier layer 104. Be formed with gate insulating film 110 at channel region 109. Grid 111 is formed on the gate insulating film 110. The oxide layer 112 that belongs to insulating barrier is formed on the grid 111. This oxide layer 112 is by being carried out anodization by anodized material and form a kind of. Source electrode 102 and drain and 103 make it homologous region and drain region contact and form respectively. Not shown interlayer isolation film among Fig. 1, but at grid or be connected to the lead-in wire of this grid and source, drain region, or the occasion that is connected to parasitic capacitance between the lead-in wire of source or drain electrode and becomes problem can form interlayer isolation film with the same manner of prior art. The example of this respect will be described later.

Still referring to Fig. 1, the grid part that becomes grid 111 and oxide layer 112 is by can be by sun The material of polarization is made. The surface portion of this grid part is formed oxide layer 112 by anodization. Treat the source region 100 of implanting ions and the distance between the drain region 101, that is, channel length 108 grows the one-tenth-value thickness 1/10 that approximately doubles oxide layer 112 than grid 111 along the vertical shared physical length of raceway groove. Described grid part comprises metal or semiconductor. The material of grid part mainly is selected from titanium (Ti), aluminium (Al), tantalum (Ta), one of chromium (Cr) and silicon (Si). On the other hand, grid part also can be made by some alloy in these materials.

Therefore, those of channel region 109 be positioned at part 106 and 107 on the relative both sides of the gate insulating film 110 of extending from oxide layer 112 parts that are formed on the grid both sides be not subjected to the effect of grid electric field or stand than a little less than those parts that directly are under the grid the electric field action of Duoing. These zones 106 and 107, particularly aspect degree of crystallinity and dosage can with occasion that channel region is compared under, after this be called deviate region.

These zones 106 and 107 can be made of the amorphous material that mixes. More strictly speaking, unique necessary condition in zone 106 and 107 is that its degree of crystallinity is inferior to adjacent source region 100 and drain region 101. For example, if source region 100 and drain region 101 are to be made of the polysilicon with big crystalline particle, then 106 and 107 need in zone are made of half non-crystalline silicon or the non-crystalline silicon that degree of crystallinity slightly is better than non-crystalline silicon. If zone 100 and 101 is to be made of half non-crystalline silicon, then zone 106 and 107 can be made of non-crystalline silicon. Certainly, these amorphous materials are to need to make it present semiconducting behavior through fully processing. For example, in order to reduce to greatest extent dead key, must usually fully reduce this generic key by hydrogen or certain fontanel.

Just can obtain good TFT characteristic shown in Figure 17 (a) by forming these amorphous tagmas.Figure 17 (b) shows the I-E characteristic of a thin film transistor (TFT) of the gated transistor structure of prior art.Can see during as these family curves relatively, when adopting the prior art method, it is very big to can observe reverse leakage current.According to the inventive method, be roughly non-crystal zone owing to form, thereby improved this characteristic.That is to say that the formation of doping amorphous area has obtained the same advantage of formation as the deviate region of before having stated.

Why can to improve this characteristic be to understand fully in the formation of amorphous area.A possible reason is as described below: in amorphous area, the doped chemical of interpolation is ionized with the speed that is lower than in the crystalline region.Therefore, if add adulterant with same dose, then the performance of amorphous tagma they have lower concentration of dopant.That is to say, formed the zone that roughly is similar to lightly doped drain region.For example, the specific ionization under the amorphous silicon room temperature is 0.1-10%, and this is more much lower than monocrystalline that is almost 100% specific ionization or poly semiconductor.

Another possible cause is the band gap of the band gap of amorphous state greater than crystalline state.For example, this can explain by Figure 17 (e) and energy band diagram 17(f).With regard to common lightly doped drain structure transistor, can be with between source, raceway groove and the drain region be shown in Figure 17 (c) and 17(d) in.The stage casing lift portion is represented channel region.Step portion is represented lightly doped drain.Figure 17 (c) shows the not situation during making alive of grid.When grid applied with big negative voltage, situation shown in Figure 17 (d) just appearred.At this moment, there is the forbidden band between source region and the channel region and between channel region and the drain region, thereby preventing the motion of the charge carrier such as electronics and hole.But, these charge carriers can utilize tunnel effect or pass through band gap in the mode of skipping the trap level (trap level) in the band gap.In not belonging to the general thin film transistor (TFT) (TET) of lightly-doped drain zone structure, band gap width is less, so be easier to flow through electric current.This is considered to oppositely sew.This phenomenon is particularly remarkable concerning TFT, and may be caused by the many trap levels owing to the grain boundary, because TFT is by making such as the heterogeneous material of polycrystal etc.

When the band gap in the increase lightly doped drain, above-mentioned reverse leakage current just reduces.This example be shown in Figure 17 (e) and 17(f) in.Figure 17 (e) shows the situation when voltage not being applied to grid, the situation when Figure 17 (f) illustrates grid and is added with big negative voltage.When shown in Figure 17 (f), applying a negative pressure, then as comparison diagram 17(f) finding when Figure 17 (d), the band gap width between band gap width between source region and the channel region and channel region and the drain region is all greater than the respective width in the situation shown in Figure 17 (d).Tunnel effect is subjected to the influence of the width (being band gap width in the case) of tunnel barrier layer widely.Along with the probability that charge carrier penetrates band gap that increases a little of band gap width reduces greatly.Moreover, be a kind of synthetic tunnel effect via the transition of local level, therefore, when band gap width increased, wearing the probability of stating band gap can sharply descend.Because these reasons are so think that it is favourable making lightly doped drain have large band gap.The band gap of amorphous silicon is 1.5 to 1.8eV, and the band gap of polysilicon is 1.1eV.If lightly doped drain adopts the material with such broad-band gap, then can produce suitable ideal situation.

For making semiconductor device according to the invention, especially make semiconductor devices with above-mentioned deviate region, becoming the source region, after forming, the semiconductor layer of drain region and channel region and gate insulation layer 110 follow with being set up grid part by anodized material, with giving semiconductor layer is that the dopant ion of P type or n type is implanted this semiconductor layer, to form source region 100 and drain region 101.After this, anodization (anodic oxidation) is carried out on the surface of grid part, to produce grid 111 and oxide layer 112.After this, heat-treat again or other step.

Another kind method is: form semiconductor layer and gate insulation layer 110 earlier, use and can then, be carried out anodization (anodic oxidation) to the surface of grid part by anodized material grid part, to form grid 111 and oxide layer 112.Then, with dopant ion implanted semiconductor layer, be P or n type to give it, form source region 100 and drain region 101 simultaneously.After this, finish thermal treatment.

In implementing these step process, can be easily and make its ditch reliably and make length greater than along the vertical insulated gate FET of shared grid length of raceway groove, and can not produce because of the caused performance change of mask deviation.

The another kind of method that manufacturing has the novel semi-conductor device in amorphous tagma is to form at the beginning to become the source region, the semiconductor layer of drain region and channel region and gate insulation layer 110.Then, using can be by anodized made grid part.Then, implant dopant ion, so that semiconductor layer doped becomes P type or n type.Therefore, it is non-crystal semiconductor layer to be made.Form source region 100, drain region 101, and the amorphous tagma of adjoining 106 and 107.After this, the surface portion of grid part is carried out anodization, to form grid 111 and oxide layer 112.At this moment, gate surface being carried out oxidation handles again.Then, when by the self-adjusting technology of using laser annealing or flash lamp annealing technology grid part being used as mask, an active area 100 and drain region 101 can be by crystallizations again.This technological process belongs to the self-adjusting pattern, because grid part has been covered the bottom doped region that is positioned at below the grid part, so forbidden the crystallization again of these doped regions.

In the place that utilizes ion implantation technology, the scope (spreading) of the doped region that is caused by the diffusion of the secondary of ion can be calculated according to the acceleration energy of ion.Moreover handling by thickness of oxide layer again of grid determined, therefore, handles and also got as a design parameter.According to the present invention, can reach the optimization of position relation between grid and the doped region by accurate design.More particularly, can control thickness of oxide layer less than 10nm by tolerance.In addition, the rescattering that is produced during ion is implanted can be controlled by the franchise of the same order of magnitude therewith.Therefore, during the manufacturing, the position relation can be controlled to franchise less than 10nm.

This shows that the present invention need not more accurate mask adjustment.The product proportion of goods damageds of being produced by the inventive method are very low.Or rather, device of the present invention has every performance of improving greatly.Examples more of the present invention have been provided below.

Example 1

Employing is the reflective mirror that 1 inch liquid crystal electro-optical manufacturing is used for TV camera according to diagonal line of the present invention.This device has 387 * 128 pixels, and this reflective mirror is with the TFT(thin film transistor (TFT) of high mobility) in low temperature process, make.The configuration that is used for each active component on the substrate of liquid crystal electro-optical of this example is shown among Fig. 7.Fig. 6 is this routine circuit diagram.Manufacturing step is shown in Fig. 8 (A) of being cut along straight line A-A ' and B-B ' to 8(F) in.Getting xsect along straight line A-A ' institute represents-the n channel TFT.Getting xsect along straight line B-B ' institute represents-the P channel TFT.

In Fig. 8 (A), glass substrate 51 is made of a kind of cheap material and has experienced below 700 ℃, for example about 600 ℃, thermal treatment.By magnetron RF(high frequency) sputtering technology, on glass substrate 51 sputter monox to thickness be 1000 to 3000 dusts ( ), to form restraining barrier 52.Its environmental baseline is 100% oxygen.Under 150 ℃ of temperature, form this film.The magnetron output power is 400 to 800 degree.Pressure is 0.5Pa.Used rake is that a kind of monocrystal by quartz or silicon constitutes.Deposition is 30 to 100

/ minute.

With low pressure chemical vapor deposition (LPCVD), sputter, or plasma acceleration CVD method forms silicon fiml on this restraining barrier 52.In the occasion of usefulness low pressure chemical vapor deposition method formation silicon fiml, then to for example at 530 ℃, descend, in a certain temperature that is lower than 100 to 200 ℃ of Tcs (for example 450 to 550 ℃) with disilane (Si ₂H ₆) or three silane (Si ₃H ₈) add in the CVD equipment, the reacting furnace internal pressure is 30 to 300Pa.Deposition rate is 50 to 250

/ minute.For making P raceway groove and n channel TFT have roughly uniform threshold voltage Vth, can be 1 * 10 with the concentration of diborane form ¹⁵To 1 * 10 ¹⁸Atom/cm ³Boron be added into this film.

Using under the situation of sputtering method, carrying out the preceding back pressure of sputter is 1 * 10 ^-5Pa or littler.With a kind of monocrystalline silicon as rake.This technological process realizes under the ar gas environment that has added 20-80% hydrogen.For example, argon gas accounts for 20%, and hydrogen accounts for 80%, forms this film in the time of 150 ℃.The frequency of RF is 13.56MHz.The sputter output power is 400 to 800 watts.Pressure is 0.5Pa.

In the occasion of quickening the silicon fiml of CVD method formation with plasma, for example, temperature is 300 ℃.Adopt monosilane (SiH ₄) or disilane (Si ₂H ₆).This class material is imported into PCVD equipment.Form silicon fiml applying under the RF electric power of 13.56MHz.

Be preferably 5 * 10 by the oxygen content that adopts the silicon fiml that these methods form ²¹Atom/cm ³Or it is littler.If when oxygen concentration is high, then is difficult to crystallization and goes out silicon fiml.As a result, essential heat treatment temperature or the prolongation heat treatment period of promoting.Otherwise, if the concentration of oxygen is low excessively, then because the leakage current increase that causes under the off-state backlight.Therefore, its suitable concentration scope is 4 * 10 ¹⁹To 4 * 10 ²¹Atom/cm ³Hydrogen concentration is 4 * 10 ²⁰Atom/cm ³, it is 4 * 10 ²²Atom/cm ³1 atomic percent of silicon concentration.

Forming 500 to 5000 with above-mentioned either party's method , for example 1500

After the thick amorphous silicon membrane, this tunic is placed under the nonoxidizing environmental baseline with 12 to 70 hours thermal treatment of 450 to 700 ℃ of moderate temperature experience.For example this tunic is placed in 600 ℃ the hydrogen chamber.Because being the substrate surface place below silicon fiml, the amorphous silicon oxide film forms, so during this thermal treatment, do not have distinctive nuclear (Specific nuclei).Therefore, whole layer is subjected to uniform treatment.That is to say, during the formation of film, be assumed to be non-crystal structure.Hydrogen is just sneaked in it.

Through bakingout process, silicon fiml transfers higher ordered state (more highly ordered-state) to from amorphous state.Silicon fiml partly presents crystalline state.Particularly, those zones that present the comparison order state during forming silicon film are tending towards crystallization.Yet the silicon atom between these higher order regions is associated in together these districts, and therefore, silicon atom attracts each other.Measurement with the laser Raman spectroscopy shows: exist silicon single crystal from 522cm ^-1Peak value shift to the fact than the low frequency peak value.Shown by the calculating of half-breadth value: apparent particle diameter scope is 50 to 500

That is to say their similar micrinite.Yet in fact, there is a large amount of crystalline regions, that is, produces a large amount of nanoclusters.These nanoclusters are fixed to one another by silicon atom.The coating of Chan Shenging has half non crystalline structure like this.

Therefore, we can say: in this coating, do not have the grain boundary basically.Because charge carrier can easily navigate between the nanocluster of fixed position, so this mobility of charge carrier rate is higher than the polysilicon with obvious grain boundary.Or rather, hole mobility (μ h) is 10 to 200cm ²/ V. second.Electron mobility (ue) is 15 to 300cm ²/ V. second.

If this coating is by a certain high-temperature heat treatment between 900 ℃ to 1200 ℃, rather than, then make the impurity segregation of coating owing to the solid state growth of nucleus via resembling moderate temperature thermal treatment recited above when constituting by polycrystal.A large amount of oxygen, impurity such as carbon and nitrogen are included in the grain boundary.An intragranular mobility is big.Yet mobility of charge carrier is subjected to the obstruction on the restraining barrier of crystal boundary place formation, makes it be difficult to obtain to surpass 10cm ²The mobility of/V. second.Therefore, must make the concentration of oxygen, carbon, nitrogen and other impurity in half amorphous film in impurity concentration, account for little or minimum ratio.In this case, obtained 50 to 100cm ²The mobility of/V. second.

The silicon fiml of Xing Chenging forms the semiconductor layer 53 of n-channel TFT and the semiconductor layer 54 of P-channel TFT through light offset printing etching by this way.The channel width of layer 53 is 20 μ m.With the same terms of the silicon oxide layer that forms the restraining barrier under, become the silicon oxide layer of gate insulating film, make its thickness reach 500 to 2000 , for example, reach 1000

During forming silicon oxide layer, can add small amount of fluorine, with the set sodion.

Then, on silicon oxide layer, form the aluminium film.Adopt photomask that the aluminium film is drawn pattern, this results are shown among Fig. 8 (B).Form the gate insulating film 55 and the grid part 56 of n-channel TFT.These films 55 and electrode part 56 are 10 μ m along the vertical shared length of raceway groove.That is to say that channel length is 10 μ m.Similarly, form the gate insulating film 57 and the grid part 58 of P channel TFT.Film 57 and grid part 58 along raceway groove longitudinally length be 7 μ m.In other words, channel length is 7 μ m.Grid part 56 and 58 thickness are 0.8 μ m.In Fig. 8 (C), to the P channel TFT with 1 to 5 * 10 ¹⁵Ion/cm ²The boron of dosage (B) is implanted source region 59 and drain region 60.Then, shown in Fig. 8 (D), form photoresist 61 with the light mask method.To the n-channel TFT, with 1 to 5 * 10 ¹⁵Ion/cm ²The phosphorus of dosage (P) is implanted source region 62 and drain region 63.

Then, carry out the grid part anodization.The acid that spent glycol will contain the L-winestone is diluted to 5% concentration, and with ammonia pH value is transferred to 7.0 ± 0.2.This laminated product immersed in this solution and join with the anode of constant current source.One platinum electrode is connected to negative terminal.When electric current remains on 20mA, increase progressively institute's making alive.Oxidizing process is proceeded to reach 150V until voltage.Then, voltage is maintained 150V, proceed this oxidation operation until electric current reduce to 0.1mA when following till.Like this, on the surface of grid part 56 and 58, form aluminium oxide layers 64, thereby respectively n-channel TFT and P-channel TFT are produced grid 65 and 66.The thickness of aluminium oxide layers 64 is 0.3 μ m.

Then, laminated product is placed under 600 ℃ again thermal treatment through 10 to 50 hours.In the source region 62 of n channel TFT and drain region 63 and the source region 59 of P-channel TFT and the adulterant in the drain region 60 be activated so that this zone of two types is doped to n respectively ⁺Type and P ⁺Type.The raceway groove district 67 and 68 that is shaped is formed as half amorphous semiconductors below the exhausted film 55 of grid and 57 respectively.

In the method, the ion of adulterant is implanted and the order that the anodization of grid can be opposite is carried out.

Like this, formed the insulation course that metal oxide constitutes around grid.So the physical length of each grid has been lacked the thickness that doubles dielectric film than channel length, be 0.6 μ m in the case.The formation of the deviate region that no electric field applies can reduce back-biased leakage current.

In this example, carried out Fig. 8 (A) and 8(E) shown in twice thermal treatment.Depend on desirable characteristics and decide, can save the thermal treatment shown in Fig. 8 (A).Twice thermal treatment can be finished in a step shown in Fig. 8 (E), thereby shortens manufacturing time.In Fig. 8 (E), formed interlevel insulator 69 by the sputter monox.The formation of silicon oxide layer can be adopted LPCVD, acceleration by light CVD or atmospheric pressure CVD technology.The thickness that forms interlevel insulator is 0.2 to 0.6 μ m, for example is 0.3 μ m.Then, adopt photomask to form electrode hole 70.Shown in Fig. 8 (F), with sputtered aluminum to whole lamination.Utilize photomask to form lead-in wire 71,73 and contact 72.After this, to plane (Planarizing) organic resin 74 of lamination coating transmitted light, for example polyimide resin.Form electrode hole once more with photomask.

For with two TFT as complementary pair, and this is linked TFT on the pixel capacitors of liquid crystal device, form indium tin oxidation (ITO) film by sputtering method, a described pixel capacitors is a transparency electrode.Use the photomask etching indium-tin oxide film, to form electrode 75.The ITO film be under a certain temperature between room temperature and 150 ℃, form and under oxygen or atmospheric environment through 200-400 ℃ thermal treatment.Like this, on same glass substrate 51, can form n-channel TFT 76, the electrode 75 of p-channel TFT 77 and nesa coating.Resulting thin film transistor (TFT) presents following electric property.The mobility of p-channel TFT is 20cm ²/ V. second, threshold voltage vt h is-5.9V.The mobility of n-channel TFT is 40cm ²/ V second, its threshold voltage vt h is 5.0V.

An a kind of substrate of liquid crystal electro-optical makes by said method.The electrode of this liquid crystal electro-optical and the configuration of other parts are shown among Fig. 7.N-channel TFT 76 and p-channel TFT 77 are to form in the intersection of first signal wire 40 and secondary signal line 41.The TFT complementary pair of this structure becomes row and column to arrange.63 input end is connected to secondary signal line 41 via lead-in wire 71 to n-channel TFT 76 in the drain region.Grid part 56 is connected with first signal wire 40 that constitutes multi-layer conductor leads.Pixel capacitors 75 is linked by contact 72 in the output terminal footpath in source region 62.

On the other hand, relative p-channel TFT 77, the input end in drain region 60 is connected with secondary signal line 41 via lead-in wire 73.Grid part 58 is connected with signal wire 40.The output terminal in source region 59 is via contact 72, to be connected with pixel capacitors 75 with the same manner of n-channel TFT.For realizing this example, repeat this structure in the horizontal and vertical directions.

As second substrate, sputter thickness reaches 2000 on a blue sheet glass

Monox.Again on this substrate, form the ITO film by sputter with a certain temperature between room temperature and 150 ℃.Under oxygen or atmospheric environment, this film is heat-treated with 200-400 ℃.On this substrate, form color filter, thereby finish second substrate.

Between first and second substrates, sandwich and comprise the acryl resin that 6 parts solidify with ultraviolet irradiation and the potpourri of 4 part nematic liquid crystals.The periphery of two substrates is fixed with epoxy resin.Because on-chip lead-in wire has only 46 μ m each other apart, so the COG method is adopted in their connection.In this example, the gold bump portion that forms on-IC chip utilizes silver epoxy-palladium resin to connect.Interval between IC chip and the substrate all is embedded in the epoxy modified form acryl resin, whereby, they is completely bonded together hermetically.Then, polarising sheet is bonded to the outside.Like this, just, obtain a kind of transmission type liquid crystal electro-optical device.In addition, same procedure also can be made as Figure 16 (A) to 16(F in the use-case 1) shown in the transmission type liquid crystal electro-optical device.

Example 2

In this example, characteristic variations by caused half non-crystalline silicon tft of the different in width of deviate region be described.In this example, half non-crystalline silicon tft has alum gate.Around the alum gate through anodization and oxidized.Form deviate region thus.A kind of method of making TFT will be described in detail in detail below.

On glass substrate, form the multilayer film of forming by silicon nitride film and silicon oxide film.Quickening CVD method formation thickness with plasma is the amorphous silicon film of 150nm.Reach the TFT raceway groove of 80 μ m to the silicon fiml graphing for forming width.Putting laminated product heated 60 hours with 600 ℃ in nitrogen chamber.Make half amorphous silicon like this.

Then, the rake of sputter monox under oxygen atmosphere can become the silicon oxide layer of gate oxidation films with formation, and this thickness is 115nm.Form aluminum coating with the electron beam shooting method.With well-known optical plane printing technology, aluminum coating and beneath silicon oxide layer are carried out etching, to form grid.In etching procedure, adopted reactive ion etching method RIE(reactive-ion etching), the length of grid channel that forms with this method is 8 μ m.

Then, grid and coupling part thereof are carried out anodization.For this purpose, spent glycol is diluted to tartrate 3% concentration and puts into container.In this liquid, add percentage by weight then and be 5% aqueous ammonia, so that pH value is transferred to 7.0 ± 0.2.Whole laminated product is immersed in this solution, adopt the platinum electrode of temperature under 25 ± 2 ℃ simultaneously as negative electrode.Aluminium Nei Lianzhu portion joins with the anode of DC power supply, thus, laminated product is carried out anodization.

In the anodization step, pass through 0.2 earlier to 1mA/cm ²Steady current.Reach certain suitable value of 100 to 250V at voltage after, just keep the anodization of voltage constant, when electric current drops to 0.005mA/cm ²The time, power cutoff.Then, take out this laminated product.Our description of test: the constant-current phase of beginning only influences the formation time of oxide film and influences the finally thickness of the oxide film of formation hardly.A parameter that obviously influences oxide thickness is accessible maximum voltage.At maximum voltage is 100V, 150V, and when 200V and 250V, resulting oxide thickness is respectively 70nm, 140nm, 230nm and 320nm.Our experiment shows that also the thickness of the alumite of acquisition is 1.5 times of aluminium oxide.And the oxide thickness that is obtained is all quite consistent on whole length.

Then, form source region and drain region by laser doping.Adopted KrF (KrF) laser instrument in this laser doping operation, this is a kind of excimer laser.Its oscillation frequency is 248nm.Sample is put in the airtight container.Produce the environment under low pressure of 95Pa.With diborane (B ₂H ₆) or hydrogen phosphide (PH ₃) introduce this container as impurity gas.Laser instrument sends 50 pulse shocks (shots).The energy that each laser pulse is impacted is 350mJ.

Making P-channel TFT occasion, the diborane that waters down with hydrogen is used as impurity gas.The flow of diborane is 100sccm.The flow of hydrogen is 20sccm.Making n-channel TFT occasion, adopted hydrogen phosphide.The flow of hydrogen phosphide is 100sccm.

Then, for quickening the activation of channel region, put laminated product and under nitrogen atmosphere, experience 30 minutes 250 ℃ thermal treatment.Form interlayer dielectric with well-known method, source electrode and drain electrode and their interior company headquarters branch, thus make TFT.

The properties example of the several TFT that make like this is shown among Fig. 9 and Figure 10.Fig. 9 shows the family curve of p-channel TFT.Figure 10 illustrates the characteristic varicose of n-channel TFT.Owing to be difficult to directly measure the size of deviate region, the existing thickness aspect that just centers on the oxide film of grid illustrates advantage of the present invention.We think that this thickness is enough to reflect the size of deviate region.

By Fig. 9 and 10 as seen, reverse leakage current and cut-off current increase along with the thickness of oxide film and reduce, that is, and and along with the width of deviate region increases and reduces.We find that concerning the n-channel TFT, this effect is more remarkable.In fact, for the n-channel TFT, the electric current when grid voltage is zero, or cut-off current and drops to an actual level because the formation deviate region is reduced.With regard to the p-channel TFT, cut-off current does not reduce, but reverse leakage current reduces greatly.Reduce to be illustrated among Figure 11 I wherein because of what form that deviate region causes cut-off current _OFFBe cut-off current, I _ONIt is turn-on current.

The formation of deviate region does not change the threshold voltage of TFT.This point obtains explanation in Figure 12.Yet different experiments has shown the unusual big place of deviate region, observes owing to formed raceway groove is the discontinuous performance depreciation that causes.For example, as shown in figure 13, when the width of each deviate region surpassed 300nm, then the electric field activity (fieldmobility) of n-raceway groove and p-channel TFT reduced rapidly.Consider these results, as seen: the suitable width scope of each deviate region is 200 to 400nm.

Example 3

In the TFT of the made according to the present invention, the width of each deviate region not only influences cut-off current, and influences voltage-resistive performance and operating speed between source and the drain region.Therefore, the parameter optimization of thickness by making anodic film and so on and can make desirable TFT.Yet in general, to go to adjust this class parameter be impossible to being independently formed in on-chip each TFT.For example, need such side circuit: promptly require in the TFT that is formed on operation under the low speed and tolerance high pressure on the same substrate and operation under high speed and stand the TFT of low pressure.According to ultimate principle of the present invention, along with the width increase of each deviate region, cut-off current reduces with resistance voltage characteristic to be improved but operating speed reduces.

This example has solved this problem, below with reference to Figure 14 (A) to 14(D) sectional view and Figure 15 (A) to 15(C) planimetric map be illustrated.This example is about making circuit used in a kind of image display method, this method is with a p-channel TFT and n-raceway groove FTF de-energisation one pixel, described in Japanese patent application 296331/1991, require this n channel TFT with high speed operation, but only need bear low-voltage gets final product, on the other hand, this p-channel TFT need not with high speed operation very, but its cut-off current must be low.In some cases, the p-channel TFT must be born high voltage.Therefore, just require: the anodic film of n-channel TFT will approach (20 to 100nm), and the anodic film of p-channel TFT thick (250 to 400nm).This routine manufacturing step is described below.

As Figure 14 (A) with 15(A), substrate 101 is made by 7059 corning glasss.What form thickness and be 50nm is roughly intrinsic amorphous or polycrystal semiconductor film, for example is amorphous silicon film.This film is plotted as the independent zones pattern that forms n-channel TFT district 102 and p-channel TFT district 103.The thermal treatment that laminated product is placed 600 ℃ of 60 hours temperature of the indoor experience of nitrogen is so that TFT respectively distinguishes crystallization again.

With ECR PCVD method silicon oxide deposition as the thick gate insulating film 104 of 115nm.If in the silicon oxide layer that forms like this, there is the mobile ion that resembles sodion and so on, then preferably by the element such as phosphorus is imported fixedly mobile ion of this film, to exempt the deleterious effect of mobile ion.This class component can import by resembling known ion doping methods such as plasma doping.

The inventor finds: with the ion doping method phosphorus is introduced silicon oxide layer and played effect as the sodium absorbing agent effectively.During this ion doping operation, phosphonium ion is 2 to 30KeV, and for example 10Kev is accelerated.Rake ambient pressure to be mixed is 2 * 10 ^-5To 5 * 10 ^-4Torr for example is 1 * 10 ^-4Torr.In this example, harrow and be silicon oxide film.The concentration of phosphorus is 5 * 10 ¹³To 1 * 10 ¹⁵Ion/cm ², for example be 2 * 10 ¹⁴Ion/cm ²Like this, the dosage of phosphorus is less than the dopant dosage that is added when forming the doped region of common MOS transistor.

After adding phosphorus like this, lamination is placed in the nitrogen environment, 600 ℃ of thermal treatments through 24 hours are to remove the defective in the silicon oxide layer that is produced because of ion doping.Phosphorus introduced silicon oxide layer has been prevented widely because the deterioration of the aspect of performance that removable ion caused.Therefore, reliability can be improved.For example, the mos capacitance device that will have a silicon oxide layer that forms with said method is after standing 150 ℃ of 1 hour temperature and the voltage bias voltage/Temperature Treatment for ± 20V, and its threshold voltage has only changed 1V.Do not introducing under the situation of phosphorus, this threshold voltage variation can be up to more than the 10V.

After forming silicon oxide layer in this way, forming thickness is the tantalum film of the refractory metal of 500nm.This tantalum film is drawn pattern, with the grid part 105 of formation n-channel TFT and the grid part 106 of p-channel TFT.Also can replace low-resistivity without tantalum, that is, and the abundant polysilicon that mixes.At this moment, channel length and width are 8 μ m.Grid and interconnecting parts thereof all are electrically connected to the common interconnect portion 150 as shown in Figure 15 (A).

Grid and interconnection portion 105 and 106 thereof are passed to electric current, on the upper surface of grid and interconnection portion 105 and 106 and side, to form aluminum oxide film 107 and 108 by anodization (anodic oxidation) method.Except maximum voltage is 50V, with same this anodization of enforcement in the example 2.As a result, be approximately 60nm(Figure 14 B at this thickness that goes on foot prepared anodic film).

With reference to Figure 15 (B), use the laser ablation method 151 cuttings, so that grid and interconnection portion 105 thereof disconnect with common interconnect portion 150.In the case, interconnection portion 150 is passed to electric current begin anodization (anodic oxidation) once more, partly be connected to interconnection portion 150 after the cutting with anodized surface with grid.These conditions are except maximum voltage increases to 250V, and are all identical with aforementioned condition.Because no current flows through interconnection portion 105, does not observe any variation.Yet, because electric current flows through the 106(Figure 14 c of interconnection portion), around gate interconnection portion 106, formed the tantalum oxide film 109 that thickness is about 300nm.

Then, with the ion doping method dopant ion is introduced each independent zones of semiconductor 102 and 103.With well-known CMOS manufacturing technology respectively with phosphorus (p) and boron (B) implanted semiconductor district 102 and 103.The energy of dopant ion is that 80Kev, the inventor and other people know that adulterant is implanted in the mode of passing gate insulating film 100 to 300nm thickness, if ion energy surpasses 100Kev, then this place's semiconductor grain will be seriously damaged because of the energy of this implanting ions.Be these districts that the activation adulterant spreads, essential high temperature more than 600 ℃ within it.It is extremely difficult will obtaining high productivity in this process.Yet, be 100Kev or less part at the implanting ions energy, 600 ℃ of following temperature, for example 450～500 ℃ can make resistance enough low.

After the ion doping step, laminated product is put 500 ℃ of thermal treatments of 30 hours of the indoor experience of nitrogen, so that the surface resistance in source region and drain region can reach is enough low.State when reaching this is shown among Figure 14 (D).By this figure as seen, the width of the deviate region of left side TFT is little, and the width of the deviate region of right side TFT is big.After this, use well-known technology, as 152 and 153 etc. desired location cutting metal interconnection portion 106 and 150.Then, form interlayer dielectric.Form contact hole.To be connected to each electrode such as 112 and 113 conductive interconnection portion, thereby finish circuit shown in Figure 15 (C).

In the circuit made from this method, the deviate region width of n-channel TFT is little, and cut-off current is big slightly, but this TFT is aspect operating speed, and performance is fabulous.On the other hand, it is difficult that the p-raceway groove is operated under high speed, but its cut-off current is little.Moreover the ability of p-channel TFT stored electric charge in keeping the pixel capacitance device that is connected with one of drain region with its source region is fabulous.The pixel capacitance device comprises pair of electrodes (indium tin oxide) and is arranged between the electrode and comprises the electrooptical modulation layer of liquid crystal.

In some other situation, several TFT that must will have difference in functionality are contained on the substrate in combination.For example, in a LCD driver, comprise that the logical circuit of shift register needs high speed TFT, and output circuit needs high voltage bearing TFT.This routine method is practicable when making the TFT that must satisfy this class contradiction requirement.

Example 4

In the TFT of the manufacturing according to the present invention, the width of each deviate region not only influences cut-off current, and influences withstand voltage properties and operating speed between source and the drain electrode.Therefore, making the TFT that satisfies this purpose can realize by making certain parameter optimization such as the thickness of anodic film.Yet usually, this class parameter that is adjusted at independent each TFT that forms on the substrate is impossible.For example, certain particular electrical circuit need form low-speed handing and tolerate the TFT of high pressure and the TFT of high speed operation and anti-low pressure on same substrate.According to ultimate principle of the present invention, along with the width increase of each deviate region, cut-off current reduces with resistance voltage characteristic to be improved, but operating speed reduces.

This example has solved this problem, below with reference to Figure 14 (A) to 14(D) sectional view and Figure 15 (A) to 15(C) planimetric map described.This example is about making circuit used in a kind of image display method, this method is with a p-channel TFT and n-channel TFT de-energisation one pixel, described in Japanese patent application 296331/1991, require this n channel TFT with high speed operation, but only need bear low-voltage gets final product, on the other hand, this p-channel TFT need not with high speed operation very, but its cut-off current must be low.In some cases, the p-channel TFT must be born high voltage.Therefore, just require: the anodic film of n-channel TFT will approach (20 to 100nm), and the anodic film of p-channel TFT thick (250 to 400nm).This routine manufacturing step is described below.

As Figure 14 (A) with 15(A), substrate 101 is made by 7059 corning glasss.What form thickness and be 50nm is roughly intrinsic amorphous or polycrystal semiconductor film, for example is amorphous silicon film.This film is plotted as the independent zones pattern that forms n-channel TFT district 102 and p-channel TFT district 103.The thermal treatment that laminated product is placed 600 ℃ of 60 hours temperature of the indoor experience of nitrogen is so that TFT respectively distinguishes crystallization again.With ECR PCVD method deposit silicon oxide as the thick gate insulating film 104 of 115nm.Form the tantalum film that thickness is the refractory metal of 500nm again.This tantalum film is drawn pattern, with the grid part 105 of formation n-channel TFT and the grid part 106 of p-channel TFT.Also can replace low-resistivity without tantalum, that is, and the abundant polysilicon that mixes.At this moment, channel length and width are 8 μ m.Grid and interconnecting parts thereof all are electrically connected to the common interconnect portion 150 as shown in Figure 15 (A).

Grid and interconnection portion 105 and 106 thereof are passed to electric current, on the upper surface of grid and interconnection portion 105 and 106 and side, to form aluminum oxide film 107 and 108 by anodization (anodic oxidation) method.Except maximum voltage is 50V, with example 2 same these anodization of enforcement.As a result, be approximately 60nm(Figure 14 B at this thickness that goes on foot prepared anodic film).

With reference to Figure 15 (B), use the laser ablation method 151 cuttings, so that grid and interconnection portion 105 thereof disconnect with common interconnect portion 150.In the case, begin anodization once more, these conditions are except maximum voltage increases to 250V, and are all identical with aforementioned condition.Because no current flows through interconnection portion 105, does not observe any variation.Yet, because electric current flows through the 106(Figure 14 c of interconnection portion), around gate interconnection portion 106, formed the tantalum oxide film 109 that thickness is about 300nm.

Then, with the ion doping method dopant ion is introduced each independent zones of semiconductor 102 and 103.With well-known CMOS manufacturing technology respectively with phosphorus (p) and boron (B) implanted semiconductor district 102 and 103.The energy of dopant ion is 80Kev.We know if ion energy surpasses 100Kev, are these districts that the activation adulterant spreads, essential high temperature more than 600 ℃ within it.It is extremely difficult will obtaining high productivity in this process.Yet, less than the 100Kev place,, for example 450～500 ℃, can make resistance enough low 600 ℃ of following temperature at the implanting ions energy.

After the ion doping step, laminated product is put 500 ℃ of thermal treatments of 30 hours of the indoor experience of nitrogen, so that the surface resistance in source region and drain region can reach is enough low.State representation when reaching this is in Figure 14 (D).By this figure as seen, the width of the deviate region of left side TFT is little, and the width of the deviate region of right side TFT is big.After this, use well-known technology, as 152 and 153 etc. desired location cutting metal interconnection portion 106 and 150.Then, form interlayer dielectric.Form contact hole.To be connected to each electrode such as 112 and 113 conductive interconnection portion, thereby finish circuit shown in Figure 15 (C).

In the circuit made from this method, the deviate region width of n-channel TFT is little, and cut-off current is relatively large, but this TFT is aspect operating speed, and performance is fabulous.On the other hand, it is difficult that the p-raceway groove is operated under high speed, but its cut-off current is little.Moreover, be fabulous aspect the ability of p-channel TFT stored electric charge in keeping the pixel capacitance device.

Example 5

Figure 18 (A) is to 18(D) show this routine sectional view.Substrate 501 is made by healthy and free from worry 7059 glass.Forming thickness with sputtering method is the base silicon oxide film 502 of 100nm.Quickening CVD method formation thickness with plasma again is the amorphous silicon film 503 of 50nm.Be the protection amorphous silicon film, forming thickness with sputtering method again is the silicon oxide layer 504 of 20nm.This lamination is placed in the nitrogen environment, 600 ℃ of thermal treatments of 72 hours of experience down, so that the crystallization again of these films.Film after the crystallization is plotted pattern through optical flat print process and reactive ion etching method (RIE) again, to form the semiconductor island district, shown in Figure 18 (A).Then, adopt the mixed solution of hydrogen fluoride and ammonium fluoride, that is, the etching acid of buffering is removed silicon oxidation diaphragm 504 through the wet corrosion method.One example of this etching acid solution is made up of with ammonium fluoride (40%) weight the high-purity fluorine hydracid (weight is 50%) of the 1 part of weight that is used for the semiconductor manufacturing and the semiconductor manufacturing of 10 parts of weight.This buffering etching acid is with the speed etching oxidation silicon of 70nm/min, with the speed etching silicon of 60nm/min with 15nm/min speed etching aluminium.

Forming thickness through sputter as rake with monox under oxygen atmosphere is the gate oxidation films 505 of 115nm.Under this state, by its ion doping method phosphonium ion is implanted gate oxidation films 505, be present in the removable ion of gate oxidation films inside such as sodium with absorption.The occasion low at Na ion concentration so that work device is not hindered by removable ion need not to carry out ion and implants.In this example, the plasma accelerating potential is 10Kev.Dosage is 2 * 10 ¹⁴Ion/cm ²Place 600 ℃ to carry out thermal treatment in 24 hours lamination.Like this, cause to oxide film with to the infringement of silicon fiml by the collision in the process of plasma doping and recovered.

Then, form the aluminium film and use acid mixture, that is, added the phosphoric acid solution of 5% nitric acid, draw pattern to form grid and interconnection portion 506 thereof with sputtering method.Etching rate is 225nm/min when etching temperature is 40 ℃.Adjust the profile of TFT in this way.At this moment, channel length is 8 μ m, and width is 20 μ m.

N type doped region 507 or say source region and drain region is formed in the semiconductor region with ionic-implantation.In this step, phosphonium ion is implanted as dopant ion.Ion energy is 80Kev, and dosage is 5 * 10 ¹⁵Ion/cm ²As shown in the figure, dopant ion is passed oxide film and is implanted.Adopt the advantage of this implantation to be: continuously again during the crystallization, to keep the smoothness on doped region surface utilizing LASER HEAT TREATMENT.Under the situation that does not adopt this implantation, then during crystallization, a large amount of nucleus are formed on the surface of adulteration area, thereby cause the out-of-flatness that this is surperficial.Like this, structure derived graph 18(B).Certainly, implant operation through this ion, the crystallinity of doped portion is subjected to havoc.These parts roughly present amorphous state or approach amorphous polycrystalline attitude.

Interconnection portion 506 is passed to electric current.Form alumite 508 through anodization in the top surface and the side of grid and interconnection portion thereof.With regard to this anodization, the tartaric ethylene glycol solution with 3% neutralizes with 5% ammonia, so that the pH value of this solution is transferred to 7.0 ± 0.2.Platinum is immersed this solution as negative electrode.Then, TFT is immersed this solution together with this substrate.Interconnection portion 506 is connected to the anode of power supply.Temperature is remained on 25 ± 2 ℃.

In this case, pass to 0.5mA/cm earlier ²Electric current.When voltage reaches 200V, keep this voltage constant, then device is powered.When electric current reaches 0.005mA/cm ²The time, cut off electric current, thereby finish the anodization operation.The thickness of the anodic film of Huo Deing (anodized coating of grid) is about 250nm like this.See shown in Figure 18 (c).

Then the laser instrument of making excimer with KrF carries out LASER HEAT TREATMENT to lamination.For example, sending power density is 350mJ/cm ²10 impacts (shots) laser pulse.We are sure: the crystallinity of amorphous silicon can be recovered so far forth, so that amorphous silicon can be stood the operation of being impacted the caused TFT of laser irradiation by at least one.In order to reduce the possibility that causes defective owing to the laser power fluctuation to greatest extent, need the impact of the laser pulse of sufficient amount.But, too much laser irradiation impact will make throughput rate descend.We find: 10 used impact laser pulses of this example are optimal.

For boosting productivity, LASER HEAT TREATMENT is carried out in atmosphere.Because silicon oxide layer has been formed on the doped region, and problem does not take place.Carry out the Laser Heat Treating in China occasion exposing doped region, in crystallization, brought the oxygen in the atmosphere into doped region, Gu and crystallinity is degenerated.Like this, just, can not obtain to possess the TFT of satisfactory performance.Therefore, require it should carry out LASER HEAT TREATMENT in a vacuum to the lamination that exposes doped region.

In this example, shown in Figure 18 (D), the laser irradiation of being carried out is the oblique lamination that enters.For example, the laser emission angle becomes 10 ° of angles with the substrate normal direction.This angle is determined according to this design instruction of making device.For doped region, can be asymmetrical by the zone of laser crystallization.That is to say that zone 509 and 510 is the doped regions behind sufficient crystallising.The zone 511 is not a doped region, but laser irradiation and crystallization.Zone 512 is doped regions but is not crystalline region.For example, the doped region on Figure 18 (D) right side can be used as and certainly will produce thermionic drain region.

This shows that the shape of device has obtained adjustment.After this, with classic method sputtered silicon oxide, to form layer insulation.Form electrode hole with the well-known optical flat typography, to expose surface or the grid and the interconnection portion surface thereof of semiconductor region.At last, form metallic coating selectively.Like this, just, make a device.

Implement 6

In the TFT of the made according to the present invention, the width in amorphous semiconductor district and the width of each deviate region not only influence voltage endurance capability and the operating speed between cut-off current but also influence leakage and the source region.Therefore, just can make the TFT that satisfies target by goodization of amount that makes the thickness that resembles anodic film or the energy of implanting ions and so on parameter.Yet to adjust this class parameter be impossible to independently being formed at on-chip each TFT usually.For example, a side circuit need form low-speed handing and high voltage bearing TFT and high speed operation and bear the TFT of low pressure on same substrate.According to ultimate principle of the present invention, along with the width of each deviate region or the width in doping amorphous semiconductor district increase, cut-off current reduces and resistance-voltage characteristic improves, but operating speed reduces.

This example has solved this problem, below with reference to Figure 22 (A) to 22(C) planimetric map and Figure 19 (A) to 19(D) sectional view described.This example belongs to makes used circuit in a kind of visual explicit representation, and described in Japanese patent application 296331/1991, this method adopts a p-channel TFT and n-channel TFT de-energisation one pixel.This n-channel TFT needs to get final product but only need bear low-voltage with high speed operation.On the other hand, the p-channel TFT need not high speed operation, but requires its cut-off current must be very low.In some cases, the p-channel TFT must be born high voltage.Therefore, just require the anodic film of n-channel TFT will approach (20 to 100nm), and the anodic film of p channel TFT thick (250 to 400nm).This routine manufacturing step is described below.

With the same in the example 5, substrate 601 is made by healthy and free from worry 7059 glass.Formation-n type doped region 602, p-type doped region 603, gate insulating film 604, grid 606 and interconnection body 607 thereof.Grid 606 and interconnection body 607 thereof are linked interconnection portion 650(Figure 22 (A) and 19(A)).

Grid 606 and interconnection body 607 thereof are passed to electric current.Use the anodization method, form top and the alumite on the side surface 613 and 614 of grid 606 and interconnection body 607 thereof.The anodization step is except that maximum voltage is 50V, with example 5 the same carrying out.The thickness of prepared anodic film is about 60nm(Figure 19 (B) in this step).

Referring now to Figure 22 (B), cut from 651 of interconnection body 650 with the laser ablation method itself and the grid and the body 606 that interconnects thereof are separated.In the case, begin anodization once more, the condition of anodization step is except that maximum voltage increases to 250V, and is the same with first precondition.Owing to do not have electric current to flow through interconnection body 606, so do not observe any variation.But, because electric current flows through interconnection body 607(Figure 19 (c)), be alumite 615 about 300nm so formed thickness on every side at gate interconnection body 607.

Then, with example 5 the same terms under, carry out the LASER HEAT TREATMENT of lamination.In the case, with regard to the n-channel TFT, (left side of Figure 19 (A)-(D)), the width a of amorphous area and deviate region ₁Be so narrow, therefore can ignore.In the place of the surperficial uncoated anodic film of aluminium interconnection body, the interconnection body is badly damaged because of laser radiation.Therefore, be necessary to form anodic film, although it is not thick.On the other hand, with regard to the p-channel TFT, the thickness of (on the right side of Figure 19) anodic film is 300nm.Also having thickness is 150 to 200nm amorphous area.The width a of deviate region ₂Estimate should be 100 to 150nm(Figure 19 (D)).

With the same among Fig. 5, under atmosphere through laser instrument irradiation, etching aluminium interconnection body on desired location.The grid of p-channel TFT is separated with interconnection body 607.Interconnection body 650 also is cut.Form an interlayer dielectric film.Form contact hole, form interconnection body 624 and 611.Like this, just, formed a circuit.

In the circuit of making like this, the deviate region of n-channel TFT and amorphous area are all narrow.Though cut-off current is bigger, operating speed is splendid.On the other hand, it is difficult desiring that the p channel TFT works under high speed.But cut-off current is little.Performance aspect the electric charge that keeps being stored in the pixel capacitance device is fabulous.

Also exist the essential aggregate erection of the TFT with difference in functionality in same on-chip other situation.For example, in a LCD driver, the logical circuit that comprises shift register needs high speed TFT, and output circuit needs high voltage bearing TFT.This routine method can be used to make the TFT that must satisfy this class contradiction requirement effectively.

Example 7

Active matrix circuit of being made up of the n-channel TFT by example 1 method therefor manufacturing is shown among Figure 20.This active matrix comprises select lines 701 and data line 702, is arranged in rows and columns respectively.These lines are made of the aluminium of low-resistivity and apply with thickness is 200 to 400nm alumite-experienced according to anodization step of the present invention Yin this circuit.The width of these lines is 2 μ m.The thickness of these lines is 0.5 μ m.The grid 703 that is used for the TFT of pixel connects with select lines 701.Grid also is coated with aluminium oxide.Below grid, formed semiconductor layer 704.The same with the n-channel TFT of example 1, also there is the n type polycrystalline that is doped with phosphorus.As for the deviate region that constitutes one of characteristics of the present invention, its width is made as about 200 to 400nm.The source of this semiconductor layer is in the contact with data line 702.All drain regions connect with the pixel capacitors 706 that is made of ITO via the aluminium utmost point 705.

Figure 21 is the circuit theory diagrams by an active matrix apparatus of this routine made.Figure 21 (A) illustrates the operational circumstances of this device.Figure 21 (B) illustrates a device operational circumstances that comprises the TFT that makes of the prior art method, uses for contrast.Just as discussed previously, in the matrix circuit of this structure, people are known: when the charging end of capacitor C and grid voltage are interrupted, then capacitor C via the stray capacitance C between grid and drain electrode by capacitive be coupled to select lines.This voltage ratio charging voltage has reduced V.This phenomenon also can observe from the circuit of the n-channel TFT that is connected in parallel.This respect situation has been made detailed description in the patented claim of being submitted to by the applicant 208648/1991.

As shown in Figure 21, by a TFT, that is, or a n-channel TFT, or in the circuit that constitutes of p-channel TFT, this voltage drop is given by following formula only

V＝C _GDV _G1（C _LC+C _GD）

V in the formula _GPoor for the connection voltage of grid voltage and cut-off voltage.For example, do not adopt among the TFT that the self-adjusting operation makes stray capacitance C at one _GDQuite big, so voltage drop V is also big.For addressing this problem, as shown in Figure 21, with holding capacitor C _ADWith the parallel connection of pixel capacitance device, to increase the apparent capacity of pixel capacitance device.Yet this method does not address this problem at all.Just as has been said: caused the new problem such as the aperture reduces.

Even for the device that adopts self-adjusting technology to make, if pixel size is very little, when consequently comparing the effect of parasitic capacitance that can not ignore TFT with pixel capacitance, then this voltage drop meeting causes serious problems.For example, in a diagonal line that cooperates the high definition television projection to use was 3 inches projection screen, pixel capacitance was little of 13fF.On the other hand, in the occasion of being made TFT by the technology that adopts 2 μ m rules, the aspect ratio of interconnection body is big.Therefore, even do not exist overlappingly, in the three-dimensional geometry space, also can produce stray capacitance.This electric capacity reaches several 5F, promptly be the pixel capacitance amount 10% or bigger.

Adopt the active matrix circuit of traditional type TFT to be shown among Figure 21 (A).Obviously, form the harmful effect that correct demonstration is subjected to voltage drop V.Specifically, in order to make the TFT high speed operation, grid is higher than leaks pressure.Usually, making grid approximately double used leakage presses.Therefore if drain voltage is 5V, then grid voltage is 10V or higher.Be negative occasion when making grid voltage at off-state for the operation of improving TFT, grid voltage is variation greatly.Under the situation of Figure 21, leak to press interchange for ± 6V.Grid voltage is+12V to be-4V during off-state when connecting attitude.According to above-mentioned equation, we can try to achieve V _G=16V.Shown in Figure 21 (A), if stray capacitance is 2fF, then voltage drop V is 2V.This just in time is 1/3 drain charge voltage.Certainly, the electric charge that is stored in the pixel discharges by discharging naturally, and therefore, in fact desirable demonstration will be provided is extremely difficult.For avoiding this problem, must sacrifice aperture and holding capacitor is set than (aperture ratio).

On the other hand, can reduce parasitic capacitance greatly according to the present invention.More precisely, this electric capacity can be reduced to below the 0.1fF.Therefore, shown in Figure 21 (B), this voltage drop V almost can ignore.In addition, according to the device cut-off current of the inventive method than the cut-off current of the TFT that makes with the prior art method little about order of magnitude.Therefore, it is much faint that spontaneous discharge is wanted, so the demonstration of near ideal can be provided.

This shows,, formed the anodization layer of an insulation in gate surface according to the present invention.Like this, channel length greater than grid along the vertical shared length of raceway groove.Therefore, formed deviate region on the opposite flank of channel region, this deviate region does not receive the grid electric field or accepts the atomic weak electric field of grid.Equally, can be formed with the phosphorus doping semiconductor region of same advantage.This has reduced back-biased leakage current.Result: saved before this for keeping the necessary electric capacity of electric charge.Being about 20% aperture ratio in prior art can be improved to more than 35%.Therefore, can form the demonstration of better quality.

According to the present invention, deviate region and doping amorphous semiconductor district are determined by the thickness of the anodic film of grid.Therefore, the width in these districts can accurately be controlled between 10 to 100nm.We also are unaware of because of having added this manufacturing step and cause falling greatly of throughput rate.And there is not any factor that can be regarded as the reason that throughput rate reduces.

So far, we are mainly described as object with silicon semiconductor device, but obviously, the present invention also is suitable for adopting germanium, silit, the semiconductor devices of gallium arsenide or other material.

Claims (20)

1, a kind of manufacture method of semiconductor devices, this method may further comprise the steps:

On semiconductor layer, form gate insulation layer;

On described gate insulation layer, form grid part;

Foreign ion is implanted described semiconductor layer, is P type or n type conductance to give it, makes mask with described grid part simultaneously, to form source region or drain region in described semiconductor layer;

Surface portion to the described grid part after the described implantation step carries out anodic oxidation;

After described anodic oxidation step, make described semiconductor devices through heat-treated.

2, a kind of method for making method of semiconductor devices, this method may further comprise the steps:

On semiconductor layer, form gate insulation layer;

On described gate insulation layer, form grid part;

Surface portion to described grid part carries out anodic oxidation;

A kind of foreign ion is implanted described semiconductor layer, to give it is P-type conduction or n type electric conductivity, simultaneously with comprising anodized surface grid part partly, to form source region or drain region in the described semiconductor layer after described anodic oxidation step as mask; And

After described implanting ions step, described semiconductor devices is heat-treated.

3, as method as described in the claim 2, it is characterized in that: after described gate insulation layer forms step, also comprise: the step that phosphorus is imported described gate insulation layer.

4, a kind of manufacture method of semiconductor devices may further comprise the steps:

Form at least two transistorized grids, with lead described grid is electrically connected together each other simultaneously;

Surface portion by making described lead pass to electric current to described grid carries out anodic oxidation;

After described anodic oxidation step, at least one described grid and described lead are electrically kept apart; With

After described isolation step, by described lead is passed to electric current and the anodized surface of grid is partly linked described lead.

5, as method as described in the claim 4, it is characterized in that described grid comprises metal or semiconductor.

6, a kind of semiconductor devices comprises at least two field effect transistors that are arranged on the insulating substrate;

The deviate region of one of wherein said at least two field effect transistors is wider than another deviate region of described at least two field effect transistors.

7, a kind of semiconductor devices comprises: a grid; Source region and drain region; And the channel region that between described source region and drain region, forms, and between described channel region and described grid, has gate insulation layer;

The length of wherein said channel region is greater than the length along the described grid on the described length direction of described channel region.

8, device as claimed in claim 7 is characterized in that: also comprise the oxide layer that is coated on the described gate surface.

9, device as claimed in claim 8 is characterized in that: described oxide layer comprises the anodized coating of described grid.

10, device as claimed in claim 8 is characterized in that: the described length of described channel region has been grown than the described length of described grid and has approximately been doubled described thickness of oxide layer value.

11, device as claimed in claim 7 is characterized in that: also comprise the capacitor that is connected with one of drain region with described source region.

12, device as claimed in claim 11 is characterized in that described capacitor comprises pair of electrodes and an electrooptical modulation layer that is arranged between the described electrode.

13, device as claimed in claim 12 is characterized in that: described electrooptical modulation layer comprises a liquid crystal.

14, device as claimed in claim 12 is characterized in that: described electrode pair comprises indium tin oxide.

15, a kind of semiconductor devices comprises:

The grid of one metal;

Cover the anodized coating of described metal gates;

A pair of first impurity range;

Be arranged on the channel region between described first impurity range, and between described channel region and described metal gates, a gate insulation layer arranged;

A pair of second impurity range, its each adjacent with correspondence one district of described first impurity range respectively; And

With the continuous capacitor of one of described second impurity range.

16, as device as described in the claim 15, it is characterized in that: described capacitor comprises pair of electrodes and is arranged on electrooptical modulation layer between the described electrode.

17, device as claimed in claim 16 is characterized in that: described electrooptical modulation layer comprises a liquid crystal.

18, device as claimed in claim 16 is characterized in that: described electrode pair comprises indium tin oxide.

19, as device as described in the claim 15, it is characterized in that: described first impurity range is lower than the crystallinity of described second impurity range.

20, as device as described in the claim 15, it is characterized in that: described first impurity range is lower than the specific ionization of described second impurity range.

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