CN1084931C - Method of programming flash memory cell - Google Patents
Method of programming flash memory cell Download PDFInfo
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- CN1084931C CN1084931C CN97113084A CN97113084A CN1084931C CN 1084931 C CN1084931 C CN 1084931C CN 97113084 A CN97113084 A CN 97113084A CN 97113084 A CN97113084 A CN 97113084A CN 1084931 C CN1084931 C CN 1084931C
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- 238000000034 method Methods 0.000 title claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 230000005684 electric field Effects 0.000 claims abstract description 18
- 239000002784 hot electron Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract 4
- 239000012535 impurity Substances 0.000 claims description 4
- RWSOTUBLDIXVET-UHFFFAOYSA-N Dihydrogen sulfide Chemical compound S RWSOTUBLDIXVET-UHFFFAOYSA-N 0.000 abstract 1
- 229940101532 meted Drugs 0.000 abstract 1
- 150000003376 silicon Chemical class 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000005086 pumping Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
Abstract
The present invention provides a meted of programming a flash memory cell which can improve the programming efficiency and characteristics and easily implement the low power device without changing the structure of the split-gate type flash memory cell. A depletion area formed at a source region is extended from the surface portion of a silicon substrate to the bottom thereof, a minority carrier is produced at a trap center existing at the extended depletion area, and the produced minority carrier receives energy from a high electric field area formed at the silicon substrate between a select gate and floating gate and is changed into a hot electron by a voltage applied to the drain region. Then, the hot electron is injected into the floating gate by a vertical direction electric field formed by a high potential voltage applied to a control gate.
Description
The present invention relates to a kind of method of the flash memory of programming, particularly relate to a kind of method that can reduce its size and realize the programming flash memory of a low power devices.
Usually, the quick storage device such as a quick electric erasable and read-only memory unit able to programme (EEPROM) has the electric function of programming and wiping and is divided into folded grid (stack-gate) type and splits grid (split-gate) type according to the shape of the gate electrode that is constituted.
Conventional folded grid type and formation and the work of splitting grid type flash memory will be described below.
As shown in Figure 1, in the folded grid type flash memory of this routine, order stack is equipped with a tunnel oxide film 4, floating grid 5, dielectric film 6 and control gate 7 on a silicon chip 1, and the both sides of floating grid 5 form source region 2 and drain region 3 respectively in this silicon chip 1.The programming and the erase operation of above-mentioned this flash memory are as described below.
For an information is programmed into this flash memory, be about to an electric charge and charge into floating grid 5, shown in Fig. 2 A general+12V be added to control gate 7 ,+5V is added to drain region 3 and ground voltage is added to source region 2 and silicon chip 1.Subsequently, thus since control gate 7 be added with high voltage and in this silicon chip 1, below floating grid 5, formed a raceway groove, so and because drain region 3 is added with voltage 3 sides form high electric field region in the drain region in this silicon chip 1.At this moment, existing portions of electronics receives from the energy of high electric field region forming hot electron in this raceway groove, and utilizes owing to be added to the formed vertical direction electric field of high voltage of control gate 7 the portion of hot electronics is injected floating grid 5 by this tunnel oxide film 4.Therefore, make the threshold voltage (V of this flash memory owing to thermionic injection
T) to improve.
In order to wipe the information in this flash memory, will charge stored discharge in floating grid 5, shown in Fig. 2 B, with ground voltage be added to control gate 7 and silicon chip 1 ,+12V is added to source region 2 and floated in this drain region 3.Subsequently,, this F-N (fowler-nordheim) tunnel(l)ing is moved to source region 2 because injecting the electronics of floating grid 5, so the threshold voltage V of this memory cell
TBe reduced.
By this tunnel(l)ing that appears at partly between source region 2 and the floating grid 5 erase operation of flash memory is achieved.Therefore, be difficult to constantly control the electron amount that moves to source region 2, and floating grid 5 occur, just under the situation that the characteristic of this tunnel oxide film 4 degenerates, (over erasure) occurred wiping not by the phenomenon of electrical reset at erase operation.This mistake has been wiped the effect that the operating characteristic that causes this device degenerates.
On the other hand, splitting in the grid type flash memory as shown in Figure 3, first dielectric film 14, floating grid 15, second dielectric film 16 and control gate 17 sequentially are layered on the silicon chip 11, and the 3rd dielectric film 18 is laminated on this overall structure that comprises this stepped construction with selection grid 19.Below floating grid 15, be formed with drain region 13 in the silicon chip 11 of a side, and in the silicon chip 11 of a preset distance, be formed with source region 12 with floating grid 15.
The following describes the gate electrode and that includes this stepped construction is selected the programming of transistorized flash memory and the operation of wiping.
For an information is programmed into this flash memory, just an electric charge is charged to floating grid 15, shown in Fig. 4 A general+12V be added to control gate 17 ,+1.8V be added to select grid 19 ,+5V is added to drain region 13 and ground voltage is added to source region 12 and silicon chip 11.Subsequently, form one owing to be added to the voltage of these selections grid 19 in the silicon chip 11 below selecting grid 19 and select raceway groove, and owing to the high voltage that is added to control gate 17 formation one raceway groove in the silicon chip 11 below floating grid 15.The leakage current of 20-30 μ A flow through this selection raceway groove and formation one high electric field region in the raceway groove floating grid 15 below simultaneously.At this moment, thereby the energy that the portions of electronics that exists in this raceway groove receives from this high electric field region becomes hot electron, and by making the portion of hot electronics inject floating grid 15 through first dielectric film 14 owing to be added to the formed vertical direction electric field of high voltage of control gate 17.Therefore, the threshold voltage V of this flash memory
TBe raised.
In order to wipe the information of programming at this flash memory, just, in order to make in floating grid 15 the stored charge discharge, shown in Fig. 4 B general-12V be added to control gate 17 ,+5V is added to drain region 13, ground voltage is added to selection grid 19 and silicon chip 11 and is floated in source region 12.Subsequently,, this F-N tunnel(l)ing moves to source region 12 owing to making the electronics of injecting floating grid 15, thereby the threshold voltage V of this memory cell
TReduce.
This read operation of splitting grid type flash memory is to carry out under the condition that this selection transistor is switched on.Thereby, have the advantage that phenomenon can not occur wiping.But because a leakage current can occur under the situation that the length of selecting grid is reduced, so the size of this memory cell is difficult to reduce.
In addition, the high voltage of 12V or a little higher than 12V is added to folded grid type and splits the control gate of grid type flash memory, and this high voltage provided by a charge pump circuit, and the supply voltage that this circuit will this about 5V rises to this high voltage.Therefore, the flash memory that includes this memory cell has following problem, at first need the time that is used to programme of a length and be used for that because of the more time of needs supply voltage is risen to this high-tension pumping to operate, so this power consumption is bigger, secondly, because the thickness of formed second dielectric film between floating grid and the control gate must greater than the thickness of first dielectric film more than two times to guarantee the reliability of this device, so bring difficulty to manufacture process.
In addition, need the low power memory spare of a kind of 3.3V of use or 2.5V low-voltage recently, and proposed a kind of when programming reduce be added to the drain region voltage method as the method that realizes this low power memory spare.But under situation about making in this way, the structure or the drain region that must change this memory cell connect with the programming characteristic of maintenance with the identical level of conventional memory spare of using supply voltage (for example 5V).Therefore, in manufacture process, understand the problem that the problem such as changing occurs and treatment step can occur increasing owing to this variation.
In addition, in the other method that realizes low power memory spare, a kind of increase by one charge pump circuit in this memory device is arranged so that when programming, will be added to the voltage in drain region and rise to the method that is higher than 5V.But the problem that this method has is can not the drain region current potential be improved by the electric charge pumping owing to 30 μ A or higher leakage current occurring in this programming time.
Therefore, the purpose of this invention is to provide a kind of method of the flash memory of programming, it can change the structure of splitting grid type flash memory and just can reduce the size of flash memory and also can realize low power devices simultaneously.
To achieve these goals, one aspect of the present invention is according to the voltage that is added to silicon chip, source and drain region, floating grid, control gate and selection grid respectively, and the minority carrier that the place, trap center of a formed depletion region produces in a silicon chip is become a hot electron.
To achieve these goals, another aspect of the present invention is according to the voltage that is added to respectively on silicon chip, source region, drain region, floating grid, control gate and the selection grid, a formed depletion region is extended to the bottom of this silicon chip by the surface portion from silicon chip in a source region, thus a minority carrier that produces at the trap center that the depletion region place of being extended exists receive from the silicon chip of selecting between grid and the floating grid on the energy of formed high electric field become a hot electron.
For achieving the above object, another aspect of the present invention be the high voltage that will be higher than supply voltage be added to control gate, with this supply voltage be added to the drain region, will be lower than supply voltage and above Ground a voltage of voltage be added to and select grid, ground voltage to be added to silicon chip and floated in the source region, make the minority carrier that the trap center of a formed depletion region is produced on this silicon chip become a hot electron and this hot electron is injected floating grid like this.
To achieve these goals, another aspect of the present invention be a high voltage that will be higher than supply voltage be added to control gate, will be higher than supply voltage and be lower than this high-tension voltage be added to the drain region, will be lower than supply voltage and above Ground a voltage of voltage be added to and select grid, ground voltage to be added to silicon chip and floated in the source region, make the minority carrier that the trap center of formed depletion region produces in described silicon chip become a hot electron like this.
Read with reference to following accompanying drawing to the detailed description that this embodiment did after, will have gained some understanding to other purpose of the present invention and advantage.
Fig. 1 is a sectional view of conventional folded grid type flash memory;
Fig. 2 A and 2B are the explanation folded grid type flash memory programming shown in Figure 1 and the sectional view of erase operation;
Fig. 3 is the sectional view that routine is split grid type flash memory;
Fig. 4 A and 4B are the explanation sectional views that splits programming of grid type flash memory and erase operation shown in Figure 3;
Fig. 5 is programme according to the present invention sectional view of method of this flash memory of explanation; With
Fig. 6 A and 6B are the charts of key diagram 5.
The present invention is the improvement of programming shown in Figure 3 being split the conventional method of grid type memory cell.Just, the conventional programming method is used a kind of like this method, the energy of the high electric field region that next comfortable this raceway groove place of the minority carrier reception that flies into from this source region in the method forms is so that become hot carrier, and this hot carrier is injected into floating grid (channel hot electron injection), but, programmed method of the present invention uses a large amount of (bulk) injection of hot electrons methods, and the existing trap of the depletion region center that forms at this silicon chip place produces a minority carrier and become a hot electron so that be injected into floating grid in the method.The programme method of flash memory of a large amount of injection of hot electrons used according to the invention is described now in conjunction with Fig. 5.
Fig. 5 is the sectional view of the method for explanation programming flash memory of the present invention, and wherein, the overall structure of this acceleration memory cell is identical with the structure of the general flash memory shown in Fig. 3, has therefore omitted the description to it.
At first, for an information is programmed into this flash memory, just, for an electric charge is charged into floating grid 15, and will be approximately as shown in Figure 5+supply voltage of 5V is added to drain region 13, a high voltage that is higher than being approximately of supply voltage+12V is added to control gate 17 and ground voltage is added to silicon chip 11.And with one be lower than supply voltage but above Ground the voltage of being approximately of voltage+1.8V be added to and select grid 19 and source region 12 is changed to floating state.Afterwards and since be added to control gate 17 high voltage and in silicon chip 11 below floating grid 15 formation one raceway groove 20, and owing to be added to the electromotive force in drain region 13 and form first-class Potential distribution at these raceway groove 20 places.At this moment, because source region 12 is to be in floating state, the body capacity effect (body effect) that causes owing to the high potential potential barrier in this drain region 13 makes that in silicon chip 11 threshold voltage of formed selection raceway groove increases below these selection grid 19.Therefore since be added to the voltage of selecting grid 19 (+1.8V) can not realize this raceway groove transoid, the formed depletion region 30 of 12 sides is extended its bottom from the surface portion of silicon chip 11 in the source region like this.At this moment, for the full-size of this depletion region 30, the concentration that is injected into the impurity in source region 12 must be higher than the concentration of the impurity that injects silicon chip 11 basically.
This electronics of the minority carrier that the trap center that exists in depletion region 30 is produced is so extended, and receive the energy of selecting formed high electric field region between grid 19 and the floating grid 15 on comfortable this silicon chip 11 owing to be added to the minority carrier that voltage produced in drain region 13, and become a hot electron.Subsequently, owing to be added to the electric field of the formed vertical direction of high voltage of control gate 17, the threshold voltage of this flash memory is enhanced there, and hot electron is injected into floating grid 15 by first dielectric film 14.
Fig. 6 A shows in programming time basis and is added to the voltage V in drain region 13
dVariation and make the threshold voltage V of this flash memory
TPThe chart that changes, curve A is represented the variations in threshold voltage of conventional programming method, curve B has been represented variations in threshold voltage of the present invention.As shown in Fig. 6 A, under the situation of using programmed method of the present invention, it is bad that this programming characteristic becomes, still, the situation of the programming operation performed with using conventional method is compared owing to the intensity that is added to the formed electric field of voltage in drain region 13 is increased, and institute is so that programming efficiency improves.
Fig. 6 B shows the voltage V that selects grid 19 according to being added to
sVariation and make the chart of the threshold voltage variation of this flash memory, curve C is represented the variations in threshold voltage of conventional programming method, curve D is represented the variations in threshold voltage of programmed method of the present invention.Shown in Fig. 6 B, under the situation of using programmed method of the present invention, as voltage V
sThis programming characteristic is enhanced when being added to selection grid 19, and this is because make the size of depletion region increase and because the cause of the generation rate of minority carrier increase along with the increase that is added to the voltage of selecting grid 19.But, be added to the voltage V that selects grid 19
sBe increased to be approximately+1.5V or higher situation under, though be increased in the size of the depletion region of selecting channel part to form, owing to the intensity that is added to the formed electric field of voltage in drain region 13 but reduces.Therefore, thermionic generation rate reduces rapidly, thereby this programming efficiency descends.
Therefore, for programming efficiency and characteristic are brought up at utmost, preferably keep being added to the voltage of selecting grid 19 and the voltage that is added to drain region 13 by the raising of use charge pump circuit.According to the present invention,, do not have leakage current and make it can use charge pump circuit because floated in this source region 12 of programming time.
On the other hand, bring up at the voltage that will be added to drain region 13 and to be higher than under supply voltage+7V or the higher situation, if will be higher than supply voltage approximately+8V is added to control gate 17 to the high voltage of+11V then can obtains identical programming characteristic, and in this case, because be added to the voltage of control gate 17 is to be lower than+12V, so pumping time reduces thereby the programming time reduces.Therefore, can obtain to reduce the effect of the thickness of formed second dielectric film 16 between control gate 17 and floating grid 15.Its result is if use need not change this structure of splitting grid type flash memory and just can easily realize low power devices according to the method for programming flash memory of the present invention.
In addition, the flash memory that is programmed so also has such advantage, and promptly it can be wiped by wiping this conventional method of splitting grid type flash memory, thereby has omitted the explanation of the operation of wiping this flash memory.
As mentioned above, according to the present invention, be freed from the voltage that is added to the drain region and the energy of the high electric field region that forms at the silicon chip place of selecting between grid and the floating grid becomes hot electron by producing a minority carrier at the existing trap of the formed depletion region that is extended of source region side center and receiving by the minority carrier that will be produced, and, can easily realize once having and having improved the low power devices of programming efficiency and characteristic and need not change the size that this structure of splitting grid type flash memory can reduce this flash memory effectively by making this hot carrier inject this floating grid owing to the high voltage that is added to control gate forms the vertical direction electric field.
In the explanation in front, though the most preferred embodiment of particularity is described to having to a certain degree, it has only illustrated principle of the present invention.Should be appreciated that the present invention is not limited in this most preferred embodiment disclosed and explanation here.Therefore, the modification that within the spirit and scope of the present invention all are suitable is all as further embodiment of the present invention.
Claims (3)
1. the method for the flash memory of programming, described flash memory comprises silicon substrate, source region and drain region, floating grid, control gate and selection grid, it is characterized in that being added to described control gate when a voltage that is higher than supply voltage, described supply voltage is added to described drain region, one be lower than described supply voltage and above Ground the voltage of voltage be added to described selection grid, and when floated in described source region, the depletion region that forms in place, described source region is extended to the bottom of silicon chip by the surface from described silicon chip, the energy of the high electric field region that the silicon chip place between next comfortable selection grid of the minority carrier reception that the trap center that exists in the described depletion region place that is extended is produced and the floating grid forms is so that it becomes hot electron, and, according to being applied to described silicon substrate respectively, described source region, described drain region, described floating grid, voltage on described control gate and the described selection grid, by formed electric field in vertical direction, described hot electron is injected into floating grid.
2. the method for claim 1, the concentration of wherein injecting the impurity in described source region is higher than the concentration of the impurity of injecting described silicon chip.
3. the method for claim 1, wherein said minority carrier is an electronics.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960009730A KR100217900B1 (en) | 1996-04-01 | 1996-04-01 | Programming method of a flash memory cell |
| KR9730/96 | 1996-04-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1168539A CN1168539A (en) | 1997-12-24 |
| CN1084931C true CN1084931C (en) | 2002-05-15 |
Family
ID=19454775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97113084A Expired - Fee Related CN1084931C (en) | 1996-04-01 | 1997-04-01 | Method of programming flash memory cell |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5867426A (en) |
| EP (1) | EP0800179B1 (en) |
| JP (1) | JP2963882B2 (en) |
| KR (1) | KR100217900B1 (en) |
| CN (1) | CN1084931C (en) |
| DE (1) | DE69719584T2 (en) |
| GB (1) | GB2311895B (en) |
| TW (1) | TW334616B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100207504B1 (en) * | 1996-03-26 | 1999-07-15 | 윤종용 | Non-volatile memory device, its making method and operating method |
| KR100276653B1 (en) | 1998-08-27 | 2001-01-15 | 윤종용 | A method of driving a split gate type nonvolatile memory cell and a method of driving a semiconductor memory device including the cells |
| KR100293637B1 (en) | 1998-10-27 | 2001-07-12 | 박종섭 | Drain Voltage Pumping Circuit |
| US6638821B1 (en) * | 2002-01-10 | 2003-10-28 | Taiwan Semiconductor Manufacturing Company | Flash EEPROM with function of single bit erasing by an application of negative control gate selection |
| US7057931B2 (en) * | 2003-11-07 | 2006-06-06 | Sandisk Corporation | Flash memory programming using gate induced junction leakage current |
| TW200607080A (en) * | 2004-08-02 | 2006-02-16 | Powerchip Semiconductor Corp | Flash memory cell and fabricating method thereof |
| US8369155B2 (en) * | 2007-08-08 | 2013-02-05 | Hynix Semiconductor Inc. | Operating method in a non-volatile memory device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5280446A (en) * | 1990-09-20 | 1994-01-18 | Bright Microelectronics, Inc. | Flash eprom memory circuit having source side programming |
| EP0676811A1 (en) * | 1994-04-11 | 1995-10-11 | Motorola, Inc. | EEPROM cell with isolation transistor and methods for making and operating the same |
| US5491657A (en) * | 1995-02-24 | 1996-02-13 | Advanced Micro Devices, Inc. | Method for bulk (or byte) charging and discharging an array of flash EEPROM memory cells |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3004043B2 (en) * | 1990-10-23 | 2000-01-31 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| BE1004424A3 (en) * | 1991-01-31 | 1992-11-17 | Imec Inter Uni Micro Electr | TRANSISTOR STRUCTURE AND for erasable programmable memories. |
| US5274588A (en) * | 1991-07-25 | 1993-12-28 | Texas Instruments Incorporated | Split-gate cell for an EEPROM |
| US5317179A (en) * | 1991-09-23 | 1994-05-31 | Integrated Silicon Solution, Inc. | Non-volatile semiconductor memory cell |
| JP2749449B2 (en) * | 1992-12-28 | 1998-05-13 | ユー、シイ−チャン | Non-volatile semiconductor memory cell |
| US5324998A (en) * | 1993-02-10 | 1994-06-28 | Micron Semiconductor, Inc. | Zero power reprogrammable flash cell for a programmable logic device |
| JP3105109B2 (en) * | 1993-05-19 | 2000-10-30 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| US5349220A (en) * | 1993-08-10 | 1994-09-20 | United Microelectronics Corporation | Flash memory cell and its operation |
| US5511021A (en) * | 1995-02-22 | 1996-04-23 | National Semiconductor Corporation | Method for programming a single EPROM or flash memory cell to store multiple levels of data that utilizes a forward-biased source-to-substrate junction |
-
1996
- 1996-04-01 KR KR1019960009730A patent/KR100217900B1/en not_active IP Right Cessation
-
1997
- 1997-03-28 TW TW086104001A patent/TW334616B/en not_active IP Right Cessation
- 1997-03-31 JP JP7936197A patent/JP2963882B2/en not_active Expired - Fee Related
- 1997-04-01 GB GB9706573A patent/GB2311895B/en not_active Expired - Fee Related
- 1997-04-01 CN CN97113084A patent/CN1084931C/en not_active Expired - Fee Related
- 1997-04-01 US US08/831,044 patent/US5867426A/en not_active Expired - Lifetime
- 1997-04-01 DE DE69719584T patent/DE69719584T2/en not_active Expired - Lifetime
- 1997-04-01 EP EP97105431A patent/EP0800179B1/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5280446A (en) * | 1990-09-20 | 1994-01-18 | Bright Microelectronics, Inc. | Flash eprom memory circuit having source side programming |
| EP0676811A1 (en) * | 1994-04-11 | 1995-10-11 | Motorola, Inc. | EEPROM cell with isolation transistor and methods for making and operating the same |
| US5491657A (en) * | 1995-02-24 | 1996-02-13 | Advanced Micro Devices, Inc. | Method for bulk (or byte) charging and discharging an array of flash EEPROM memory cells |
Also Published As
| Publication number | Publication date |
|---|---|
| DE69719584T2 (en) | 2004-04-08 |
| GB2311895B (en) | 2001-03-14 |
| KR100217900B1 (en) | 1999-09-01 |
| CN1168539A (en) | 1997-12-24 |
| KR970072447A (en) | 1997-11-07 |
| EP0800179A2 (en) | 1997-10-08 |
| GB2311895A (en) | 1997-10-08 |
| US5867426A (en) | 1999-02-02 |
| GB9706573D0 (en) | 1997-05-21 |
| TW334616B (en) | 1998-06-21 |
| DE69719584D1 (en) | 2003-04-17 |
| EP0800179A3 (en) | 1999-04-28 |
| EP0800179B1 (en) | 2003-03-12 |
| JP2963882B2 (en) | 1999-10-18 |
| JPH1032272A (en) | 1998-02-03 |
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