CN1106688C - 用于集成电路的互连结构及其形成方法 - Google Patents

用于集成电路的互连结构及其形成方法 Download PDF

Info

Publication number
CN1106688C
CN1106688C CN95196649A CN95196649A CN1106688C CN 1106688 C CN1106688 C CN 1106688C CN 95196649 A CN95196649 A CN 95196649A CN 95196649 A CN95196649 A CN 95196649A CN 1106688 C CN1106688 C CN 1106688C
Authority
CN
China
Prior art keywords
layer
conductive layer
interconnection line
interconnection
path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN95196649A
Other languages
English (en)
Other versions
CN1168739A (zh
Inventor
A·M·迈尔斯
P·K·查维特
T·A·莱特森
杨事宁
P·白
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1168739A publication Critical patent/CN1168739A/zh
Application granted granted Critical
Publication of CN1106688C publication Critical patent/CN1106688C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

Abstract

一种防止通路分层的高性能和高可靠度的新型互连结构。本发明的互连结构包括伸进并底割下层互连线(202)、将连接通路(212)固定在互连线(202)中的连接通路(212)。

Description

用于集成电路的互连结构及其形成方法
发明背景
1.发明领域
本发明涉及半导体集成电路领域,特别是涉及集成电路的新型互连结构及其制造方法。
2.相关工艺讨论
现代集成电路完全由数百万个诸如晶体管,电容和电阻等的有源和无源器件组成。这些器件最初是互相分离的,后来相互连接在一起形成功能电路。互连结构的质量严重地影响到制成电路的性能和可靠性。互连越来越决定了现代超大规模集成(ULSI)电路的密度和性能极限。
图1a是现在用于半导体工业中的互连结构的剖面图。在硅衬底或阱102中形成的是诸如晶体管和电容的有源器件(未画出)。通常是铝或铝合金的互连线104和106用来连接有源器件形成功能电路。金属互连线104,106和衬底102分别由中间层电介质(ILDs)108和110电绝缘地隔开。金属互连线104和106之间通过使用通常为钨的金属通路或填料112形成电路连接。
与图1a中的互连结构及其制造方法有关的一个严重的可靠性问题是通路分层。通路分层是如图1b中所示的通路与下层金属连接之间的有形分离114。连接通路和下层金属连接之间的有形分离会使所形成的电路开路而导致器件或电路完全失效。
虽然还不是完全清楚,但通路分层很可能是以下几个因素引起的,包括:ILD、互连线和通路材料中的大应力,受沾污的金属互连/填料界面,以及薄弱的互连/ILD及互连/填料界面。在半导体器件的寿命中,器件要受到显著的热变化的影响。例如,在器件的整个生产过程和封装中会遇到各种温度条件。另外,在器件工作中,大电流密度流过通路和互连线会导致高阻区,比如通路和下层连接之间的界面等温度升高。
金属连接、通路和绝缘层具有不同的热膨胀系数导致的结果是,器件处于温度循环变化中时通路连接会受到大量的应力作用。另外,在通路金属化之前,包含在通路腐蚀过程中形成的氟化物和氧化物的各种残留物通常会留在界面。这些氟化物和氧化物通常是易脆物质,当受到极大的热应力时,会破裂而导致通路分层。
因此,需要一种能阻止通路分层的新型互连结构及其制造方法。
发明概述
描述了一种能防止通路分层的新型互连结构。多层互连包含铝化钛电子迁移分流层,铝合金体导体,和铝化钛盖层形成在半导体衬底的绝缘层上。第二绝缘层形成在多层互连的周围和上面。包含钨的通路连接具有有着第一宽度的第一部分,它穿过绝缘层和互连线的盖层,以及宽于第一部分的第二部分,它形成在体导体上和盖层之下,以使通路连接锁定在互连线上。
附图简述
图1a是现有工艺的互连结构的剖面示意图。
图1b是现有工艺的互连结构中的已分层通路的示意图。
图2是本发明的新型互连结构的优选实施例的剖视图。
图3a是一剖视图,所示的半导体衬底具有形成于其上的绝缘层和一组形成于绝缘层上的金属层。
图3b是表示在图3a的衬底上的金属层中形成图案构成互连线的剖视图。
图3c是表示在图3b的衬底上形成通路开口的剖视图。
图3d是表示在图3c的衬底上的互连线中形成锚定开口(anchoropening)的剖视图。
图3e是表示在图3d的衬底中形成通路连接的剖视图。
图3f是表示在图3e的衬底中形成第二互连的剖视图。
发明详述
本发明描述由USI制造工艺制造的新型高密度,高可靠度和高性能的互连结构。在以下描述中为了完全理解本发明,陈述了诸如具体材料,工艺,和设备等具体细节。但是很明显,对于本领域中熟练人员,没有这些具体细节本发明也能实现。另一实例中,为了不必要地使本发明模糊不清,熟知的半导体制造材料,工艺和设备没有详细陈述。
图2中示出了本发明新型互连结构的优选实施例的剖视图。本发明的互连结构200包含形成在绝缘层204上的第一多层互连。绝缘层204依次形成在半导体衬底206上。半导体衬底206包含一组有源和无源器件,比如晶体管,电容器和电阻等,它们由本发明中的互连结构连接在一起而形成功能电路比如微处理器和存储器件等。多层互连线202优选地包含优选为难熔金属化合物的导电盖层226,优选为铝合金的体导体224,和优选为难熔金属化合物的电子迁移分流层222。另外,如果需要,诸如TiN的抗反射镀膜(ARC)228可以形成在互连线202上。第二互连线208,优选为与互连线202相似的多层互连线,通过绝缘体或中间层电介质(ILD)210与第一互连线202隔离开,并且电绝缘互连线202通过通路连接212与互连线208电连接。
本发明的重要特点是通路连接212锚定于互连线202中。通路连接212具有穿过ILD210,ARC228和盖层226的第一狭窄部分214。通路连接212还包含形成在体导体224中、并钻蚀互连线202的盖层226的第二较宽部分216。因为盖层226和体导体224之间的结合很牢,通路连接212就稳固地锚定在互连线202中。通路连接212说是钻蚀互连线202是因为通路连接212具有的位于互连线202中的上部214比位于互连线202中的通路连接212的下部216细。通过锚定通路连接212于互连线202中,没有必要依靠通路连接212和下层的互连线202之间的强机械结合来防止通路分层。通过锚定通路连接212于互连线202中,通路分层在本发明中得以防止。
根据本发明,通路连接212中的锚定部分216完全形成于互连线202中并被之包围,而不是简单地依靠于互连线202的外表面上。另外,根据本发明,盖层226的形成厚度足以提供足够的机械力来防止在以后的器件工艺或器件工作中通路连接212从互连线202上脱离或分层。厚度为300~1500的盖厚能提供足够的机械力来防止通路分层。
另外,根据本发明,通路连接212的锚定部分216以足够的量钻蚀盖层226以使通路连接212稳固定位。少量的钻蚀将导致弱的机械锚定,同时太大的钻蚀将不利地影响通路封装密度。500到1500的钻蚀盖层212可提供足够的通路连接锚定,同时依然允许有穿过半导体器件的高密度通路布局。
本发明的优选实施例中一个重要特点是,使用铝合金(铝-铜)层作为体导体224和使用难熔金属-铝层作为盖层226。因为铝合金具有低电阻率以及它们的工艺技术在半导体工业中是熟知的,所以铝合金是体导体224的理想选择。另外更重要的是通过使用难熔金属/铝盖层226,盖层226能与体导体224起化学反应并结合在一起。通过使盖层226和体导体224起反应而结合在一起,与使用非反应的盖层相比,盖层具有特别强的机械强度。因为盖层226与体导体224具有强的机械结合,在通路连接212和互连线202之间可形成牢固的界面。
本发明优选实施例的另一个重要特点是使用难熔金属盖层226和难熔金属电子迁移分流层222。应理解的是,难熔金属对电子迁移有很高的电阻。通过在通路连接212的上面和下面分别提供难熔金属导体226和222,可得到连续的分流层而防止互连中的电子迁移失效。应理解的是难熔金属比铝金属层具有更高的电阻,所以在电子迁移阻抗和互连电阻之间必须进行权衡。厚为300~1000的难熔金属电子迁移分流层222可在电学性能和可靠性之间具有良好的平衡。
另外,根据本发明的优选实施例,锚定物216在盖层226下扩展到一定深度,这足够使通路连接212稳固定位。但是,锚定物216优选地并不扩展进电子迁移分流层222中,这样互连线202的电子迁移电阻并不受到妨碍,延伸1000-3500进入约4000体导体中的通路连接就足够了,但是,锚定物216扩展入体导体224的精确深度是不重要的,只要锚定物216扩展入体导体224的深度足以提供足够的机械强度来锁定通路连接212到位。
应理解的是,根据本发明的新型通路外形,通路连接212和互连线202之间具有很大的界面接触面积。通路连接212与盖层226的垂直侧面、盖层226的下底面具有界面接触,还和体导体224之间有大面积接触。通路连接212和互连线202之间的大界面接触面积改善了本发明的互连结构的性能和可靠性。大界面接触面积通过在通路连接212和互连线202之间提供大的机械结合表面积而改善了可靠性。另外,大界面接触面积通过减小通路连接212和互连线202之间的接触电阻而改善了性能。
图3a-3f表示本发明的优选互连结构。参照图3a,给出了半导体衬底,它包括但并不限于硅和砷化镓衬底。一组诸如晶体管和电容等的器件通过熟知的技术形成在衬底302之上和之中。接下来绝缘层304或ILD,诸如掺杂或未掺杂的二氧化硅通过熟知的技术形成在衬底302上。
接着,在绝缘体304上形成多层互连线。在多层互连的形成过程中,首先,约200厚的钛(Ti)层306通过诸如溅射等熟知技术在绝缘体304上形成。虽然钛层是优选的,其它难熔金属层也能使用。接着,约5200厚的包含约1%铜的铝合金层308通过诸如溅射等熟知技术形成在钛层306上。虽然由于铝合金层的低电阻率和它们熟知工艺,铝合金层是优选的,但应理解其它低电阻率材料也可在互连线中作为体导体。接下来,约200厚的钛层310在铝合金层308上形成。虽然钛是优选的,如果需要其它难熔金属层也可使用。如果需要,诸如氮化钛(TiN)的抗反射镀膜312在钛层310上形成。
接着,如图3b所示,钛层306,铝合金层308,钛层310,和氮化钛层312通过熟知的光刻和腐蚀工艺制图形成互连线306。氮化钛抗反射镀膜312有助于进行可制造的光刻工艺。诸如使用包含化学剂BCl3和Cl2的反应离子刻蚀(RIE)等熟知的腐蚀技术可用于形成互连线305图案。
接着,如图3b所示,诸如掺杂的二氧化硅的中间层电介质(ILD)314在多层互连线305的上面和周围形成。诸如CVD等熟知的技术可用来形成ILD314,这时ILD314优选地通过诸如化学机械抛光或深腐蚀等熟知技术平面化而形成平整的顶表面。应理解ILD314在平整化后应该足够厚以便在互连线305与下级金属化之间提供足够的电绝缘。约10,000厚的二氧化硅层可提供合适的绝缘。
应理解的是,根据本发明的优选实施例,钛层310直接形成在铝合金层308上。当钛和铝被加热足够时,发生反应形成铝化钛(TiAl3)。根据本发明,优选的是在通道腐蚀之前,在钛层306和钛层310与铝合金层308之间产生完全反应或基本完全反应而分别形成铝化钛层307和309。这可以通过在金属成形后的高温过程实现,比如在ILD淀积,ILD退火和高温粉尘清除等过程中。虽然钛层306和310的初始厚度只为约200,但因为反应消耗了铝合金层3 06中的铝而导致铝化钛层厚度大于800。
应当指出通过形成铝化钛盖层,盖层309牢固地连接在下层铝合金层308上,提供了附加的机械强度,可防止盖层309和从后形成的锚定通路连接从铝合金层308上脱离。约300-1500厚的铝化钛就可提供足够的强度来防止通路分层。虽然铝化钛化合物对盖层309是优选的,其它难熔金属/铝化合物也能使用。
应理解的是,所有的钛层306和310不必都在这时参加反应。但是,钛层310和铝合金层308之间必须发生足够的反应以产生足够厚的铝化钛层,以便提供足够的防止通路分层的机械强度。任何未反应的Ti可在完成器件制造的后序的标准和熟知工艺中完全反应,比如形成ILD,退火,固化,清洁、溅射,和高温氢钝化处理等。
接着,如图3c所示,形成通孔穿过ILD314,氮化钛层312,和铝化钛层309。首先,在平整过的ILD314上形成光刻胶层316,并通过熟知的光刻工艺形成图案,以决定通孔316形成的位置。接着,ILD34,氮化钛312和铝化钛层309的暴露部分被腐蚀。通路孔306必须腐蚀至达到铝合金层308。带包含CF4和CHF3的化学试剂的反应离子刻蚀(RIE)可用来形成通路孔316。
为了使本发明的工艺可制造,准确控制穿过衬底的通路腐蚀深度是重要的。重要的是保证衬底或晶片上的所有通路其腐蚀都停止于铝合金层308。这可通过几个不同的方法实现。一个用于本发明的优选实施例的方法是化学-机械抛光ILD314以形成非常平整的上表面。这种方法中,即使氧化物淀积和抛光速率有变化,衬底上的所有通路在给定层中具有基本相同的深度。
第二种可使用的技术是在通路孔腐蚀之前使氮化钛和钛盖层312和310分别尽可能薄。薄的盖层减少了到铝合金层308所需的特别长的通路腐蚀。为了使盖层相当薄,建议在金属形成后,通路腐蚀之前处理温度保持尽可能低以防止形成较厚的铝化钛层,这样通路腐蚀不需要特别长才能到达铝合金层308。但是,如果使用这种技术,在形成锚定孔之前必须进行足够的反应以便有足够的盖层来锁定后序形成的通路到位。
接着,如图3d所示,在互连线305中形成锚定孔320。根据本发明,使用各向同性湿法腐蚀,它相对于盖层309而言对导体308具有高度选择性(即,它腐蚀导体308的速率快于腐蚀盖层309的速率)。这样,导体308在盖层309之下被侧向腐蚀掉,形成钻蚀互连线305的盖层309的凹孔320。本发明中优选的是锚定孔320以500~1500的量钻蚀盖层309(即,在盖层309之下倒向扩展)。
当导体308是铝-铜合金层,盖层309是铝化钛层时,以下的优选工艺可用于形成锚定孔320。首先,在通路孔318腐蚀之后,衬底302和所形成的金属物在约70℃下放入从J.T.Baker已知为PRS-3000的可向商业提供的溶剂中。PRS-3000包含约40~60%重量的1-甲基-2-吡咯烷酮,30-50%重量的噻吩烷和5~15%重量的雌异丙醇胺(menoisopropanolamine)。在优选方法中,衬底302浸入不同的两批PRS-3000中,每批至少7.5分钟,以完全清除衬底302上的光刻胶和腐蚀聚合物。
接着,衬底302在室温下快速浸入去离子水中约7.0秒。然后衬底302从去离子水中取出,使之放在空的快速倾倒清洗Quick DumpRinse(QDR))槽中约1分钟。只有当PRS-3000和水同时在衬底表面上时才发生腐蚀铝合金层308的反应。应理解的是PRS-3000/水的混合物腐蚀铝化钛层309与腐蚀铝铜合金层308相比特别地慢。所以,铝化钛盖层的完整性保持很好。这就保证了后面形成的通路连接是锁定于互连线305中且钻蚀互连线305,而不是简单地位于互连线305的上面。所述腐蚀剂的重要特点是它的自限性。即在约1分钟后腐蚀由于有限的反应剂而基本停止。这使本发明具有很好的重复性,由此还可制造。另外,应理解的是,铝化钛层307作为锚定孔腐蚀的腐蚀阻挡,可保证锚定孔320不会一直扩展而穿过互连线305。
让H2O/PRS-3000溶液保留在衬底302表面约1分钟后,在空的QDR槽中注满去离子水,使用标准的、熟知的水清洗或QDR循环来清洗衬底302。接着,标准的旋转于清洗循环(SRD)用来结束清洗过程。这时其他的标准和熟知的湿法和干法清洗工艺,比如尘化,可用于充分清洗锚定孔320和晶片表面。应指出本发明的锚定孔腐蚀可去除通路腐蚀的残余物,从而提供一个“新鲜”的铝表面这有助于在后面形成的通路连接与互连线305之间形成强的机械连接,也有助于因清洁而形成更小的电阻。
应理解,虽然以上提到的锚定孔形成工艺是优选的,但是其它工艺也可使用。例如,诸如反应离子刻蚀(RIE)和等离子体刻蚀等干法腐蚀技术也可使用。另外,其它腐蚀剂也可使用比如缓冲的氢氟酸或氟化氨等。唯一的要求是形成锚定孔320的腐蚀技术相对于盖层309而言对导体308是有选择性的。因此,显而易见,选择能被选择腐蚀的盖层309和导体308材料是重要的。
接着,如图3e所示,通路孔318和锚定孔320通过熟知的技术被填入导电材料322,以形成通路连接或孔塞。根据本发明的优选方法,在金属淀积之前进行熟知的溅射清洗。接着,薄的附着/阻挡层,比如Ti和TiN(未画出),通过诸如溅射等熟知的技术覆盖淀积在ILD314上和通路孔318与锚定孔320之中。接着,一种保形的导电材料,优选地为钨,覆盖淀积在附着/阻挡层上并填满通路孔318和锚定孔320。熟知的化学气相淀积(CVD)技术优选地被用来形成导电材料322。CVD钨层可由以下步骤形成,首先通过CVD用包含WF6和SiH4的化合物形成核化层,然后通过CVD用包含WF6和H2的化合物形成钨层。因为CVD形成非常保形的层,所以CVD技术是优选的。这样,导电层322从侧壁内形成,允许在盖层309下淀积金属。应理解的是,导电材料322被淀积直至通路孔318和固定孔320被填满为止。
接着,如图3f所示,ILD314的上表面上的钨层和任何附着或阻挡层被深腐蚀以形成通路连接324。在本发明的该优选实施例中,钨层322和任何附着/阻挡金属通过使用熟知的化学-机械抛光技术来深腐蚀。但是应理解,如果需要,其它诸如反应离子腐蚀(RIE)的其他熟知深腐蚀技术也能使用。
接着,如图3f所示,第二互连线326在通路连接324上形成并与之有电学接触。第二互连线326通过通路连接324与第一互连线305之间具有电学接触。第二互连线326优选地用与第一互连线305相同的结构和方法形成。这样,下一级的金属物可用本发明的新型通路连接技术锚定于互连线326之中。至此本发明的优选互连结构的形成过程就完成了。
这样,描述了一种能阻止通路分层的新型互连结构及其制造方法。

Claims (30)

1.一种用于集成电路的互连结构,包含:
一层互连线;和
一个通路连接,其中该通路连接伸进上述互连线中并且钻蚀该互连线。
2.根据权利要求1的互连结构,其中所说的互连线包含一层铝合金层。
3.根据权利要求1的互连结构,其中所说的互连线还包含含有难熔金属的导体。
4.根据权利要求3的互连结构,其中所说的通路连接钻蚀包含难熔金属的导体。
5.根据权利要求1的互连结构,其中所说的互连线包含形成在铝合金层上的铝化钛层,其中所说的通路连接钻蚀该互连线中的铝化钛层。
6.一种用于形成在半导体衬底上的集成电路的互连结构,包含:
在该衬底上包含铝的第一导电层;
在该第一导电层上包含难熔金属层的第二导电层;
位于该第二导电层上的绝缘层;和
通路连接,该通路连接有穿过第二导电层的第一部分和伸进第一导电层中的第二部分,其中该通路连接的第二部分比该通路连接的第一部分更宽。
7.根据权利要求6的互连结构,还包含位于所说绝缘层和所说第二导电层之间的氮化钛层。
8.根据权利要求6的互连结构,还包含在所说的第一导电层下面的包含难熔金属的第三导电层。
9.根据权利要求8的互连结构,其中位于第一导电层下的所说的难熔金属是钛。
10.根据权利要求6的互连结构,其中通路连接至少伸进第一导电层的一半。
11.根据权利要求6的互连结构,其中所说通路连接包含钨。
12.根据权利要求6的互连结构,其中所说的第二导电层是TiAl3
13.根据权利要求12的互连结构,其中所说的第二导电层厚度为300-1500之间。
14.根据权利要求6的互连结构,其中所说的通路连接伸进所说导电层1000-3500深。
15.根据权利要求6的互连结构,其中通路连接的第二部分的宽度比第二互连线中的通路连接的第一部分宽1000-3000。
16.形成在半导体衬底上的集成电路的互连结构的形成方法,包含以下步骤:
在该衬底上形成第一导电层;
在该第一导电层上形成第二导电层;
在第二导电层上形成绝缘层;
形成穿过绝缘层和第二导电层的第一开口;和
在第一导电层中在第一开口之下形成第二开口,其中第二开口比第二导电层中的第一开口宽。
17.根据权利要求16的方法,其中第二开口通过腐蚀形成,其腐蚀剂相对于第二导电层而言对第一导电层具有选择性。
18.根据权利要求17的方法,其中所说腐蚀剂是湿法腐蚀剂。
19.根据权利要求18的方法,其中形成第二开口的步骤包含以下步骤:
将衬底暴露在包含PRS-3000的溶液中;
将衬底暴露在包含水的溶液中;
在暴露衬底于包含水的溶液中之后,让衬底放置一预定的时间段;
清洗衬底;和
干燥衬底。
20.根据权利要求16的方法,其中第一导电层是铝合金层。
21.根据权利要求16的方法,其中第二导电层是铝/难熔金属层。
22.根据权利要求21的方法,其中第二导电层是铝化钛。
23.根据权利要求22的方法,其中的形成第二导电层的步骤包含以下步骤:
在铝合金层上形成钛层;和
加热该铝合金层和钛层直至基本上所有钛层都与铝合金层反应形成铝化钛层。
24.根据权利要求16的方法,还包含在第一导电层下和衬底上形成钛层的步骤。
25.根据权利要求16的方法,其中第二开口只是部分伸入第一导电层。
26.一种形成互连结构的工艺,包含以下步骤:
形成互连线;
第一次腐蚀互连线,在互连线中形成具有第一宽度的第一开口;和
在第一开口下第二次腐蚀互连线,互连线被侧向腐蚀以形成比第一开口进一步侧向伸入互连线的第二开口。
27.根据权利要求26的工艺,其中第一次腐蚀形成穿过互连线的导电盖层的第一开口,以及其中第二次腐蚀在导电盖层之下侧向腐蚀。
28.根据权利要求27的工艺,其中第一次腐蚀是干法腐蚀。
29.根据权利要求27的工艺,其中第二次腐蚀是湿法腐蚀。
30.根据权利要求27的工艺,其中互连线的导电盖层包含铝化钛,以及其中互连线包含铝合金。
CN95196649A 1994-10-17 1995-07-14 用于集成电路的互连结构及其形成方法 Expired - Fee Related CN1106688C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/324,763 US5470790A (en) 1994-10-17 1994-10-17 Via hole profile and method of fabrication
US08/324,763 1994-10-17

Publications (2)

Publication Number Publication Date
CN1168739A CN1168739A (zh) 1997-12-24
CN1106688C true CN1106688C (zh) 2003-04-23

Family

ID=23264999

Family Applications (1)

Application Number Title Priority Date Filing Date
CN95196649A Expired - Fee Related CN1106688C (zh) 1994-10-17 1995-07-14 用于集成电路的互连结构及其形成方法

Country Status (8)

Country Link
US (3) US5470790A (zh)
JP (1) JPH10507315A (zh)
KR (1) KR100274138B1 (zh)
CN (1) CN1106688C (zh)
AU (1) AU3152195A (zh)
GB (1) GB2308234B (zh)
TW (1) TW289152B (zh)
WO (1) WO1996012295A1 (zh)

Families Citing this family (105)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2921773B2 (ja) * 1991-04-05 1999-07-19 三菱電機株式会社 半導体装置の配線接続構造およびその製造方法
KR0138308B1 (ko) 1994-12-14 1998-06-01 김광호 층간접촉구조 및 그 방법
KR100193100B1 (ko) * 1995-02-02 1999-06-15 모리시다 요이치 반도체장치 및 그 제조방법
JP2953340B2 (ja) * 1995-03-29 1999-09-27 ヤマハ株式会社 配線形成法
US5897374A (en) * 1995-05-22 1999-04-27 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical via/contact with undercut dielectric
US5726498A (en) * 1995-05-26 1998-03-10 International Business Machines Corporation Wire shape conferring reduced crosstalk and formation methods
JP2899540B2 (ja) * 1995-06-12 1999-06-02 日東電工株式会社 フィルムキャリアおよびこれを用いた半導体装置
TW298674B (zh) * 1995-07-07 1997-02-21 At & T Corp
TW318261B (zh) * 1995-09-21 1997-10-21 Handotai Energy Kenkyusho Kk
JPH11511593A (ja) * 1995-09-29 1999-10-05 インテル・コーポレーション 専用チャンバによる2層のチタン薄層を有する集積回路用金属スタック
US5747879A (en) * 1995-09-29 1998-05-05 Intel Corporation Interface between titanium and aluminum-alloy in metal stack for integrated circuit
US5851928A (en) * 1995-11-27 1998-12-22 Motorola, Inc. Method of etching a semiconductor substrate
US5851923A (en) * 1996-01-18 1998-12-22 Micron Technology, Inc. Integrated circuit and method for forming and integrated circuit
US6040613A (en) * 1996-01-19 2000-03-21 Micron Technology, Inc. Antireflective coating and wiring line stack
US5661083A (en) * 1996-01-30 1997-08-26 Integrated Device Technology, Inc. Method for via formation with reduced contact resistance
US5700718A (en) * 1996-02-05 1997-12-23 Micron Technology, Inc. Method for increased metal interconnect reliability in situ formation of titanium aluminide
JP4179483B2 (ja) 1996-02-13 2008-11-12 株式会社半導体エネルギー研究所 表示装置の作製方法
US6821821B2 (en) * 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US5912510A (en) * 1996-05-29 1999-06-15 Motorola, Inc. Bonding structure for an electronic device
US6222272B1 (en) 1996-08-06 2001-04-24 Nitto Denko Corporation Film carrier and semiconductor device using same
US6046100A (en) * 1996-12-12 2000-04-04 Applied Materials, Inc. Method of fabricating a fabricating plug and near-zero overlap interconnect line
US6028363A (en) * 1997-06-04 2000-02-22 Taiwan Semiconductor Manufacturing Company Vertical via/contact
US5877092A (en) * 1997-06-18 1999-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for edge profile and design rules control
US6141870A (en) 1997-08-04 2000-11-07 Peter K. Trzyna Method for making electrical device
US5969425A (en) * 1997-09-05 1999-10-19 Advanced Micro Devices, Inc. Borderless vias with CVD barrier layer
US5925932A (en) 1997-12-18 1999-07-20 Advanced Micro Devices, Inc. Borderless vias
US6522013B1 (en) * 1997-12-18 2003-02-18 Advanced Micro Devices, Inc. Punch-through via with conformal barrier liner
TW359884B (en) * 1998-01-07 1999-06-01 Nanya Technology Co Ltd Multi-level interconnects with I-plug and production process therefor
GB2347267B (en) * 1998-02-20 2001-05-02 Lg Lcd Inc A liquid crystal display
KR100276442B1 (ko) * 1998-02-20 2000-12-15 구본준 액정표시장치 제조방법 및 그 제조방법에 의한 액정표시장치
US6576547B2 (en) 1998-03-05 2003-06-10 Micron Technology, Inc. Residue-free contact openings and methods for fabricating same
US6433428B1 (en) 1998-05-29 2002-08-13 Kabushiki Kaisha Toshiba Semiconductor device with a dual damascene type via contact structure and method for the manufacture of same
US6080664A (en) * 1998-05-29 2000-06-27 Vanguard International Semiconductor Corporation Method for fabricating a high aspect ratio stacked contact hole
US6084296A (en) * 1998-07-09 2000-07-04 Satcon Technology Corporation Low cost high power hermetic package with electrical feed-through bushings
KR100265772B1 (ko) * 1998-07-22 2000-10-02 윤종용 반도체 장치의 배선구조 및 그 제조방법
KR100267106B1 (ko) * 1998-09-03 2000-10-02 윤종용 반도체 소자의 다층 배선 형성방법
KR100295054B1 (ko) * 1998-09-16 2001-08-07 윤종용 다층금속배선을갖는반도체소자및그제조방법
JP3655113B2 (ja) * 1998-12-28 2005-06-02 シャープ株式会社 半導体記憶装置の製造方法
US6169010B1 (en) * 1999-01-26 2001-01-02 Lucent Technologies Inc. Method for making integrated circuit capacitor including anchored plug
US6153901A (en) * 1999-01-26 2000-11-28 Lucent Technologies Inc. Integrated circuit capacitor including anchored plug
DE19903195B4 (de) * 1999-01-27 2005-05-19 Infineon Technologies Ag Verfahren zur Verbesserung der Qualität von Metalleitbahnen auf Halbleiterstrukturen
US6087726A (en) * 1999-03-01 2000-07-11 Lsi Logic Corporation Metal interconnect stack for integrated circuit structure
US6265305B1 (en) * 1999-10-01 2001-07-24 United Microelectronics Corp. Method of preventing corrosion of a titanium layer in a semiconductor wafer
JP2001145241A (ja) * 1999-11-15 2001-05-25 Sumitomo Wiring Syst Ltd 配線板組立体
JP3502800B2 (ja) 1999-12-15 2004-03-02 新光電気工業株式会社 半導体装置の製造方法
US6313026B1 (en) * 2000-04-10 2001-11-06 Micron Technology, Inc. Microelectronic contacts and methods for producing same
JP3547364B2 (ja) * 2000-04-21 2004-07-28 シャープ株式会社 半導体装置の製造方法
US6396677B1 (en) * 2000-05-17 2002-05-28 Xerox Corporation Photolithographically-patterned variable capacitor structures and method of making
US6392524B1 (en) 2000-06-09 2002-05-21 Xerox Corporation Photolithographically-patterned out-of-plane coil structures and method of making
US6856225B1 (en) * 2000-05-17 2005-02-15 Xerox Corporation Photolithographically-patterned out-of-plane coil structures and method of making
DE10193432B4 (de) * 2000-08-18 2010-05-12 Mitsubishi Denki K.K. Montageplatte, Verfahren zum Montieren einer Montageplatte und Birnenhalter mit einer Montageplatte
KR100365642B1 (ko) * 2000-10-30 2002-12-26 삼성전자 주식회사 접촉창을 갖는 반도체 장치의 제조 방법
JP4752108B2 (ja) * 2000-12-08 2011-08-17 ソニー株式会社 半導体装置およびその製造方法
US6613664B2 (en) * 2000-12-28 2003-09-02 Infineon Technologies Ag Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices
US6441435B1 (en) * 2001-01-31 2002-08-27 Advanced Micro Devices, Inc. SOI device with wrap-around contact to underside of body, and method of making
US6595787B2 (en) * 2001-02-09 2003-07-22 Xerox Corporation Low cost integrated out-of-plane micro-device structures and method of making
KR100385227B1 (ko) * 2001-02-12 2003-05-27 삼성전자주식회사 구리 다층 배선을 가지는 반도체 장치 및 그 형성방법
US20030219459A1 (en) * 2002-01-18 2003-11-27 Cytos Biotechnology Ag Prion protein carrier-conjugates
US20030194872A1 (en) * 2002-04-16 2003-10-16 Applied Materials, Inc. Copper interconnect with sidewall copper-copper contact between metal and via
JP3974470B2 (ja) * 2002-07-22 2007-09-12 株式会社東芝 半導体装置
KR20040017037A (ko) * 2002-08-20 2004-02-26 삼성전자주식회사 반도체 콘택 구조 및 그 형성 방법
DE10257681B4 (de) 2002-12-10 2008-11-13 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Schaltungsanordnung, die eine Metallnitridschicht enthält, und integrierte Schaltungsanordnung
US6806579B2 (en) * 2003-02-11 2004-10-19 Infineon Technologies Ag Robust via structure and method
US6977437B2 (en) * 2003-03-11 2005-12-20 Texas Instruments Incorporated Method for forming a void free via
US20040192059A1 (en) * 2003-03-28 2004-09-30 Mosel Vitelic, Inc. Method for etching a titanium-containing layer prior to etching an aluminum layer in a metal stack
US7045455B2 (en) * 2003-10-23 2006-05-16 Chartered Semiconductor Manufacturing Ltd. Via electromigration improvement by changing the via bottom geometric profile
KR20050056419A (ko) * 2003-12-10 2005-06-16 동부아남반도체 주식회사 반도체 소자의 금속 배선 형성 방법
US7956672B2 (en) * 2004-03-30 2011-06-07 Ricoh Company, Ltd. Reference voltage generating circuit
US7217651B2 (en) * 2004-07-28 2007-05-15 Intel Corporation Interconnects with interlocks
KR100668833B1 (ko) * 2004-12-17 2007-01-16 주식회사 하이닉스반도체 반도체소자의 캐패시터 제조방법
US7332428B2 (en) * 2005-02-28 2008-02-19 Infineon Technologies Ag Metal interconnect structure and method
US20060244151A1 (en) * 2005-05-02 2006-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Oblique recess for interconnecting conductors in a semiconductor device
DE102005024914A1 (de) * 2005-05-31 2006-12-07 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden elektrisch leitfähiger Leitungen in einem integrierten Schaltkreis
EP1920459A4 (en) * 2005-08-12 2012-07-25 Semiconductor Energy Lab PROCESS FOR PRODUCING A SEMICONDUCTOR COMPONENT
US7511349B2 (en) * 2005-08-19 2009-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Contact or via hole structure with enlarged bottom critical dimension
US7517736B2 (en) * 2006-02-15 2009-04-14 International Business Machines Corporation Structure and method of chemically formed anchored metallic vias
US7528066B2 (en) * 2006-03-01 2009-05-05 International Business Machines Corporation Structure and method for metal integration
JP4788474B2 (ja) * 2006-05-19 2011-10-05 三菱電機株式会社 半導体装置
DE102006035645B4 (de) * 2006-07-31 2012-03-08 Advanced Micro Devices, Inc. Verfahren zum Ausbilden einer elektrisch leitfähigen Leitung in einem integrierten Schaltkreis
KR100790452B1 (ko) * 2006-12-28 2008-01-03 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법
DE102007004860B4 (de) * 2007-01-31 2008-11-06 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Kupfer-basierten Metallisierungsschicht mit einer leitenden Deckschicht durch ein verbessertes Integrationsschema
US7790599B2 (en) * 2007-04-13 2010-09-07 International Business Machines Corporation Metal cap for interconnect structures
US9076821B2 (en) 2007-04-30 2015-07-07 Infineon Technologies Ag Anchoring structure and intermeshing structure
DE102007020263B4 (de) * 2007-04-30 2013-12-12 Infineon Technologies Ag Verkrallungsstruktur
US7709966B2 (en) * 2007-09-25 2010-05-04 Sixis, Inc. Large substrate structural vias
WO2011046388A2 (ko) 2009-10-15 2011-04-21 엘지이노텍주식회사 태양광 발전장치 및 이의 제조방법
US9793199B2 (en) * 2009-12-18 2017-10-17 Ati Technologies Ulc Circuit board with via trace connection and method of making the same
US8314026B2 (en) 2011-02-17 2012-11-20 Freescale Semiconductor, Inc. Anchored conductive via and method for forming
JP5360134B2 (ja) * 2011-06-01 2013-12-04 三菱電機株式会社 半導体装置及びその製造方法
JP2013187339A (ja) * 2012-03-07 2013-09-19 Toshiba Corp 半導体装置及びその製造方法
US8772949B2 (en) 2012-11-07 2014-07-08 International Business Machines Corporation Enhanced capture pads for through semiconductor vias
US9230934B2 (en) 2013-03-15 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Surface treatment in electroless process for adhesion enhancement
US9832887B2 (en) * 2013-08-07 2017-11-28 Invensas Corporation Micro mechanical anchor for 3D architecture
US9299656B2 (en) 2014-06-02 2016-03-29 Infineon Technologies Ag Vias and methods of formation thereof
KR102307633B1 (ko) 2014-12-10 2021-10-06 삼성전자주식회사 반도체 소자 및 그 제조 방법
US10667709B2 (en) * 2016-05-27 2020-06-02 Board Of Trustees Of Michigan State University Hybrid diamond-polymer thin film sensors and fabrication method
US10163692B2 (en) * 2017-03-08 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of interconnection structure of semiconductor device structure
US10475702B2 (en) * 2018-03-14 2019-11-12 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive feature formation and structure using bottom-up filling deposition
US11121025B2 (en) 2018-09-27 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Layer for side wall passivation
US11177169B2 (en) 2019-06-21 2021-11-16 International Business Machines Corporation Interconnects with gouged vias
CN110190030A (zh) * 2019-06-24 2019-08-30 南京华瑞微集成电路有限公司 一种通过连接孔改善uis的方法及功率器件
CN110739269B (zh) * 2019-10-25 2020-11-20 武汉新芯集成电路制造有限公司 半导体器件及其形成方法
US11183455B2 (en) * 2020-04-15 2021-11-23 International Business Machines Corporation Interconnects with enlarged contact area
US11551967B2 (en) * 2020-05-19 2023-01-10 Taiwan Semiconductor Manufacturing Company Limited Via structure and methods for forming the same
US20230187350A1 (en) * 2021-12-13 2023-06-15 International Business Machines Corporation Dual-metal ultra thick metal (utm) structure

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59228737A (ja) * 1983-06-10 1984-12-22 Seiko Epson Corp 半導体装置
US4507852A (en) * 1983-09-12 1985-04-02 Rockwell International Corporation Method for making a reliable ohmic contact between two layers of integrated circuit metallizations
US4714686A (en) * 1985-07-31 1987-12-22 Advanced Micro Devices, Inc. Method of forming contact plugs for planarized integrated circuits
JPS63133647A (ja) * 1986-11-26 1988-06-06 Oki Electric Ind Co Ltd 半導体装置の製造方法
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
JPH02122546A (ja) * 1988-10-31 1990-05-10 Nec Corp 半導体装置の製造方法
US5106461A (en) * 1989-04-04 1992-04-21 Massachusetts Institute Of Technology High-density, multi-level interconnects, flex circuits, and tape for tab
JP2660359B2 (ja) * 1991-01-30 1997-10-08 三菱電機株式会社 半導体装置
JPH0529470A (ja) * 1991-07-24 1993-02-05 Sony Corp 配線の形成方法
US5262352A (en) * 1992-08-31 1993-11-16 Motorola, Inc. Method for forming an interconnection structure for conductive layers

Also Published As

Publication number Publication date
US5619071A (en) 1997-04-08
GB2308234A (en) 1997-06-18
KR100274138B1 (ko) 2000-12-15
GB9706661D0 (en) 1997-05-21
CN1168739A (zh) 1997-12-24
AU3152195A (en) 1996-05-06
GB2308234B (en) 1999-04-14
TW289152B (zh) 1996-10-21
US5874358A (en) 1999-02-23
WO1996012295A1 (en) 1996-04-25
JPH10507315A (ja) 1998-07-14
KR970707573A (ko) 1997-12-01
US5470790A (en) 1995-11-28

Similar Documents

Publication Publication Date Title
CN1106688C (zh) 用于集成电路的互连结构及其形成方法
US5821620A (en) Electromigration resistant metallization structures for microcircuit interconnections with RF-reactively sputtered titanium tungsten and gold
JP3057054B2 (ja) 銅線の多層相互接続を形成する方法
US5565707A (en) Interconnect structure using a Al2 Cu for an integrated circuit chip
US5289035A (en) Tri-layer titanium coating for an aluminum layer of a semiconductor device
EP0788156B1 (en) Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD
US6391777B1 (en) Two-stage Cu anneal to improve Cu damascene process
US6004876A (en) Low resistance interconnect for a semiconductor device and method of fabricating the same
US20070252278A1 (en) Process of forming a composite diffusion barrier in copper/organic low-k damascene technology
US20020027287A1 (en) Semiconductor device with copper wiring and its manufacture method
US6797642B1 (en) Method to improve barrier layer adhesion
KR20000048295A (ko) 반도체 장치의 배선 구조 및 그 제조 방법
US6087726A (en) Metal interconnect stack for integrated circuit structure
US6413863B1 (en) Method to resolve the passivation surface roughness during formation of the AlCu pad for the copper process
US6787467B2 (en) Method of forming embedded copper interconnections and embedded copper interconnection structure
KR0178406B1 (ko) 반도체 장치 제조방법
US6297158B1 (en) Stress management of barrier metal for resolving CU line corrosion
US20090096103A1 (en) Semiconductor device and method for forming barrier metal layer thereof
KR100588904B1 (ko) 구리 배선 형성 방법
US6867135B1 (en) Via bottom copper/barrier interface improvement to resolve via electromigration and stress migration
US20210327753A1 (en) Multi-pass plating process with intermediate rinse and dry
US6130150A (en) Method of making a semiconductor device with barrier and conductor protection
US6440841B2 (en) Method of fabricating vias
KR100219061B1 (ko) 반도체 장치의 금속배선 형성 방법
KR100197665B1 (ko) 반도체 소자의 금속배선 형성방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20030423

Termination date: 20100714