CN1107321C - 多值的、其信噪比有所改善的固定值存储单元 - Google Patents
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Abstract
本发明涉及一种多值的固定值存储单元。其中,尽量减少所需的电路费用并且与已公开的、多值的存储单元相比,其信噪比有显著改善。所述存储单元用于存储制成对称结构的一个第一和第二状态和制成非对称结构的一个第三状态,其特征在于,固定值存储单元包括一个MOS场效应晶体管,其中通过一个第一单元引线端、一个第二单元引线端与MOS场效应晶体管的源/漏极区与MOS场效应晶体管的各个电极区连接的不同连接方式,分别存储第一状态至第四状态。
Description
技术领域
本发明涉及一种多值的、其信噪比有所改变的固定值存储单元。
背景技术
普通的存储单元都可以存储一位(Bit)信息。存储单元的两个状态譬如可以是在一个单一晶体管存储单元内晶体管的一个高的或低的截止电压。在很多公开的存储单元中,位线在读出过程中首先被预充电到一个确定的电压。在经由字线控制存储单元时,连接到存储单元上的位线根据存储单元的具体状态被或多或少地再充电。据此,存储单元的信息可经由位线的一个高的或者低的电平被读出。为了得到高的扰干扰性,这两个电平必须具有尽可能高的电压差,例如具有正的馈电电压和零伏。
为了增加信息密度,特别是在固定值存储器中,有时也采用多值的存储单元。多值的存储单元是其存储能力分别多于一位的存储单元。
其公开号为WO82/02977的国际专利申请公开了一种可用掩膜程序化的固定值存储器(ROM),在其存储单元中可存储多于仅只有两个逻辑状态。其中,为了得到同样尺寸的、且尺寸最小的存储单元,逻辑状态是这样编入存储单元的,即处在具体的存储单元中的晶体管的阈电压(截止电压)分别被单独调整。
其中,多个,例如四个不同的电压值或电流值须可靠地被区别。这意味着譬如为了建立稳定的基准电压须付出较高的电路费用,并首先意味着抗干扰性有所降低。这还会导致成品率降低。估计,这是多值的存储单元迄今没有达到实用阶段的原因所在。在现代的、其馈电电压有所降低的,譬如为3.3伏的存储器中,上述缺点更不可接受的。
实用新型GB-A-2157489公开了一种多值的固定值存储单元,该多值的存储单元用于存储一个第一或第二状态制成对称结构,用于存储一个第三或第四状态制成非对称结构。
发明内容
本发明的任务在于提供一种多值的存储单元,其中,尽量减少所需的电路费用并且与已公开的、多值的存储单元相比,其信噪比有显著改善。
按照本发明,提供了一种多值的固定值存储单元,该存储单元用于存储制成对称结构的一个第一和第二状态(M,M)并且用于存储制成非对称结构的一个第三状态(M,M”),其特征在于,固定值存储单元包括一个MOS场效应晶体管(T),该晶体管(T)具有一个处在半导体(H)中的源/漏极区(S/D)和一个在半导体(H)中的漏/源极区(D/S),其中,为了存储第一状态(M),一个第一单元引线端(1)与MOS场效应晶体管的源/漏极区(S/D)直接连接并且一个第二单元引线端(2)与MOS场效应晶体管的漏/源极区(D/S)直接连接,其中,为了存储第二状态(M),第一单元引线端(1)经一个元件(D1、R1)与MOS场效应晶体管的源/漏极区(S/D)相连,并且第二单元引线端(2)经另一元件(S2、R2)与MOS场效应晶体管的漏/源极区(D/S)连接,其中,为存储第三状态(M’),第一单元引线端(1)经元件(D1、R1)与MOS场效应晶体管的源/漏极区(S/D)相连并且第二单元引线端(2)与MOS场效应晶体管的漏/源极区(D/S)直接连接,其中,为了存储一个第四状态(M”),第一单元引线端(1)与MOS场效应晶体管的源/漏极区(S/D)直接连接并且第二单元引线端(2)经另一元件(D2、R2)与MOS场效应晶体管的漏/源极区(D/S)连接,其中,一个第三单元引线端(3)与MOS场效应晶体管的一个栅极(G)相连,其中,该栅极通过一个绝缘层(ISO)与半导体电气绝缘,并且,上述的元件是一个第一二极管(D1),并且上述的另一元件是一个第二二极管(D2)。
优选地,在上述多值的固定值存储单元中,为了形成第一二极管(D1),第一单元引线端(1)经一个第一附加区(Z1)与MOS场效应晶体管的源/漏极区(S/D)相连并且为了形成第二二极管(D2),第二单元引线端(2)经一个第二附加区(Z2)与MOS场效应晶体管的漏/源极区(D/S)连接,为了存储第一状态(M),第一附加区和第二附加区(Z1、Z2)均是通过第一和第二引线端(1、2)的凹陷结构的、伸达源/漏极区(S/D)和漏/源极区(D/S)的金属接触(K、K’)被桥接的,其中,为了存储第二状态(M),第一和第二附加区(Z1,Z2)均是只通过第一和第二引线端(1、2)的浅平结构的、仅伸达两个附加区的金属接触被桥接的,其中,为了存储第三状态(M’),只有第一附加区(Z1)是通过第一引线端(1)的一个凹陷结构的、伸达源/漏极区(S/D)的金属接触被桥接的,并且,为了存储第四状态(M”),只有第二附加区(Z2)是通过第一引线端(1)的一个凹陷结构的、伸达漏/源极区(D/S)的金属接触被桥接的。
根据本发明的另一个方面,提供了一种多值的固定值存储单元,该存储单元用于存储制成对称结构的一个第一和第二状态(M,M)并且用于存储制成非对称结构的一个第三状态(M,M”),其特征在于,所述固定值存储单元包括一个MOS场效应晶体管(T),该晶体管(T)具有一个处在半导体(H)中的源/漏极区(S/D)和一个处在半导体中的漏/源极区(D/S),其中,为了存储第一状态(M),一个第一单元引线端(1)与MOS场效应晶体管的源/漏极区(S/D)直接连接并且一个第二单元引线端(2)与MOS场效应晶体管的漏/源极区(D/S)直接连接,其中,为了存储第二状态(M),第一单元引线端(1)经一个元件(D1、R1)与MOS场效应晶体管的源/漏极区(S/D)相连,并且一个第二单元引线端(2)经另一元件(D2、R2)与MOS场效应晶体管的漏/源极区(D/S)连接,其中,为存储第三状态(M’),第一单元引线端(1)经元件(D1、R1)与MOS场效应晶体管的源/漏极区(S/D)连接并且第二单元引线端(2)与MOS场效应晶体管的漏/源极区(D/S)直接连接,其中,为了存储一个第四状态(M”),第一单元引线端(1)与MOS场效应晶体管的源/漏极区(S/D)直接连接并且第二单元引线端(2)经另一元件(D2、R2)与MOS场效应晶体管的漏/源极区(D/S)连接,其中,一个第三单元引线端(3)与MOS场效应晶体管的一个栅极(G)相连,其中,该栅极通过一个绝缘层(ISO)与半导体电气绝缘,并且,上述的元件是一个第一电阻(R1)并且上述的另一元件是一个第二电阻(R2)。
下面借助附图详细说明本发明。
附图说明
图1在四个可能的状态下的存储单元的视图,
图2A至2D一个用于实施四个不同存储状态的存储单元用的MOS型晶体管的不同的实施形式,
图3图2D的另一种派生形式,
图4第一个本发明存储单元电路图,
图5用于说明制作图4所示存储单元的剖面图,
图6第二个改进的本发明存储单元电路图。
具体实施方式
在图1中示出了在四个不同状态M,M’、M”和M下编制程序的、本发明的存储单元及其具体的单元引线端1、2和3。其中,具有状态M的存储单元没有点形标记,具有状态M’的存储单元在单元引线端1上有一个点形标记,具有状态M”的存储单元在单元引线端2上有一个点形标记,并且具有状态M的存储单元在单元引线端1和2上均有一个点形标记。所以,具有存储的状态M和M的存储单元就单元引线端1和2而言是对称的,并且具有存储的状态M’和M”的存储单元就单元引线端1和2而言是非对称的。
图2A至2D举例性地示出了四个状态在一个譬如处在一个一次可编程序的存储单元(OTP存储单元)中的N沟道晶体管内的存储情况。
其中,图2A示出了未编程序的、对称的MOS晶体管。在图2B所示的MOS晶体管中,在单元引线端1附近的栅极氧化物的范围内置入了负电荷。据此,为了在该区域的下方建立一个反型沟道,栅电压VG须高于单元引线端2附近的栅极氧化物下方的电压。简言之,这意味着单元引线端1附近的截止电压VT局部有所升高。MOS晶体管在饱和区(漏源极间电压VDS>VG-VT)工作时,实现导通近乎只取决于源极引线端附近的截止电压。按照规定,源极引线端是两个单元引线端1或2中的那个具有较低的电压的单元引线端。据此,在选择单元引线端1作为源极时,得到一个高的截止电压,在选择单元引线端2作为源极时,得到一个低的截止电压。在图2C中所示的单元引线端1和2的情况与图2B所示的情况实际上恰恰颠倒。而图2D则示出了两侧的截止电压均被升高的情况。
图3示出了在整条沟道中有所升高的截止电压的情况。在电气特性方面,图2D和图3所示的晶体管是相等的,但可采用不同程序设计方法,后面还要对此详加说明。
在下面的表中依次列出了用于图2A至2D或者图3所示的晶体管的截止电压(阈电压)VT与单元引线端1和2上的电压VDS的极性的关系以及所属的、作为2位数的单元信息。其中,须注意的是,与普通的1位存储单元一样,待读的信号具有同样高的信噪比。VDS=V21>0时的VT VDS=V12>0时的VT 单元信息低 低 00M低 高 01M’高 低 10M”高 高 11M
对状态M”和M进行区别的措施譬如可在于,先在第一单元引线端1上置一个固定的电平,单元引线端2上的位线被预充到一个预充电平,其中,此预充电平与单元引线端1上的固定电平是不同的,并且随后在驱动存储单元之后对位线电位的变化加以评定。然后把该固定电平置于单元引线端2上,对单元引线端1上的位线进行预充电并再次评定位线的电位变化。
评定也可这样进行,即首先把一个第一固定电平置于单元引线端1上,并对单元引线端2上的位线的电平进行评定,并且随后把一个第二固定电平置于单元引线端1上,并再次对单元引线端2上的位线的电平进行评定。
本发明的存储单元譬如特别适用于一次可编程序的存储器(OTP)。其中,可通过把电子局部注入一个至少是MOS场效应晶体管的绝缘层ISO的一个构成部分的氧化物-氮化物-氧化物层(ONO)中,或通过把电子局部注入一个普通的氧化物层中来完成程序编制。其中,在漏源极间电压VDS高的情况下注入“热的”电荷时,这些电荷被注入漏极区附近的一个小的范围内。与普通的氧化物层相比,所谓的ONO层的优点在于,ONO层具有高的电子俘获概率,并且这些电荷实际上不进行侧向运动。通过均匀的注入可造成图3所示的状态。
本发明的另一实施形式在于,一个引线端附近的沟道范围的掺杂不同于MOS场效应晶体管的其余沟道的掺杂。这可譬如通过一个注入掩膜来完成,该注入掩膜的开孔只覆盖沟道范围的一部分。也可在对源/漏极进行注入前,在譬如覆盖住源极范围的情况下在漏极注入附加的掺杂,并把其从晶体管的漏极侧扩散到沟道中。为此所需的掩膜是自调准的并因此较不临界。此外,也可考虑选择以缓斜角或以锐角对源漏极进行注入。锐角注入,譬如由0至约7度角注入已在标准技术中公开。从LATID晶体管(大角度倾斜注入的漏极)的开发中提供了缓斜角,如30至60度角注入的经验。相对而言,用于以缓斜角注入的掩膜是不临界的,因为该掩膜只须在向栅极氧化物的过渡范围内与相关的源漏极区重叠并可与沟道范围任意重叠。
作为替代提高截止电压的方案,也可譬如通过注入正的电荷来降低截止电压。
此外,相应的存储单元当然不仅可用n沟道晶体管实现,而且也可用p沟道晶体管实现。
为了建立晶体管的非对称性,不仅可考虑截止电压的影响,而且也可考虑譬如改变氧化物的厚度或在漏极引线端和源极引线端附近选用不同的晶体管宽度。
此外,在对存储单元进行读出时,对三个不同的晶体管状态可如此进行区别,即晶体管或者在线性区工作,就是说在漏源极间电压VDS小于减少了阈电压VT的栅极电压(VDS<VG-VT)的情况下工作,或者在饱和区工作。在该情况下,所有引线端不转换极性,而只是单元引线端1和单元引线端2的压差的大小有所改变。在不同的工作点所产生的阈电压列于下表:
图 V21>V31时的VT V21≈V31时的VT 单元信息
2A 低 低 0M
2B 高 低 1M’
2D.3 高 高 2M
除了在MOS场效应晶体管T内建立对称或者非对称之外,在另一实施形式中,通过加有的元件,如二极管或电阻形成对称或者非对称。
在图4中示出了一个MOS场效应晶体管,其源/漏极区经一个二极管D1与单元引线端1相连,其漏/源极区经一个二极管D2与单元引线端2相连,并且其栅极引线端与单元引线端3相连。其中,根据具体的程序设计,二极管D1可通过一条导电的连线K桥接,并且二极管D2可通过一条导电的连线K’桥接。可从下表中看出四个不同的状态据此是如何可存储在一个相应的存储单元中的。
设在如下单元
引线端上的二极管 V(2)-V(1) 单元状态 单元信息
- >0 导通 00M
<0 导通
1 >0 阻塞 01M’
<0 导通
2 >0 导通 10M”
<0 阻塞
1和2 >0 阻塞 11M
<0 阻塞
在图5中示出了图4所示存储单元的一个优选的实施形式的一个剖面图,其中,为了形成二极管D1,在本图中譬如n+掺杂的源/漏极区S/D内插入了一个p+区,并且为了形成二极管D2,在本图中譬如n+掺杂的漏/源极区D/S内同样插入了一个p+区。为了进行程序设计,在一个可用掩膜程序化的固定值存储器(ROM)中,二极管可通过腐蚀透p+区直至n+掺杂的源/漏极区或漏/源极区的、并包括接触连线K和K’的接触孔被桥接。因此,程序化可借助一个附加的接触孔掩膜来实现。
为了用电的方法来编程,二极管必须能单另地被桥接。这可譬如可通过加上一个高的电压来进行,该电压譬如通过烧通氧化物隔离层建立持久的导通连接。
替而代之,原有的导电接线也可通过熔化被单另断开。
图6和图4的区别仅在于,设置电阻R1和R2,用以替代二极管D1和D2。其中,建立非对称的措施可在于,源极馈线中的电阻导致的电流降大于漏极馈线中的电阻所导致的电流降。
单元引线端区的电阻可通过掺杂材料的密度和掺杂区的深度被改变。接触孔的电阻也可通过制作,譬如通过势垒的结构形式予以影响。与图4所描述的实施形式一样,程序化可借助一个附加的掩膜来进行,或者用电的方法来进行。
Claims (3)
1.多值的固定值存储单元,该存储单元用于存储制成对称结构的一个第一状态和一个第二状态(M,M)并且用于存储制成非对称结构的一个第三状态(M,M”),
其特征在于,固定值存储单元包括一个MOS场效应晶体管(T),该晶体管(T)具有一个处在半导体(H)中的源/漏极区(S/D)和一个在半导体(H)中的漏/源极区(D/S),
其中,为了存储第一状态(M),一个第一单元引线端(1)与MOS场效应晶体管的源/漏极区(S/D)直接连接并且一个第二单元引线端(2)与MOS场效应晶体管的漏漏/极区(D/S)直接连接,
其中,为了存储第二状态(M),第一单元引线端(1)经一个元件(D1、R1)与MOS场效应晶体管的源/漏极区(S/D)相连,并且第二单元引线端(2)经另一元件(D2、R2)与MOS场效应晶体管的漏/源极区(D/S)连接,
其中,为存储第三状态(M’),第一单元引线端(1)经元件(D1、R1)与MOS场效应晶体管的源/漏极区(S/D)相连并且第二单元引线端(2)与MOS场效应晶体管的漏/源极区(D/S)直接连接,
其中,为了存储一个第四状态(M”),第一单元引线端(1)与MOS场效应晶体管的源/漏极区(S/D)直接连接并且第二单元引线端(2)经另一元件(D2、R2)与MOS场效应晶体管的漏/源极区(D/S)连接,
其中,一个第三单元引线端(3)与MOS场效应晶体管的一个栅极(G)相连,其中该栅极通过一个绝缘层(ISO)与半导体电气绝缘,并且其中,上述的元件是第一二极管(D1),并且上述的另一元件是第二二极管(D2)。
2.按照权利要求1所述的多值的固定值存储单元,其特征在于,
为了形成第一二极管(D1),第一单元引线端(1)经一个第一附加区(Z1)与MOS场效应晶体管的源/漏极区(S/D)相连并且为了形成第二二极管(D2),第二单元引线端(2)经一个第二附加区(Z2)与MOS场效应晶体管的漏/源极区(D/S)连接,
其中,为了存储第一状态(M),第一附加区和第二附加区(Z1、Z2)均是通过第一和第二引线端(1、2)的凹陷结构的伸达源/漏极区(S/D)和漏/源极区(D/S)的金属接触(K、K’)被桥接的,
其中,为了存储第二状态(M),第一和第二附加区(Z1,Z2)均是只通过第一和第二引线端(1、2)的浅平结构的仅伸达两个附加区的金属接触被桥接的,
其中,为了存储第三状态(M’),只有第一附加区(Z1)是通过第一引线端(1)的一个凹陷结构的伸达源/漏极区(S/D)的金属接触被桥接的,并且
其中,为了存储第四状态(M”),只有第二附加区(Z2)是通过第一引线端(1)的一个凹陷结构的伸达漏/源极区(D/S)的金属接触被桥接的。
3、多值的固定值存储单元,该存储单元用于存储制成对称结构的一个第一状态和一个第二状态(M,M)并且用于存储制成非对称结构的一个第三状态(M,M”),
其特征在于,所述固定值存储单元包括一个MOS场效应晶体管(T),该晶体管(T)具有一个处在半导体(H)中的源/漏极区(S/D)和一个处在半导体中的漏/源极区(D/S),
其中,为了存储第一状态(M),一个第一单元引线端(1)与MOS场效应晶体管的源/漏极区(S/D)直接连接并且一个第二单元引线端(2)与MOS场效应晶体管的漏/源极区(D/S)直接连接,
其中,为了存储第二状态(M),第一单元引线端(1)经一个元件(D1、R1)与MOS场效应晶体管的源/漏极区(S/D)相连,并且一个第二单元引线端(2)经另一元件(D2、R2)与MOS场效应晶体管的漏/源极区(D/S)连接,
其中,为存储第三状态(M’),第一单元引线端(1)经元件(D1、R1)与MOS场效应晶体管的源/漏极区(S/D)连接并且第二单元引线端(2)与MOS场效应晶体管的漏/源极区(D/S)直接连接,
其中,为了存储一个第四状态(M”),第一单元引线端(1)与MOS场效应晶体管的源/漏极区(S/D)直接连接并且第二单元引线端(2)经另一元件(D2、R2)与MOS场效应晶体管的漏/源极区(D/S)连接,
其中,一个第三单元引线端(3)与MOS场效应晶体管的一个栅极(G)相连,其中该栅极通过一个绝缘层(ISO)与半导体电气绝缘,并且其中,上述的元件是第一电阻(R1),并且上述的另一元件是第二电阻(R2)。
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CN104978990B (zh) | 2014-04-14 | 2017-11-10 | 成都海存艾匹科技有限公司 | 紧凑型三维存储器 |
US10304495B2 (en) | 2014-04-14 | 2019-05-28 | Chengdu Haicun Ip Technology Llc | Compact three-dimensional memory with semi-conductive address line portion |
US10199432B2 (en) | 2014-04-14 | 2019-02-05 | HangZhou HaiCun Information Technology Co., Ltd. | Manufacturing methods of MOSFET-type compact three-dimensional memory |
US10304553B2 (en) | 2014-04-14 | 2019-05-28 | HangZhou HaiCun Information Technology Co., Ltd. | Compact three-dimensional memory with an above-substrate decoding stage |
KR102323612B1 (ko) * | 2015-11-23 | 2021-11-08 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 이의 동작 방법 |
CN107301878B (zh) | 2016-04-14 | 2020-09-25 | 成都海存艾匹科技有限公司 | 多位元三维一次编程存储器 |
US11170863B2 (en) | 2016-04-14 | 2021-11-09 | Southern University Of Science And Technology | Multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAM) |
US10490562B2 (en) | 2016-04-16 | 2019-11-26 | HangZhou HaiCun Information Technology Co., Ltd. | Three-dimensional vertical one-time-programmable memory comprising multiple antifuse sub-layers |
US10559574B2 (en) | 2016-04-16 | 2020-02-11 | HangZhou HaiCun Information Technology Co., Ltd. | Three-dimensional vertical one-time-programmable memory comprising Schottky diodes |
US10002872B2 (en) | 2016-04-16 | 2018-06-19 | Chengdu Haicun Ip Technology Llc | Three-dimensional vertical one-time-programmable memory |
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1995
- 1995-02-16 DE DE19505293A patent/DE19505293A1/de not_active Withdrawn
- 1995-12-28 IN IN1748CA1995 patent/IN185754B/en unknown
-
1996
- 1996-02-05 EP EP96901232A patent/EP0809847B1/de not_active Expired - Lifetime
- 1996-02-05 KR KR1019970705615A patent/KR19980702220A/ko active IP Right Grant
- 1996-02-05 DE DE59600366T patent/DE59600366D1/de not_active Expired - Lifetime
- 1996-02-05 CN CN96191959A patent/CN1107321C/zh not_active Expired - Fee Related
- 1996-02-05 WO PCT/DE1996/000168 patent/WO1996025741A2/de active IP Right Grant
- 1996-02-05 JP JP8524568A patent/JPH11500559A/ja not_active Abandoned
- 1996-02-05 US US08/875,955 patent/US5825686A/en not_active Expired - Lifetime
- 1996-02-16 AR ARP960101414A patent/AR000974A1/es unknown
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GB2157489A (en) * | 1984-03-23 | 1985-10-23 | Hitachi Ltd | A semiconductor integrated circuit memory device |
EP0590319A2 (en) * | 1992-10-02 | 1994-04-06 | Matsushita Electric Industrial Co., Ltd. | A non-volatile memory cell |
US5296726A (en) * | 1993-03-31 | 1994-03-22 | Northern Telecom Limited | High value resistive load for an integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH11500559A (ja) | 1999-01-12 |
WO1996025741A3 (de) | 1997-02-06 |
EP0809847B1 (de) | 1998-07-22 |
DE59600366D1 (de) | 1998-08-27 |
IN185754B (zh) | 2001-04-24 |
AR000974A1 (es) | 1997-08-27 |
CN1174628A (zh) | 1998-02-25 |
KR19980702220A (ko) | 1998-07-15 |
EP0809847A2 (de) | 1997-12-03 |
DE19505293A1 (de) | 1996-08-22 |
US5825686A (en) | 1998-10-20 |
WO1996025741A2 (de) | 1996-08-22 |
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