CN1139116C - 集成电路封装及具有该封装的计算机系统 - Google Patents

集成电路封装及具有该封装的计算机系统 Download PDF

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CN1139116C
CN1139116C CNB961925345A CN96192534A CN1139116C CN 1139116 C CN1139116 C CN 1139116C CN B961925345 A CNB961925345 A CN B961925345A CN 96192534 A CN96192534 A CN 96192534A CN 1139116 C CN1139116 C CN 1139116C
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power supply
face
supply signal
becket
dielectric layer
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CN1178602A (zh
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L・莫斯雷
L·莫斯雷
�锏
A·马里德
拉雅
S·那塔拉雅
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Intel Corp
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Intel Corp
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    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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Abstract

放置在印制电路(PC)板(56)上的高性能的集成电路封装(10)，并具有第一介质层。在这个第一介质层上为金属化管芯焊盘(22)和第一金属环(38a)，第一金属环环绕金属化管芯焊盘。金属化管芯焊盘和第一金属环与PC板电连接，分别用于接收第一电源信号和第二电源信号。然后将集成电路管芯(12)贴到金属化管芯焊盘上。该集成电路管芯(12)有第一电源信号焊盘(28，30)和第二电源信号焊盘(33，34)，它们分别接金属化管芯焊盘和第一金属环。因此，金属化管芯焊盘和第一金属环用作第一电源板和第二电源板，将来自PC板的第一和第二电源信号接到集成电路管芯上的第一和第二电源信号焊盘上。

Description

集成电路封装及具有该封装的计算机系统
                       发明背景
                      1.发明领域
本发明涉及高性能的集成电路封装。
                       2.背景技术
一般来说，由于电性能和热性能的要求，微处理器封装在陶瓷针栅阵列的封装中。特别是，指令执行速度很高的微处理器封装在微处理器设计上面临两个限制。首先，由于指令执行速度与功率消耗成一定的函数关系，并且由于微处理器高在指令执行速度下工作，所以节约能量成为微处理器封装设计上面临的一个限制。第二，高指令执行速度的微处理器要求封装减小向微处理器提供和撤消瞬时电源电流(例如，瞬时接地和瞬时Vcc电流源)的时间，以便电路节点尽可能快地充电和放电。
可以在印制电路(PC)板至管芯之间提供电源信号(例如，外加接地信号和Vcc电源信号)的最短通路来同时满足节约能源和时间限制。换句话说，由于电源信号在通路中遇到很少的障碍(即，电阻和电感)，所以可减小电源信号由PC板传输到管芯之间的距离来节约能源。而且，通过减小电源信号由PC板传输到管芯之间的距离也减小了由PC板到管芯之间提供和撤消瞬时电源电流的时间。
在过去，由于现有技术缩短电源信号通路(由PC板到芯片)的办法在其他类型的封装中经常不是很成功，所以微处理器大多数封装在陶瓷针栅阵列的封装中。现有技术缩短电源信号通路的一个方法是在封装中放置容性带电板。这些容性带电板(也称做薄层电容)接电源信号，这样就提供了一种可很快访问芯片的局部芯片上电源。
然而，容性带电板仅在几种类型的材料中实行。容性带电板生效的可行性取决于每个电源和接地板之间的最小间距以及封装的介电常数。这样，由于陶瓷外壳有很高的介电常数并能提供很小的间隔距离，因此容性带电板可以在陶瓷封装中实行。然而，如上面所提到的，容性带电板不能在所有类型的封装中实行。例如，由于塑料封装具有较低的介电常数，并且不能在相邻的带电板之间提供很小的间距，所以便宜的塑料封装技术不能使用容性带电板来缩短电源信号的通路。
现有技术缩短电源信号通路的另一个方法是在封装上安装片式电容器，并将这些电容器与电源信号相接，以便这些电容器作为电源的局部源。然而，由于片式电容器很昂贵，所以这种现有技术的方法增加了微处理器的工艺成本。
因此，需要提供一种用于微处理器能有效地节约能源和缩短电源信号由PC板传递到管芯的时间的封装方法和装置。特别是，用于微处理器能提供由PC板到管芯的最短电源信号通路，而不必使用容性带电板(不能在所有类型的封装中实行)且不必利用片式电容器(价格昂贵)的一种封装方法和装置。
                        发明概述
本发明的目的在于提供一种用于能有效地节约能源和缩短电源信号由PC板传递到管芯的时间的微处理器的封装方法和装置。特别是，本发明的目的在于提供一种用于微处理器的封装方法和装置，它能提供由PC板到管芯的最短电源信号通路，而不必使用容性带电板以及片式电容器。
本发明的这些和其他目的由放置在印制电路(PC)板上的高性能集成电路的封装实现。这种高性能的封装有第一介质层，其上为金属化管芯焊盘和第一金属环，第一金属环环绕金属化管芯焊盘。金属化管芯焊盘和第一金属环与PC板电连接用于分别接受第一电源信号和第二电源信号。然后将集成电路管芯贴在金属化管芯焊盘上。该集成电路管芯有第一电源信号焊盘和第二电源信号焊盘，分别连接金属化管芯焊盘和第一金属环。因此，金属化管芯焊盘和第一金属环用作第一电源板和第二电源板，将来自PC板上的第一和第二电源信号接到集成电路管芯的第一和第二电源信号的焊盘上。
                         附图简述
浏览以下的详细说明和附图之后，对本领域的普通技术人员来说，本发明的目的和优点将更明显。
图1为本发明的一个实施例球栅阵列封装的俯视图；
图2为图1球栅阵列封装的侧面剖视图；
图3为图1球栅阵列封装的放大剖视图。
图4为本发明内置有通用计算机系统的微处理器的高性能集成电路封装。
                        发明详述
本发明提供一种利用高性能的球栅阵列(BGA)封装的集成电路封装的方法和装置。特别是，由于焊料球以相邻球之间较小的距离(例如，50密耳)贴到集成电路的封装中，因此BGA封装可以有很高的焊料球密度。同样，BGA封装很高的焊料球密度使的它有较小的尺寸。如下面将介绍的，本发明的封装设计将利用高焊料球密度及小尺寸的BGA封装提供最短的电源信号通路。
在以下的说明中，介绍大量的细节是为了更彻底地理解本发明。然而，很明显本领域的普通技术人员可以不采用这些特定的细节也可以实施本发明。例如，虽然本发明下面的介绍是针对BGA封装，但是本领域的普通技术人员应该理解，，如果针栅阵列(PGA)封装的管脚密度和相邻管脚的间距与BGA封装的球密度和相邻球的间距相当，那么针栅阵列(PGA)封装也可以采用本发明。
图1-3为本发明的封装方法和装置的一个实施例。如图中所示，塑料封装10内有集成电路12，本发明的一个实施例为微处理器。此外，虽然介绍了塑料封装作为本发明的图1-3所示实施例，但应该理解，封装10可以由其他类型的材料组成。封装10有多个贴在封装下表面的连接体14。这些连接体与PC板上的金属焊盘形成接触，因此将封装10连到PC板上。对于图1-3的本发明实施例，连接体为焊料球。然而，如上面提到的，如果密度和相邻的间距与BGA封装的球密度和相邻球的间距相当，那么也可以使用其他类型的连接体(例如，管脚)。
对于图1-3中本发明的实施例，封装10有以下三层介质材料：第一介质层16、第二介质层18，和第三介质层20。在封装10的第一介质层的上表面上，第一金属化管芯焊盘22贴到封装10上。在本发明的一个实施例中，第一金属化管芯焊盘22通过层压工艺贴合到封装10上。该管芯焊盘通过电镀通孔24与第二金属化焊盘26进行电连接和热连接，而第二金属化焊盘26附着在第一介质层16的下表面上。同样，通过与第二金属化焊盘26相连的焊料球14a，第一金属化管芯焊盘22接PC板上的第一电源信号。在图1-3的本发明的实施例中，第一电源信号为中心接地电源信号Vss。然而，应该理解，第一电源信号可以为许多不同类型电源信号中的任何一种。
然后通过电和热导电粘合剂将微处理器管芯12粘合在第一金属化管芯焊盘22上。微处理器管芯12包含多个焊盘，这些焊盘包括中心接地焊盘28、周边接地焊盘30、中心Vcc焊盘32、周边Vcc焊盘34、和分立的信号焊盘36。中心接地焊盘通过焊线与管芯焊盘22短接。这样，由管芯上的中心接地焊盘到PC板上的中心接地电源信号间的最短电通路(即，最低电感)就通过第一金属化管芯焊盘22、通孔24、第二金属化焊盘26，和焊料球14a建立起来。这个最短通路与管芯尺寸和封装尺寸无关。
封装10还包括在第一介质层16的顶面和底面上环绕金属化焊盘的第一金属环38。第一组金属环的顶面环38a和底面环38b通过电镀通孔40相互电连接和热连接。通过焊料球14b，底面的第一金属环接PC板上的第二电源信号。在图1-3的本发明实施例中，第二电源信号为中心Vcc电源信号。然而，应该理解，第二电源信号可以为许多不同类型电源信号中的任何一种。微处理器管芯上的中心Vcc焊盘都通过焊线与顶面的第一金属环短接。这样，由管芯上的中心Vcc焊盘到PC板上的中心Vcc电源信号间的最短电(即，低电感)通路就通过顶部第一金属环38a、通孔40、底面的第一金属环38b，和焊料球14b建立起来。
还如图所示，封装10还包括在第一介质层16的顶面和底面上环绕金属化焊盘及第一组金属环的第二组金属环42。第二组金属环的顶面环42a和底面环42b通过电镀通孔44相互电连接和热连接。通过焊料球14c，底面第二金属环接PC板上的第三电源信号。在图1-3的本发明的实施例中，第三电源信号为周边接地电源信号Vssp。然而，应该理解，第三电源信号可以为许多不同类型电源信号中的任何一种。
微处理器管芯上的周边接地焊盘都通过焊线与顶部的第二金属环短接。以这种方式，第二组金属环将管芯上的周边接地焊盘与PC板上的周边接地电源信号连接起来。本发明的该实施例提供周边电源连接是为了将微处理器的中心活动(例如，执行指令)使用的电源与微处理器的周边活动(例如，和其他器件通信)使用的“噪声器”电源隔离开。
还如图所示，封装10还包括两列键合销(bond fingers)。第一列键合销46和金属化管芯焊盘22、第一顶面金属环38a，和第二顶面金属环42a一起放置在第一介质层16(组成第一较低粘合架)的顶面上面。第一列键合销46有许多用于分立信号连接的分立信号键合销。特别是，微处理器管芯上的指定信号焊盘可以将来自PC板的指定信号通过焊线指定的信号焊盘接到指定的信号销上；同样，指定的信号销将沿封装的长度或宽度方向(即，沿封装的长度或宽度的部分或封装的整个长度或宽度)的分立轨迹与PC板上接受指定信号的分立通孔和分立焊料球连接起来。
第二列键合销48放置在第三介质层20(组成第二较高粘合架)的顶面，而第三介质层20位于第二介质层18的顶部。如图1-3所示，第二和第三介质层环绕第一金属化管芯焊盘22、第一顶面金属环38a、第二顶面金属环42a，和第一列键合销46。此外，第二和第三介质层与封装的中心轴偏离一预定量，以便露出管芯焊盘、顶部金属线，和第一列键合销。
第二列键合销包括两种类型的键合销。第一种类型的键合销为第四电源键合销50，显示在图1中的是较长的键合销。这些第四电源键合销横越第一、第二，和第三介质层形成的凹槽的边缘，并连接位于第二介质层的顶面和第三介质层的底面间的金属化板54。该金属化板通过至少一个通孔连接至少一个焊料球，同时连接PC板上的第四电源信号。以这种方式，金属化板54缩短了所有第四键合销到第四电源信号的距离。
在图1-3的本发明的实施例中，第四电源信号为周边Vcc电源信号(Vccp)。然而，应该理解，第四电源信号可以为许多不同类型电源信号中的任一种。此外，如上面所提到的，本发明的实施例提供了周边Vcc电源信号连接，以便将用于微处理器的中心活动的Vcc电源信号与用于微处理器的周边活动的“噪声器”Vcc电源信号隔离开。
在图1-3的本发明的实施例中，第二列键合销也包括第二种类型的键合销。然而，应该理解，在本发明的另一实施例中，第二列键合销仅包括第四电源键合销。在图1-3的实施例中，在第二列上的第二种类型的键合销为附加分立信号键合销52，每个指定的信号键合销将微处理器管芯上的指定信号焊盘通过焊线互连、特定的条痕(横越封装的长度或宽度)、特定的通孔，和特定的焊球连接来自PC板的指定输入信号。在这个实施例中，提供第二列分立的信号键合销以便管芯上的相邻信号焊盘连接到分立的信号键合销上。特别是，由于目前分立的键合销之间可获得的最小间距是200微米，而分立的焊盘之间可获得的最小间距是100微米，本发明的该实施例提供了第二列信号销以便相邻信号焊盘连接到分立的信号键合销上。最后，封装10具有还形成(与第一、第二，和第三介质层一起)凹槽的塑料顶部56，在凹槽中注入成模密封剂从而密封BGA封装的顶部。
图4为放置在通用计算机系统的微处理器中的应该理解高性能集成电路封装本发明。如图所示，计算机系统60放置在印制电路(PC)板62上，并包括总线64、微处理器66、高性能微处理器封装68、电源信号发生器70，和存储器72。高性能微处理器封装68连接微处理器66和总线64，以便在微处理器66和接到总线64上的器件间进行电源信号和非电源信号的通讯。对于显示在图4的本发明实施例，总线64将微处理器66与存储器72和电源信号发生器70相连。然而，应该理解，在本发明的另一实施例中，微处理器66可以通过两条不同的总线连接存储器72和电源信号发生器70。此外，在本发明的再一实施例中，电源信号发生器70没有设置在PC62板上来连接总线64。
这样，本发明就有许多优点。例如，使用由管芯到PC板的最短通路作为电源信号的通路(即，使用封装中心附近的球作为Vcc和接地连接)，本发明不必使用片式电容和容性带电板就可降低电源回路电感。此外，由于该设计使用封装中心附近的球作为电源连接，并且将封装外列的球用做信号连接，因此PC板上的信号路径得到简化(即，附加的布线层不必经过封装中心附近的球)。而且，本发明的方法和装置通过在一键合架(即，第一键合架)上设置管芯焊盘及第一和第二顶金属环，使封装顶面的金属环的外部区域适于信号连接，从而减少多层金属和衬底层。
应该意识到，以上介绍的发明可以为其他形式但并没有脱离公开内容的精神或基本特性。例如，虽然以上针对有两个键合架进行的介绍，但本领域的普通技术人员应该理解，本发明的可选实施例包括仅有一个键合架的集成电路封装。例如，本发明的一个实施例仅有一个键合架(1)由于代替第四电源键合销50和金属化板54，它使用环绕第二组金属环42的第三组金属环，将第四电源焊盘34接到PC板上的第四电源，(2)由于它仅使用一列信号键合销(即，第一列信号键合销46)，环绕金属化焊盘22、第一顶面金属环36a、第二顶面金属环42a，和第三顶面金属环，将管芯上的分立信号焊盘接PC板上的分立信号。这样，虽然结合附图介绍了一些典型的实施例，但应该理解，发明并不局限在以上介绍的细节，而应由所附的权利要求来限定。

Claims (19)

1.一种短接电源信号通路的集成电路封装，包括：
a)具有一顶面和一底面的第一介质层；
b)设于第一介质层顶面上，电连接于印制电路板以接收第一电源信号的一个顶面金属化焊盘；
c)设于所述顶面金属化焊盘上，以便露出一部分顶面金属化焊盘的集成电路管芯，所述集成电路管芯具有第一电源信号焊盘、第二电源信号焊盘和第三电源信号焊盘，所述第一电源信号焊盘连接于所述顶面金属化焊盘的外露部分；
d)一个围绕顶面金属化焊盘的顶面第一金属环，所述顶面第一金属环设于第一介质层顶面上，第二电源信号焊盘连接于顶面第一金属环；
e)一个接收第二电源信号的底面第一金属环，所述底面第一金属环设于第一介质层的底面，所述底面第一金属环连接于顶面第一金属环；
f)一个围绕顶面第一金属环的顶面第二金属环，所述顶面第二金属环设于第一介质层的顶面，第三电源信号焊盘连接于顶面第二金属环；
g)一个接收第三电源信号的底面第二金属环，所述底面第二金属环设于第一介质层的底面，所述底面第二金属环连接于顶面第二金属环。
2.根据权利要求1的短接电源信号通路的集成电路封装，其中集成电路管芯还具有第一非电源信号焊盘，该集成电路封装还包括围绕顶面第二金属环的第一列键合销，所述第一列键合销具有为接收第一非电源信号的第一键合销，所述第一非电源信号焊盘连接于所述第一键合销。
3.根据权利要求2的短接电源信号通路的集成电路封装，其中集成电路管芯还具有第四电源信号焊盘，该集成电路封装还包括：
a)位于第一介质层顶面上，以便外露顶面金属化管芯焊盘、顶面金属环、和第一列键合销的第二介质层；
b)位于第二介质层顶面上，以便外露顶面金属化管芯焊盘、顶面金属环、和第一列键合销的第三介质层；以及
c)位于第三介质层顶面上的第二列键合销，第二列键合销具有为接收第四电源信号的第二键合销，所述第二键合销连接于所述第四电源信号焊盘。
4.根据权利要求3的短接电源信号通路的集成电路封装，还包括一个位于第二和第三介质层之间的金属化平面，所述金属化平面将所述第四电源信号连接于所述第二键合销。
5.根据权利要求4的短接电源信号通路的集成电路封装，其中集成电路管芯还具有第二非电源信号焊盘，第二列键合销还具有为接收第二非电源信号的第三键合销，所述第三键合销连接于所述第二非电源信号焊盘。
6.根据权利要求4的短接电源信号通路的集成电路封装，其中所述集成电路为微处理器。
7.根据权利要求4的短接电源信号通路的集成电路封装，其中所述封装为球栅阵列封装。
8.一种位于印制电路板上的计算机系统，所述计算机系统包括：
a)总线；
b)连接所述总线的存储器；和
c)连接所述总线和所述印制电路板的短接电源信号通路的集成电路封装，所述封装包括：
d)具有一顶面和一底面的第一介质层；
e)设于第一介质层顶面上，电连接于印制电路板以接收第一电源信号的一个顶面金属化焊盘；
f)设于所述顶面金属化焊盘上，以便露出一部分顶面金属化焊盘的集成电路管芯，所述集成电路管芯具有第一电源信号焊盘、第二电源信号焊盘和第三电源信号焊盘，所述第一电源信号焊盘连接于所述顶面金属化焊盘的外露部分；
g)围绕顶面金属化焊盘的一个顶面第一金属环，所述顶面第一金属环设于所述第一介质层的顶面上，第二电源信号焊盘连接于顶面第一金属环；
h)一个接收第二电源信号的底面第一金属环，所述底面第一金属环设于第一介质层的底面，所述底面第一金属环连接于顶面第一金属环；
i)一个围绕顶面第一金属环的顶面第二金属环，所述顶面第二金属环设于第一介质层的顶面上，第三电源信号焊盘连接于顶面第二金属环；
j)一个接收第三电源信号的底面第二金属环，所述底面第二金属环设于第一介质层的底面，所述底面第二金属环连接于顶面第二金属环。
9.根据权利要求8的计算机系统，其中集成电路管芯还具有第一非电源信号焊盘，该集成电路封装还包括围绕顶面第二金属环的第一列键合销，所述第一列键合销具有为接收来自印制电路板的第一非电源信号的第一键合销，所述第一非电源信号焊盘连接于所述第一键合销。
10.根据权利要求9的计算机系统，其中集成电路管芯还具有第四电源信号焊盘，该集成电路封装还包括：
a)位于第一介质层顶面上，以便外露顶面金属化管芯焊盘、顶面金属环、和第一列键合销的第二介质层；
b)位于第二介质层顶面上，以便外露顶面金属化管芯焊盘、顶面金属环、和第一列键合销的第三介质层；以及
c)位于第三介质层顶面上的第二列键合销，第二列键合销具有为接收第四电源信号的第二键合销，所述第二键合销连接于所述第四电源信号焊盘。
11.根据权利要求10的计算机系统，其中集成电路封装还包括一个位于第二和第三介质层之间的金属化平面，所述金属化平面将所述第四电源信号连接于所述第二键合销。
12.根据权利要求11的计算机系统，其中集成电路管芯还具有第二非电源信号焊盘，第二列键合销还具有为接收来自印制电路板的第二非电源信号的第三键合销，所述第三键合销连接于所述第二非电源信号焊盘。
13.根据权利要求8的计算机系统，其中所述集成电路为微处理器。
14.根据权利要求8的计算机系统，其中所述封装为球栅阵列封装。
15.一种短接电源信号通路的集成电路封装，包括：
a)具有第一和第二表面的第一介质层；
b)第一金属化焊盘，所述第一金属化焊盘设于第一介质层上；
c)设于所述第一金属焊盘上，以便外露一部分第一金属化焊盘的集成电路管芯，所述集成电路管芯具有第一电源信号焊盘、第二电源信号焊盘、第三电源信号焊盘和第四电源信号焊盘，所述第一电源信号焊盘连接于所述第一金属化焊盘的外露部分；
d)设于第一介质层的第二表面上的第二金属化焊盘，所述第二金属化焊盘连接于所述第一金属化焊盘，用于连接印制电路板以接收第一电源信号；
e)围绕金属化焊盘的第一顶面金属环，所述第一顶面金属环设于第一介质层的第一表面上，所述第二电源信号焊盘连接于第一顶面金属环；
f)围绕第二金属化焊盘的一个底面第一金属环，所述底面第一金属环设于第一介质层的第二表面上，所述底面第一金属环连接于所述第一顶面金属环，用于电连接印制电路板以接收第二电源信号；
g)围绕第一金属环的第二金属环，所述第二金属环设于第一介质层上，所述第二金属环用于接收第三电源信号，所述第三电源信号焊盘连接于第二金属环；
h)围绕第二金属环的第一列键合销，所述第一列键合销具有第一键合销，用于接收来自印制电路板的第一非电源信号，所述第一非电源信号焊盘连接于所述第一键合销；
i)位于第一介质层顶面上，以便外露第一金属化管芯焊盘、顶面第一金属环、第二金属环和第一列键合销的第二介质层；
j)位于第二介质层顶面上，以便外露第一金属化管芯焊盘、顶面第一金属环、第二金属环和第一列键合销的第三介质层；和
k)位于第三介质层上的第二列键合销，第二列键合销具有用于接收第四电源信号的第二键合销，所述第二键合销连接于所述第四电源信号焊盘。
16.根据权利要求15的短接电源信号通路的集成电路封装，还包括一个位于第二和第三介质层之间的金属化平面，所述金属化平面将所述第四电源信号连接到所述第二键合销。
17.根据权利要求15的短接电源信号通路的集成电路封装，其中集成电路管芯还包具有第二非电源信号焊盘、第二列键合销还具有第三键合销，用于接收来自印制电路板的第二非电源信号，所述第三键合销连接于所述第二非电源信号焊盘。
18.根据权利要求15的短接电源信号通路的集成电路封装，其中所述集成电路为微处理器。
19.根据权利要求15的短接电源信号通路的集成电路封装，其中所述封装为球栅阵列封装。
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JP3758678B2 (ja) 2006-03-22
GB2312786B (en) 1999-07-28
US5982632A (en) 1999-11-09
WO1996023320A1 (en) 1996-08-01
JPH10513012A (ja) 1998-12-08
GB9713489D0 (en) 1997-09-03
GB2312786A (en) 1997-11-05
CN1178602A (zh) 1998-04-08
KR19980701636A (ko) 1998-06-25
HK1004702A1 (en) 1998-12-04

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