CN1149198A - Method for manufacturing MOS transistor with low dosed drain and upside-down T shape grid and its structure - Google Patents
Method for manufacturing MOS transistor with low dosed drain and upside-down T shape grid and its structure Download PDFInfo
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- CN1149198A CN1149198A CN 95115967 CN95115967A CN1149198A CN 1149198 A CN1149198 A CN 1149198A CN 95115967 CN95115967 CN 95115967 CN 95115967 A CN95115967 A CN 95115967A CN 1149198 A CN1149198 A CN 1149198A
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Abstract
A method for manufacturing low-doped drain of MOS transistor with reversed T-shaped grid and its structure are disclosed. The reversed T-shaped grid has longer silicide layer as lower layer and shorter tungsten layer as upper layer and its longitudinal cross section is in the shape of reversed T, resulting in easy control of uniformity during etching back to form the reversed T shape, low-resistance characteristics of polysilicon, suppressing the generation of hot carriers and high on/off current ratio of drain.
Description
The invention relates to the manufacture method and the structure thereof of MOS transistor, particularly about a kind of manufacture method and structure thereof with upside-down T shape grid MOS transistor with low dosed drain.
Generally more do when entering the sub-micron manufacture process more for a short time when electronic component, meaning is that the contained transistor unit number of unit crystal grain (die) is more and more many, and then the horizontal direction size of transistor unit certainly will be dwindled.The size of element vertical direction comprises that the face junction depth (junc-tion depth) of source/drain electrode then has a multiple situation and a difficult problem.One is for reducing vertical dimension on a 50-50 basis, and the face junction depth of source/drain electrode shoals and causes resistance to raise so, and source/drain surface impurity concentration reduces and influences the due electrical quantity of transistor.Because this method negative interaction is too big, therefore do not consider; Another kind is to keep original source/drain surface concentration and face junction depth thereof, and then the short channel of Xing Chenging (short channel) can make source electrode and drain electrode produce puncture (punch-through) phenomenon, causes the element collapse to use.Moreover be increase source/drain surface concentration and reduce its face junction depth, though it is constant to keep source/drain electrode resistance, but because of impurity concentration gradient (gradient), form big electric field strength and produce hot electron (hotelectron), this hot electron is the injector grid oxide layer very easily, make this grid oxic horizon quality variation and limit voltage (threshold Voltage) shakiness, the reliability of element is worsened.
For solving problems such as aforesaid jitty and hot electron, adopt low dosed drain (lighly doped drain is to call LDD in the following text) structure the earliest, as shown in Figure 1, Fig. 1 is a nmos pass transistor.Itself and traditional not existing together mainly are N
+Source/drain region no longer is adjacent under the grid G, but mat low concentration doping N
-Source/drain region separates the two.Be applied to N so
+The then most of N of the pressure drop of drain electrode across high value
-On the drain region, therefore the electric field strength between its gate edge of conventional crystal tube elements and drain edge will be weakened, and produce oppressive thermionic effect.While N
-Depletion region (depletionregion) between source/drain electrode and the substrate of P type is limited in major part in N source/drain region, so the source electrode depletion region is difficult for contacting with the depletion region that drains, and meaning is that transistorized puncture voltage is improved.
Though the LDD structure can solve the ill effect of jitty, it is simultaneously also because of N
-High value and reduce the conducting electric current of drain electrode, cause transistorized conduction and cut-off current ratio to diminish, and it is indeterminate to form digital signal.For addressing this problem, the present invention proposes upside-down T shape grid LDD structure.Its structure as shown in Figure 2, its grid includes the change layer polysilicon that upper strata 2 is short and lower floor 1 is long, and the vertical section is the font of falling T, lower floor's 1 polysilicon and N
-Source/drain electrode overlaid.Therefore when nmos pass transistor is in conducting state, be positioned at the beneath N of grid
-Source/drain surface will go out charge carrier with the substrate opposite conductivity type because of grid induction, i.e. electronics, and increase N
-The electron concentration of source/drain surface; Meaning is that upside-down T shape grid LDD structure has not only kept the advantage of LDD structure and nmos pass transistor that its conducting electric current can be more not traditional reduces.Yet lower floor's 1 polysilicon in the double-layered polycrystal silicon gate of Fig. 2 forms via the reverse etching of polysilicon.Because it is to adopt the mode of fixing time but not endpoint monitoring (endpointdetection) mode that this reverse etching adds, is therefore very easily causing the etching uniformity between wafer and wafer not enough on the production line, make crudy be difficult to control and improved manufacturing cost.Therefore just be necessary to propose a kind of manufacture method and structure thereof that solves the LDD of aforesaid drawbacks.
Main purpose of the present invention provides a kind ofly makes that integrated circuit processing is easy to control, stay in grade and the LDD that reduces the upside-down T shape grid MOS transistor of manufacturing cost make and structure.
Another purpose of the present invention provides and a kind ofly not only can keep the advantage of LDD structure and have upside-down T shape grid MOS transistor LDD manufacture method and the structure thereof that more traditional MOS transistor increases the conducting electric current and improves effects such as transistor turns/cut-off current compares.
The present invention also has a purpose to provide a kind ofly can obviously reduce upside-down T shape grid and N
-Coupling capacitance between source/drain electrode is with the LDD manufacture method and the structure thereof of the upside-down T shape grid MOS transistor that improves element switch speed.
For overcoming the above problems, the invention provides a kind of LDD manufacture method with upside-down T shape grid MOS transistor, its step comprises:
In the first conduction type silicon substrate, form grid oxic horizon, first silicide, tungsten layer and silicon nitride layer in regular turn;
Covering a photoresist layer and form pattern through photographic process, is that mask is moving to this silicon nitride layer with design transfer through being etched with this photoresistance, with the definition gate regions again;
Be etching mask forms design transfer the inverted T-shaped grid to this tungsten layer the short metal level in upper strata with this silicon nitride layer again;
Remove this silicon nitride layer, and implement the low concentration second conductive-type impurity ion and inject, then deposit an oxide layer and form first spacer around the tungsten layer edge through oppositely etching, annealing, and this low concentration second conductive-type impurity ion diffuse to form low concentration source/drain region;
With this first spacer and this tungsten layer is that etching mask is removed the unwanted part of this first silicide, and forms the first long silicide of lower floor of upside-down T shape grid, and then implementing the high concentration second conductive-type impurity ion injects formation high concentration source/drain region;
Remove the unwanted part of this grid oxic horizon, and pictograph becomes the method for first spacer the same, edge at this first spacer, this first silicide and this grid oxic horizon forms second spacer, to prevent the silicide of subsequent deposition in source/drain electrode and the improper short circuit of inverted T shape;
Deposit second silicide and it is only stayed on source/drain electrode and the grid through selective etch.
For solving the problems of the prior art, the present invention also provides a kind of upside-down T shape grid MOS transistor LDD structure that has, and comprising:
One first conduction type silicon substrate contains the source/drain electrode of second conductive-type impurity of the source/drain electrode of low concentration second conductive-type impurity and high concentration;
One second silicide is positioned at this high concentration source/drain region and extremely goes up;
One grid oxic horizon is positioned in this first conduction type silicon substrate and its two ends and this source, drain electrode overlaid;
One upside-down T shape grid is positioned on this grid oxic horizon and by the long short tungsten layer of first silicide and upper strata of lower floor to be formed;
One first spacer is positioned at the edge of aforementioned tungsten layer;
One second spacer is positioned at the edge of this tungsten layer, this first silicide and this grid oxic horizon.
Upside-down T shape grid of the present invention mainly comprises long first silicide (silicide) of short tungsten (tungsten) in upper strata and lower floor, and its vertical section is to be the font of falling T, while N
-Source/drain electrode is to overlap under first silicide grids, and the mat grid oxic horizon separates.
Description of drawings:
Fig. 1 is traditional transistorized section of structure of NMOS LDD.
Fig. 2 is the section of structure of traditional double level polysilicon upside-down T shape grid LDD MOS transistor.
Fig. 3 A-3D is the section of structure according to each main manufacture process of upside-down T shape grid LDD MOS transistor of the present invention.
Be that embodiment explains detailedly the present invention in conjunction with the accompanying drawings below with the nmos pass transistor.
Because part IC manufacture process belongs to standard processing, for example the field oxide of the isolation usefulness of being grown up with local field oxidation (locos) etc. is not a theme of the present invention, does not repeat them here.
At first see also Fig. 3 A; in P type substrate 10 through the thermal oxidation grid oxic horizon 11 (representing) of growing up with oblique line; deposit one first silicide (silicide) 12 with the CVD method again; because silicide technology is very advanced at present; this first silicide 12 can be protected gate oxidation utmost point layer 11 simultaneously; avoid impaired in the RIE etching; the tungsten metal that also can prevent subsequent deposition in addition combines formation volatile oxidn (volatile oxides) with oxygen in the grid oxic horizon 11, thereby destroys the quality of grid oxic horizon 11.(WSix of titanium dioxide monosilane-dichlorosilane), having low fluorine content simultaneously is another advantage of this tungsten silicide and the best first silicide that meets above-mentioned condition is for containing DCS.The resistance value of this DCS-WSix is about 70 μ Ω after annealing in process, optimum thickness is several one hundred dusts (A).Afterwards, on this first silicide 12 more successively through CVD or sputtering method deposit tungsten (tungst-en) layer 13 of a thickness approximate number thousand dust (A), with CVD method deposited silicon nitride 14, and coating one photoresist layer 15.Then, with RIE etching of silicon nitride 14, and the pattern of photoresistance is passed on the silicon nitride 14, to define transistorized grid, as shown in Figure 3A via photoresistance 15 with pattern.
Then removing photoresistance and carry out the electric paste etching of tungsten layer 13, is to serve as the upper strata tungsten layer 13 that the erosion mask forms upside-down T shape grid with silicon nitride 14 at this moment, removes silicon nitride 14 with chemical solution simultaneously, promptly shown in Fig. 3 B.The low concentration impurity ion first time that carries out two secondary ion implantation steps in the LDD structure then injects, and is NMOS so adopt phosphonium ion because of present embodiment, forms low concentration N but the annealing steps of follow-up first spacer 16 of this phosphonium ion mat diffuses to substrate 10
-Source/drain region 101.Afterwards in entire wafer surface deposition one a low temperature oxide layer LTO and a reverse etching, make the LTO residue form first spacer (spacer) 16 at the edge of tungsten layer 13, this first spacer 16 and tungsten layer 13 can be used as the mask of the etching mask of follow-up first silicide 12 and high concentration impurities ion injection for the second time, to form lower floor's first silicide 12 and the high concentration N of upside-down T shape grid
+Source/drain region 102 is promptly shown in Fig. 3 c.
Afterwards, be etching mask and grid oxic horizon 11 unnecessary portions are removed with first spacer 16 and upside-down T shape grid again.Pictograph becomes the method for first spacer 16 the same simultaneously, forms second spacer 17 at the edge of first spacer 16, first silicide 12 and grid oxic horizon 11, to prevent the silicide of subsequent deposition in source/drain electrode and the improper short circuit of upside-down T shape grid.Then, with sputtering method deposit second silicide 18 (representing) with point-like and by solution optionally etching it is only stayed on source/drain electrode and the grid be connected resistance value and form upside-down T shape grid structure of the present invention with reduction.To form more good Ohmic contact in order making between second silicide 18 and source/drain electrode in addition, can optionally to carry out N for the third time
++The higher concentration foreign ion injects (but this selectivity step is not represented at Fig. 3 D).
The present invention compares with traditional upside-down T shape grid LDD structure obviously has following advantage:
The present invention because first silicide 12 has the high rate of etch ratio of selecting with grid oxic horizon 11, therefore can adopt endpoint monitoring when the etching upside-down T shape grid; And traditional two-fold polysilicon gate adopts the etching of fixing time, so the thickness of each layer of the present invention grid has the higher uniformity with traditional comparing, makes crudy be easy to control and reduction manufacturing cost;
The resistance of tungsten grid of the present invention is low far beyond polysilicon, and generally speaking, the square resistance of polysilicon is about 60 μ Ω, and the square resistance of tungsten is approximately less than 5 μ Ω.And the electricity of tungsten grid is led, and (transconductance is gm) than the increase by 30% of polysilicon, so can be than traditional higher conduction and cut-off current ratio, power amplification and switching rate that provide;
The work function of tungsten metal (work function) is positioned at the centre position that silicon can be with, and therefore makes the NMOS of tungsten grid provide identical limit voltage value with PMOS, is more suitable for the design of ultra-large type integrated circuit;
Silicide resistance of the present invention is little far beyond polysilicon, so silicide grids and N
-The negative interaction of overlapping formed coupling capacitance (as reducing the switching rate of element) can be compensated by the silicide of low resistance, and traditional this effect of not tool.
As described in the embodiment of front, the present invention has crudy compared with the prior art really and is easy to control and reduces manufacture cost and other advantages.Except that the disclosed embodiment in front, all simple combinations of being done in view of the above, etc. effect replace the scope also do not break away from the application's claim.
Claims (9)
1, a kind of manufacture method with low dosed drain of upside-down T shape grid MOS transistor, its step comprises:
In the first conduction type silicon substrate, form grid oxic horizon, first silicide, tungsten layer and silicon nitride layer in regular turn;
Covering a photoresist layer and form pattern through photographic process, is that mask is moving to this silicon nitride layer with design transfer through being etched with this photoresistance, with the definition gate regions again;
Be etching mask forms design transfer the inverted T-shaped grid to this tungsten layer the short metal level in upper strata with this silicon nitride layer again;
Remove this silicon nitride layer, and implement the low concentration second conductive-type impurity ion and inject, then deposit an oxide layer and form first spacer around the tungsten layer edge through oppositely etching, annealing, and this low concentration second conductive-type impurity ion diffuse to form low concentration source/drain region;
With this first spacer and this tungsten layer is that etching mask is removed the unwanted part of this first silicide, and forms the first long silicide of lower floor of upside-down T shape grid, and then implementing the high concentration second conductive-type impurity ion injects formation high concentration source/drain region;
Remove the unwanted part of this grid oxic horizon, and pictograph becomes the method for first spacer the same, edge at this first spacer, this first silicide and this grid oxic horizon forms second spacer, to prevent the silicide of subsequent deposition in source/drain electrode and the improper short circuit of inverted T shape;
Deposit second silicide and it is only stayed on source/drain electrode and the grid through selective etch.
2, the manufacture method with low dosed drain of upside-down T shape grid MOS transistor as claimed in claim 1 is characterized in that: described first conductivity type and second conductivity type are to be opposite conductivity type.
3, the manufacture method with low dosed drain of upside-down T shape grid MOS transistor as claimed in claim 1 is characterized in that: the etching of described tungsten layer and silicide is to adopt active-ion-etch.
4, the manufacture method with low dosed drain of upside-down T shape grid MOS transistor as claimed in claim 1 is characterized in that: described low concentration second conductive-type impurity injects used energy and need adjust and make it can't penetrate grid to channel region.
5, the manufacture method with low dosed drain of upside-down T shape grid MOS transistor as claimed in claim 1 is characterized in that: can implement the higher concentration second conductive-type impurity ion and inject so that good Ohmic contact to be provided after described deposition second silicide.
6, a kind of structure with upside-down T shape grid MOS transistor low dosed drain comprises:
One first conduction type silicon substrate contains the source/drain electrode of second conductive-type impurity of the source/drain electrode of low concentration second conductive-type impurity and high concentration;
One second silicide is positioned in this high concentration source/drain electrode;
One grid oxic horizon is positioned in this first conduction type silicon substrate and its two ends and this source, drain electrode overlaid;
One upside-down T shape grid is positioned on this grid oxic horizon and by the long short tungsten layer of first silicide and upper strata of lower floor to be formed;
One first spacer is positioned at the edge of aforementioned tungsten layer;
One second spacer is positioned at the edge of this tungsten layer, this first silicide and this grid oxic horizon.
7, the structure with upside-down T shape grid MOS transistor low dosed drain as claimed in claim 6, it is characterized in that: the source/drain electrode of described low concentration second conductive-type impurity is adjacent under the tungsten layer, and the source/drain electrode of high concentration second conductive-type impurity then is adjacent under first spacer.
8, the structure with upside-down T shape grid MOS transistor low dosed drain as claimed in claim 6 is characterized in that: described first conductivity type and second conductivity type are opposite conductivity type.
9, the structure with upside-down T shape grid MOS transistor low dosed drain as claimed in claim 6 is characterized in that: the source/drain electrode of described high concentration second conductive-type impurity contains the impurity of higher concentration second conductivity type so that good Ohmic contact to be provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN95115967A CN1046823C (en) | 1995-10-24 | 1995-10-24 | Method for manufacturing MOS transistor with low dosed drain and upside-down T shape grid and its structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN95115967A CN1046823C (en) | 1995-10-24 | 1995-10-24 | Method for manufacturing MOS transistor with low dosed drain and upside-down T shape grid and its structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1149198A true CN1149198A (en) | 1997-05-07 |
| CN1046823C CN1046823C (en) | 1999-11-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN95115967A Expired - Fee Related CN1046823C (en) | 1995-10-24 | 1995-10-24 | Method for manufacturing MOS transistor with low dosed drain and upside-down T shape grid and its structure |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1120523C (en) * | 1997-09-30 | 2003-09-03 | 西门子公司 | Reliable polysilicon-silicide grid laminate with reduced sheet resistance |
| CN1324655C (en) * | 2003-12-22 | 2007-07-04 | 台湾积体电路制造股份有限公司 | Novel process for improved hot carrier injection |
| CN101452853B (en) * | 2007-12-07 | 2010-09-29 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor forming method |
| CN101826457B (en) * | 2009-03-02 | 2012-03-07 | 中芯国际集成电路制造(上海)有限公司 | Production method of grid and MOS transistor |
| CN102130162B (en) * | 2010-01-18 | 2012-11-07 | 上海华虹Nec电子有限公司 | Laterally diffused MOSFET (LDMOS) and method for manufacturing same |
| CN104037084A (en) * | 2013-03-05 | 2014-09-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN104103587A (en) * | 2013-04-03 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method for semiconductor device |
| WO2015024478A1 (en) * | 2013-08-19 | 2015-02-26 | International Business Machines Corporation | Self-aligned gate contact structure |
| US9627460B2 (en) | 1998-11-17 | 2017-04-18 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a semiconductor device |
| CN111384160A (en) * | 2018-12-29 | 2020-07-07 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of field effect transistor, field effect transistor and grid structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162884A (en) * | 1991-03-27 | 1992-11-10 | Sgs-Thomson Microelectronics, Inc. | Insulated gate field-effect transistor with gate-drain overlap and method of making the same |
-
1995
- 1995-10-24 CN CN95115967A patent/CN1046823C/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1120523C (en) * | 1997-09-30 | 2003-09-03 | 西门子公司 | Reliable polysilicon-silicide grid laminate with reduced sheet resistance |
| US9627460B2 (en) | 1998-11-17 | 2017-04-18 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a semiconductor device |
| CN1324655C (en) * | 2003-12-22 | 2007-07-04 | 台湾积体电路制造股份有限公司 | Novel process for improved hot carrier injection |
| CN101452853B (en) * | 2007-12-07 | 2010-09-29 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor forming method |
| CN101826457B (en) * | 2009-03-02 | 2012-03-07 | 中芯国际集成电路制造(上海)有限公司 | Production method of grid and MOS transistor |
| CN102130162B (en) * | 2010-01-18 | 2012-11-07 | 上海华虹Nec电子有限公司 | Laterally diffused MOSFET (LDMOS) and method for manufacturing same |
| CN104037084A (en) * | 2013-03-05 | 2014-09-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN104037084B (en) * | 2013-03-05 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN104103587A (en) * | 2013-04-03 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method for semiconductor device |
| CN105745738A (en) * | 2013-08-19 | 2016-07-06 | 格罗方德半导体股份有限公司 | Self-aligned gate contact structure |
| US9324709B2 (en) | 2013-08-19 | 2016-04-26 | Globalfoundries Inc. | Self-aligned gate contact structure |
| WO2015024478A1 (en) * | 2013-08-19 | 2015-02-26 | International Business Machines Corporation | Self-aligned gate contact structure |
| CN105745738B (en) * | 2013-08-19 | 2018-07-31 | 格罗方德半导体股份有限公司 | Self-aligning grid contact structure |
| CN111384160A (en) * | 2018-12-29 | 2020-07-07 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of field effect transistor, field effect transistor and grid structure |
| CN111384160B (en) * | 2018-12-29 | 2023-09-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of field effect transistor, field effect transistor and grid structure |
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| Publication number | Publication date |
|---|---|
| CN1046823C (en) | 1999-11-24 |
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