CN1150617C - 半导体基板和层叠的半导体封装及其制作方法 - Google Patents

半导体基板和层叠的半导体封装及其制作方法 Download PDF

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CN1150617C
CN1150617C CNB981007147A CN98100714A CN1150617C CN 1150617 C CN1150617 C CN 1150617C CN B981007147 A CNB981007147 A CN B981007147A CN 98100714 A CN98100714 A CN 98100714A CN 1150617 C CN1150617 C CN 1150617C
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lead
main body
hole
base main
cavity
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CN1211821A (zh
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金朝汉
金振圣
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SK Hynix Inc
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Abstract

半导体基板和层叠的半导体封装及其制作方法，可以在有限的面积内实现高集成度的半导体组件。半导体基板包括：非导电的基板主体，其内部有多根已构图的导线；在基板主体的中心上部形成的腔体；垂直通过基板主体边缘部分的多个通孔。

Description

半导体基板和层叠的半导体封装及其制作方法
技术领域
本发明涉及半导体基板和层叠的半导体封装及其制作方法，尤其涉及改进的球栅阵列(BGA)半导体封装。
背景技术
图1是常规BGA半导体封装的示意图。如图所示，11是基板的主体。在基板主体11内分布多根已构图的导线(图未示出)。具有诸多芯片焊盘(图未示出)的半导体芯片13用粘合剂15粘接在基板主体11的上面。通过多根金属线17实现芯片焊盘与导电布线的连接。为了半导体芯片13和金属线17，形成模制部分18，以便用环氧树脂模制化合物模制基板主体的预定部分。此外，贴在基板11底表面上的数个焊球用于与基板11内形成的导电布线连接。然而，常规封装因其结构特点的限制，不可能将半导体芯片堆叠起来，因而不可能在有限的面积内实现具有高集成度的存储组件。
发明内容
本发明的目的是提供半导体基板和层叠的半导体封装及其制作方法，克服常规工艺中遇到的上述问题。
本发明的另一目的提供改进的半导体基板和层叠的半导体封装及其制作方法，以便在有限的面积内实现高集成度的半导体组件。
为了达到上述目的，提供一种半导体基板，包括：非导电的基板主体，其内部有多根已构图的导线；在基板主体的中心上部形成的腔体；垂直通过基板主体边缘的多个通孔；及填入每个通孔的导电金属棒，以及形成于基板主体上下表面上的导电外部端子，用于与每根金属棒的两端电连接。
为了达到上述目的，提供一种层叠的半导体封装，包括：非导电的基板主体，其内部有多根已构图的导线；基板主体的中心上部形成的腔体；垂直通过基板主体的边缘部分的多个通孔；安装在腔体的下表面的半导体芯片；用于连接半导体芯片与导电布线的多根导线；填充各个通孔的多根导电金属棒；贴在基板主体的上下表面的多个导电外部端子，用于与金属棒连接；填装于腔体中的模制化合物，用于模制半导体芯片和各导线。
为了达到上述目的，提供一种层叠的半导体封装的制作方法，包括如下步骤：制备其内部有多根已构图的导线的非导电的基板主体；形成具有在基板主体的中心上部形成的阶梯部分的腔体；形成垂直通过基板主体边缘的多个通孔；将半导体芯片安装在腔体的下表面；用第二导线(35)将半导体芯片和第一导线(22)电连接；在腔体内填充模制化合物，并模制半导体芯片和第二导线(35)；将导电金属材料填入每个通孔；将导电外部端子安装到基板主体上下表面上，用于与导电金属材料电连接；以及每根第一导线(22)的一端露在阶梯部分的上表面，而每根第一导线(22)的另一端则延伸到每个通孔。
为了达到上述目的，提供一种层叠的半导体封装的制作方法，包括，制备非导电的基板主体，其内部形成有多根已构图的导线；形成具有在基板主体的中心上部形成的阶梯部分的腔体；在腔体附近形成垂直通过基板主体的多个通孔；把半导体芯片安装在腔体的下表面上；用第二导线(35)电连接半导体芯片与第一导线(22)；通过在腔体中填充模制化合物模制半导体芯片与第二导线(35)；准备层叠的半导体封装；对准形成于层叠的半导体封装中的通孔；把层叠的半导体封装叠在一起；将导电金属材料分别填入这样对准了的通孔；将最上层层叠的半导体封装的上表面和最下层层叠的半导体封装下表面的外部端子固定在一起，用于与导电金属材料电连接；以及每根第一导线(22)的一端露在阶梯部分的上表面，而每根第一导线(22)的另一端则延伸到每个通孔。
本发明的其他优点、目标和特点在下文的进一步描述将得更清楚。
附图说明
从以下的详细说明和各图可以更充分地理解本发明，各附图只是为了说明，所以本发明并不限于此，其中：
图1为常规球栅阵列半导体封装的剖面图；
图2是根据本发明的半导体基板的剖面图；
图3是根据本发明的层叠的半导体封装的剖面图；
图4A至4D是根据本发明的层叠的半导体封装制作方法的剖面图；
图5A至5C辊根据本发明的堆叠半导体封装组件制作方法的剖面图。
具体实施方式
下面将说明半导体基板、用其制造的层叠的半导体封装、半导体组件及其制造方法。
图2是根据本发明的半导体基板的剖面图。如图所示，提供非导电的基板主体21，其内部装有多根构图的导线22。基板主体21上表面中心部分形成具有阶梯23的腔体24。在腔体24的两侧形成有多个通孔25垂直通过基板主体21。每根导线22的一端在阶梯部分的上表面露出，另一端延伸至相应的通孔25。
另外，导电金属棒26例如焊料棒被分别填入通孔25，基板主体21上下表面贴有外部端子27，用于与每根金属棒26的两端电连接。在此，金属棒26和外部端子27还可以按本发明另一实施例制作。
图3是根据本发明的层叠的半导体封装的剖面图。如图所示，运用图2的半导体封装封装半导体芯片。在图3的实施例中，与图2实施例相同的部件有相同的参考标记。
如图3所示，半导体芯片33用粘合剂31粘接在腔体24的下表面。多根导线35用于电连接半导体芯片33和导线22，模制化合物37填充腔体24，以此封装半导体芯片33和导线35。
现在根据图4A至4D来说明根据本发明的层叠的半导体封装制作方法。
首先，如图4A所示，非导电的基板主体21具有多根已构图的导线22，基板主体22的中心上部形成具有阶梯部分23的腔体24，在腔体24附近形成多个通孔25，垂直通过基板主体21，以便每根导线22的一端在阶梯部分的上表面露出，其另一端暴露于通孔25内。
如图4B所示，引线键合过程如下，半导体的芯片33用粘合剂31粘接在腔体24的底部，用导线33连接半导体芯片33和导线22。
其次，如图4C所示，模制过程如下，模制化合物填充腔体24，由此模制半导体芯片33和导线35。
此外，如图4D所示，可以进行金属材料填充过程，将导电金属材料26例如焊料棒填入到每个通孔25，导电的外部端子27例如焊料球粘在基板主体21的上下表面上，由此电连接每条导电金属材料26的两端。金属材料填入工序分成几步，先是将焊料棒填入通孔25，而后将其回流和硬化。
图5A到图5C是根据本发明的层叠的的半导体封装组件制作方法的剖面图。
如图5A所示，将层叠的的半导体封装100，110和120堆叠在一起，如图4所示。堆叠时，应将层叠的的半导体封装100，110和120精确对准，同时对准形成于层叠的的半导体封装100，110和120上的通孔25。
如图5B所示，在金属材料填入步骤，将导电金属材料26填入到这样对准的通孔25。在此，金属材料填入过程分成几步，先是将焊料棒分别填入对准的通孔25，后再回流和硬化。
如图5C所示，导电外部端子27分别贴在最上层层叠的半导体封装120的上表面和最下层层叠的半导体封装100下表面上，由此电连接每个导电金属材料27的两端，从而制备根据本发明的层叠的的半导体封装组件。
如上所述，根据本发明，采用半导体基板封装半导体芯片可以制成层叠的半导体封装。此外，按照本发明，采用层叠的半导体封装有可以在有限的面积内作成高集成度的半导体封装组件。而且，采用层叠的的半导体封装中形成的通孔可以精确对准并堆叠每个半导体封装，通过填入通孔的导电金属材料(焊料棒)可电连接每个封装内的半导体芯片。
虽然为了说明披露了本发明的优选实施例，但在不背离本发明所附权利要求的范围和精神的情况下，本领域的普通技术人员可以作出各种修改，增加和替代。

Claims (5)

1.一种层叠的半导体封装的制作方法，包括如下步骤：
制备其内部有多根已构图的导线的非导电的基板主体；
形成具有在基板主体的中心上部形成的阶梯部分的腔体；
形成垂直通过基板主体边缘的多个通孔；
将半导体芯片安装在腔体的下表面；
用第二导线(35)将半导体芯片和第一导线(22)电连接；
在腔体内填充模制化合物，并模制半导体芯片和第二导线(35)；
将导电金属材料填入每个通孔；和
将导电外部端子安装到基板主体上下表面上，用于与导电金属材料电连接，
其中，每根第一导线(22)的一端露在阶梯部分的上表面，而每根第一导线(22)的另一端则延伸到每个通孔。
2.如权利要求1的层叠的半导体封装的制作方法，其特征在于，所说外部端子是焊料制成的。
3.如权利要求1的层叠的半导体封装的制作方法，其中，所说的将导电金属材料填入每个通孔包括步骤：
将焊料棒填入通孔；和
对焊料棒进行回流和硬化。
4.一种层叠的半导体封装组件的制作方法，包括如下步骤：
制备其内部有多根已构图的导线的非导电的基板主体；
形成具有在基板主体的中心上部形成的阶梯的腔体；
在腔体附近形成多个通孔垂直通过基板主体；
将半导体芯片安装在腔体的下表面；
用第二导线(35)将半导体芯片和第一导线(22)电连接，并且在腔体填充模制化合物，以模制半导体芯片和第二导线(35)；
堆叠上述半导体封装；
对准上述堆叠的半导体封装的通孔；
将导电金属材料分别填入对准的通孔；和
将导电外部端子贴在最上层半导体封装的上表面和最下层半导体封装的下表面，用于与导电金属材料电连接，
其中，每根第一导线(22)的一端露在阶梯部分的上表面，而每根第一导线(22)的另一端则延伸到每个通孔。
5.如权利要求4的层叠的半导体封装组件的制作方法，其特征在于，所说的将金属材料分别填入对准的通孔的步骤包括将焊料棒分别填入对准的通孔，然后回流和硬化焊料棒。
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