CN1158006A - 具有降低应力成模衬底部分的挠性层的高密度互连电路模件 - Google Patents

具有降低应力成模衬底部分的挠性层的高密度互连电路模件 Download PDF

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CN1158006A
CN1158006A CN96120813A CN96120813A CN1158006A CN 1158006 A CN1158006 A CN 1158006A CN 96120813 A CN96120813 A CN 96120813A CN 96120813 A CN96120813 A CN 96120813A CN 1158006 A CN1158006 A CN 1158006A
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chip
substrate
molding material
flexible material
curing
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罗伯特·约翰·沃纳洛斯基
托马斯·伯特·高克立卡
史丹顿·伊尔·威佛二世
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Lockheed Martin Corp
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Lockheed Martin Corp
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    • H01L2924/3511—Warping

Abstract

本发明提供了一种高密度互连多芯片模件，在多芯片周围模铸聚合物衬底之前，将一降低应力的挠性材料置于各芯片周围。具有接触垫的芯片面向下置于由一基片所支持的一粘合剂层上。一挠性材料沉积于芯片周围，然后将一模具置于芯片周围。聚合物衬底模铸材料加进模具中，然后固化衬底模铸材料。一介质层置于固化的衬底模铸材料及芯片面上，其通孔与一个预定的接触垫对准，并具有电导体延伸穿过通孔。在衬底模铸材料加进之前，可将一热插塞固定于芯片的背面。

Description

具有降低应力成模衬底部分的挠性层的 高密度互连电路模件
本发明涉及改进的聚合物封装的多芯片模件，尤其涉及在集成电路芯片周围利用挠性材料降低工作模件内的应力。
高密度互连(HDI)结构在电子系统的紧凑组合上有许多优点。例如，多芯片电子系统(诸如装有30-50块芯片的微电脑)可由适当的高密度互连结构整个组合及互连于一单个衬底上，以形成单一包装，其长为2英寸，宽为2英寸，而厚为0.050英寸。更为重要的是，该互连结构可从衬底上拆离，以便修理或更换故障的组件，而不会对该系统内所装良好组件不构成危险。这在单一衬底上装有许多(例如50)值钱的芯片的单一系统中尤为重要。该可修理的特点较之先有技术的连接系统为一重大优点，在先有技术连接系统中，更换故障组件是不可能的或对良好组件存在极大危险。
简言之，在这种高密度互接结构中，提供有诸如由铝土之类的材料制成的陶瓷衬底，其厚为25-100mil及具有相对整个系统而言适当的大小及强度。此大小通常小于2平方英寸，但可制成更大或更小。一旦设定了各芯片的位置，在不同芯片的预定位置处制备单独的具有适当深度的孔或一大孔。此制备过程始于具有均匀厚度及所需大小的一块裸衬底。通常可使用超音波或激光制造各芯片及其他组件位置其中的孔。在各芯片边对边接近放置的许多系统而言，单个大孔即为一满意情况。此大孔通常具有均匀深度，在此，各半导体芯片具有大致均匀的厚度。孔底部在特别厚或薄的组件放置处可分别制成较深或较浅，以便对应组件的上表面大致在与其余组件上表面及包围该孔的衬底部份在同一平面上。孔的底面然后铺以热塑性粘合剂层，该层最好为聚醚亚胺树脂(诸如ULTEM6000树脂，由康州费尔非德城的通用电气公司供应)，或由美国专利5,270,371号(该专利结合于此以为参考)所述的粘合剂复合物。各组件然后置于孔内所需位置中，然后整个结构加热以除去溶剂，再将各组件通过热塑粘合于衬底上。
其后，厚约0.0005-0.003英寸(约12.5-75微米)的一薄膜(此可为KAPTON聚亚胺，由位于特拉华州威明顿市的杜邦公司供应)由反应性离子蚀剂(RIE)预处理以提高附着力。衬底及芯片然后需涂以ULTEM100聚醚亚胺树脂或其他热塑性粘合剂，以便当KAPTON树脂薄膜叠合于芯片，任何其他组件，以及衬底上时，粘合该薄膜。其后，设置通孔(最好由激光钻制)穿过KAPTON树脂薄膜及ULTEM树脂层，其位置与欲与之接触的电子组件上的接触垫对准。一个金属多层沉积于KAPTON树脂层上，并延伸进入通孔中，以便与其下之接触垫进行电接触，该金属多层具有包含钛的第一层及包含铜的第二层。该金属层可在沉积过程中进行布线制图，以形成各个导体，或可沉积成一连续层，然后使用光刻胶及蚀刻法进行布线制图。光刻胶最好由激光曝光，以便在处理结束处提供精确对准的导体布线图案。另一方案则是使用掩膜曝光。
用以隔离第一金属层及任何其后的金属层之间的任何另外的介质层可通过旋转或喷淋所需介质粘合剂材料溶液于热固性介质材料层的方式加上。目前，使用一矽氧烷聚亚胺/环氧树脂(SPIE)混合粘合剂作为粘合剂，以粘合其他的KAPTON层。由于介质材料使用于粘合剂及介质层中，故对该系统有特别要求。明确言之，为使最后之结构能适用于大温度范围，介质层(包含粘合剂)需具有高熔点及高热稳定性。任何侯选层需对其下的介质及金属及其上的介质层具有良好的附着力，且亦应本质上为可由激光蚀刻或应可变成可由激光蚀刻，如美国专利5,169,678号，题为“激光蚀刻的聚合物介质及方法”所述。各个电子组件及其接触垫的任何位置误差可由适当的激光制版系统补偿，此为以后所列一些专利及申请书的主题。
设计一互连布线图案来互连在一个高密度互连衬底上的一电子系统的所有芯片及组件的过程通常需时一日到五周。一旦互连结构定后，在衬底上及上面结构的系统的组合置于芯片及衬底上，每次一层。整个过程通常可在一日内完成，如C.W.艾查伯格等人的美国专利5,214,655号，题为“快速定制设计及独特测试能力的集成电路包装安排”中所述，该文在此列作参考。故此，此高密度互连结构不仅导致电子系统的重量大为减轻，而且其包装更为紧凑，而且可使原型系统能在较其他包装技术所需的更短时间内制成和测试。
高密度互连结构的制造方法及其制造工具说明于C.W.艾查伯格等人的美国专利4,783,695号，题为“多芯片集成电路包装安排及方法”；H.S.可尔等人的美国专利5,127,998号，题为“区域选择性金属化处理”；可尔等人的美国专利5,127,844号，题为“区域选择性金属化处理”；T.R.何拉等人的美国专利5,169,678号，题为“局部取向特定路由选择系统”；C.W.艾查伯格等人的美国专利5,108,825号，题为“环氧树脂/聚亚胺共聚物混合介质及含有此介质的成层电路”；及H.S.可尔等人的美国专利申请序号08/239,785，题为“含有改良的介质材料的高密度互连结构及制造方法”。这些专利及专利申请书及其中的参考资料在此列作参考。
如上所述，常规高密度互连(HDI)处理通常使用构制于衬底中的孔，供装置芯片之用，以致各芯片的顶表面大致与衬底的表面在同一平面。衬底通常为陶瓷或复合物结构。用以在衬底中制作孔的常规高密度互连技术是使用计算机控制的钻石工具钻头通过机械构制或磨制成孔。此费时方法并不总能产生所需的芯片孔深度，并会导致破裂，使衬底不能使用。
芯片置于磨制的孔中，并通过多滴模粘合剂由机械，热，及电固定。由此法置放的芯片在进一步处理期间中，由于芯片至模粘合剂界面处的表面拉力不均匀，会发生位移。位移降低芯片位置的精确度，从而需要另外的处理步骤，以使每一电互连适应芯片的不对齐。而且，在普通衬底中出现于芯片周围的沟道会使芯片周边处的聚合物薄膜的粘合剂减薄，并使聚合物薄膜在沟道上下陷，从而增加在芯片阱附近设置通孔及构制互连布线图案的难度。而且，陶瓷基体及聚合物层的不同热膨胀系统数有时在粘合剂层处产生应力，从而促使聚合物薄膜与衬底分离。
费利昂等人的美国专利5,353,498号，题为“集成电路模组的制造方法”中发表了一种制造高密度互连衬底的方法，其使用塑胶铸模于薄膜上所置的芯片周围，从而省除了磨制过程，并提供一个在芯片及衬底之间没有沟道的表面。简言之，该方法包含将一绝缘基片施加于一基底上。具有接触垫的至少一芯片面向下置于基片上。一模型置于所需周边周围，并包围至少一块芯片。加进基体模铸材料于模型内，并然后固化。然后去除模型及基底，并反转衬底并互连各芯片。当模铸材料包围并直接接触芯片时，由于芯片的矽与模铸材料的聚合物基质的热膨胀系数不同而产生应力。
为降低此应力，美国专利5,353,498号的实施例在加进衬底模铸材料之前，把一聚合物薄片置于芯片的背面。这在芯片之间留下了空气沟道，并降低一些应力集聚；然而，如上述，这类沟道的存在会使芯片周边处的聚合物薄膜的粘合剂减薄，并使沟道上的聚合物薄膜下陷。而且，用以模组散热的热插塞不能由此聚合物薄片包裹，因为有和没有散热塞的芯片间的厚度大不相同。
故此，需有一种塑胶模铸方法，其中，模型成为衬底的整体的一部分，用以防止衬底暴露于化学物中，并提供一种用于降低模组内的应力的机构。
故此，本发明的主要目的在于提供一种高密度互连模件，它具有创新的挠性层以作为降低应力，低翘曲，以及模铸塑胶衬底的一部分。
通过说明书，包括附图，可以明了，通过在以聚合物衬底铸模材料包裹芯片之前，将至少一挠性材料层置于多个积成电路芯片周围可以达到根据本发明的以上及其他目的。
简言之，根据本发明的一个优选实施例的一种用以构制积成电路衬底的方法使用的步骤包括：将一绝缘基片施加于一基底构件上，基片上铺以一粘合剂层。多个积成电路芯片(各具有接触垫)面向下置于基片上的粘合剂层上。至少一层挠性材料置于芯片的不含粘合剂的表面周围。然后，一模型置于所需的周边周围，并包围芯片及挠性材料。一聚合物衬底模铸材料加进模型中，以包裹芯片及挠性材料的所有表面，但含有接触垫至与粘合剂接触的芯片表面除外。聚合物材料然后在模型内固化。移去模型，然后设置高密度互连结构于芯片接触垫的表面。
基片可选择成为高密度互连结构的一个第一介质层。
本发明的主题由说明书特别指出并要求。参考以下说明及附图，可明了本发明及其目的和优点，各图中相同的编号标示相同的组件，其中：
图1(a)为芯片的断面图，芯片面向下置于涂有粘合剂的薄膜层上，它可包含完成的模件中的一个互连层的一部分；
图1(b)为与图1(a)相似的断面图，显示一挠性材料置于各芯片间及周围；
图1(c)为与图1(b)相似的断面图，另显示一模型置于芯片及挠性材料周围，并包含衬底模铸材料；
图1(d)为与图1(c)相似的断面图，显示在模型移去后，芯片埋置于衬底模铸材料中，并具有挠性材料置于芯片间及周围；
图1(e)为与图1(d)相似的断面图，显示加在成模衬底上的一高密度互连结构衬底；
图2为二芯片的断面图，该二芯片面向下置于涂有粘合剂的薄膜上并具有的挠性材料层；
图3为用以构制及固化衬底模铸材料的一个优选层合器及模型的断面图；及
图4为与图1(c)相似的断面图，另显示热插塞置于芯片的背面以加强散热。
图1(a)为多个芯片的断面图，包括电容器20及集成电路芯片14，集成电路芯片具有芯片垫15，并面向下置于一基片12上，基片由一基底构件10支持。基片12可包括由聚合物，诸如“KAPTON”聚亚胺(Kapton为杜邦公司的商标)薄膜层12b所构成，其涂以一接触粘合剂层12a，诸如“ULTEM”聚醚亚胺树脂(Ultem为麻州匹司非城的通用电气公司的注册商标)，或环氧树脂/聚亚胺共聚物混合物，诸如于1992年4月28日所颁发的同一受让人伍纳洛等的美国专利5,108,825号所公开的，该专利在此列作参考。可使用溶剂模附著，如1991年8月5日所提出的同一受让人艾查伯格等的美国专利申请序号07/745,982，题为“高密度互连热塑性模附著材料及溶剂模附著方法”所公开的，该文在此列作参考。“面向下”意为接触垫15与粘合剂层12a接触。基底构件10可包含任何结构(最好是刚性的)材料，诸如塑胶，陶瓷，或金属。
芯片14可包含任何电路组件，包括有源半导体芯片(诸如集成电路)及分立装置(诸如晶体管)，及无源组件(诸如电容器，电阻器，电感器，及转换器)。芯片14无需具有相同厚度，并可以任何常规方式与粘合剂层12a接触。在一实施例中，使用一检放机器18(部份显示)。在另一实施例中，各芯片精确置于一暂时表面，诸如具有低接触附著力的蜡或一薄膜，诸如由尼杜公司(称为“尼杜胶带”)及半导体装备公司(称为“蓝膜片”)所生产的膜片，然后在芯片仍附著于暂时表面上的期间，将其向下置于基片12上。当各芯片具有相同厚度时，使用暂时表面最为有效。
由粘合剂层12a及聚合物薄膜12b所构成的基片12可用作HDI结构的第一介质层，其中，一介质层通常包含一热塑性或热固性粘合剂，它施敷于完全固化的聚合物薄膜上。如需要，可建立多个粘合剂/介质/金属层，并加以处理使之成为全功能高密度互连结构(以下详细说明)，芯片14附著于最下面而且暴露的粘合剂层上。另一方面，基片12可为一牺牲层，使其在模铸后移去。如基片用作第一介质层，则粘合剂及聚合物层二者宜可由波长为350-370nm范围内的激光进行蚀刻。在一优选实施例中，暂时使用一可选择的片框16，以保持基片在基底构件10上平坦。片框16普通为不锈钢，钼，或钛所制，但可为任何适当的结构材料所制。在芯片附著后，可使用诸如反应离子蚀刻处理，以清洁矽模片的背面，并粗化粘合剂12a，以提高附著力。可任选地，在进一步模组处理之前，可由已知方法施敷一附著力促进剂(未显示)，诸如VM-651(由DE的威明顿城的杜邦公司供应)于粘合剂12a上。
依据本发明，图1(b)显示一挠性层17，置于粘合剂12a背面，并包围芯片14。挠性材料17可施放于芯片14背面，使用本技术领域一般技术人员所熟悉的多种方法，诸如由微注射器，旋转施敷等，将其喷淋，浸渍，散布于各芯片之间。挠性材料17设计用作防震座，以打破及降低可能由芯片14及模铸化合物间的热膨胀系数差所产生的任何应力。(以下详细讨论)。
挠性材料17可包括多种材料，例如紫外线(UV)及热可固化的丙烯酸酯，UV及热可固化的环氧树脂，聚亚胺，及环氧树脂聚亚胺混合物，诸如SPIE，参见1992年4月28日颁发给伍纳洛等人的美国专利5,108,825号，题为“环氧树脂/聚亚胺共聚物混合物介质及含有该介质的成层电话”。挠性材料17中可包含微粒，纤维，网，垫片，或板状填料。填料的型式及含量可用以改变材料性质，诸如导热系数及热膨胀系数，以适应模件需求。例如，挠性材料17可包含玻璃。SiC，Al2O3，或AIN等无机微粒，钻石或石墨微粒，银或铜金属微粒。玻璃，SiC，AIN，钻石，氧化矽，及石墨具有低热膨胀系数，而挠性材料聚合物及金属则具有较高的热膨胀系数。导热性材料包括SiC，AIN，铜，石墨，氧化矽，及钻石，而以石墨及钻石为优选导体。
一种现有的优选挠性材料17包含SPIE聚合物材料，它由约百分之六十重量的SPI固体及约百分之四十重量的环氧树脂固体混合构成。此聚合物再与微分散的微化的二氧化矽微粒，诸如S-5631微化二氧化矽(由密苏里州圣路易城的Sigma化学公司供应)混合，以产生具有约百分之五十五重量的二氧化矽微粒，约百分之二十七重量的SPI固体，约百分之十八重量的环氧树脂固体于适当溶剂(诸如diglyme)中的最后复合物。二氧化矽宜具有的直径约为2至5微米之间。二氧化矽降低挠性材料17的热膨胀系数至接近芯片14。在一些情形，可能需制造沟区围绕芯片，同时仍留一些挠性材料，以降低模件应力。在此情形，挠性材料17应可由激光蚀刻，或使其能由激光蚀刻，如可尔等的美国专利5,169,678号，题为“可由激光蚀刻的聚合物介质及方法”中所述。去掉SPIE混合物的溶剂及完全固化SPIE混合是由一斜烤步骤在一对流炉中以约100℃至200℃加热，然后保持于此第二温度上约30分钟而实现的。
当移去溶剂及聚合物混合物固化时，挠性材料17收缩，且从而仅填塞芯片14之间约百分之五十的高度。各芯片14间百分之五十的填塞在许多应用上已足够了，然而，当芯片14的密度特别高时，即具有15mil间隔的25块芯片时，则需要较厚的挠性材料层17，如图2所示。为制造厚层，合并二层17a及17b，以构成一厚层挠性材料17。这通常是由在一个第二应用中沉积SPIE(17b)来完成的，另一方案则是由百分之一百的固体混合物构成一厚层的挠性材料17，例如，使用液体环氧树脂或UV可固化的丙烯酸，在此情形，可在单一应用中实现完全填充。当此无溶剂层固化时，不会发生溶剂丧失，故收缩最小。制造一厚层17的挠性材料的另一方法为于第一层17a上沉积一第二层(17b)的另一挠性材料，诸如矽酮，例如矽酮RTV，丙烯酸酯等。在第二层17b的挠性材料固化后，其厚度约为18-22mil，此约为集成电路芯片14的厚度。对大部分模件来说，确信芯片14并不完全浸没于挠性材料17中。然而，应明了在本发明范围之内，芯片亦可完全浸没于挠性材料17内。
图1(c)为图1(b)装置的断面图，显示一模型22置于芯片周围，并填以衬底模铸材料24。模型22可包含能制造“衬底”形状的任何适当结构，且可为能在热及压力下制造及固化该“衬底”的结构，如图3所示。然而，图3所示模型仅以如何制造模铸材料24为一可用形状的优选实例来显示。其他较不复杂的设计可包含简单的壁，该壁可保持基于液体的模铸材料24，直至其固化为适当形状为止。模型22可由任何结构材料，包括例如塑胶或金属构制，且如设计许可，可在进一步处理期间与铸成的衬底保持一起，或在模铸后移去。可移去的模型可为牺牲或再用。如该模型可再用，则在模铸材料注入模型之前，可喷淋一释放剂(未显示)，诸如TEFLON四氟乙烯(TEFLON为杜邦公司的商标)，矽酮，或非粘性的植物油于其上。
可能的衬底模铸材料24包含，但不限于脂族及芬芳族聚合物，包括热塑性及热固性的聚合物及各种聚合物的混合物，诸如ULTEM聚醚亚胺树脂，丙烯酸酯，聚氨基甲酸乙酯，TEFLON聚四氟乙烯，环氧树脂，苯并环丁烯(BCB)聚亚胺，或其他聚合物。模铸材料24中亦可包含微粒，纤维，网，垫片，或板形状填料。如上述(在讨论挠性层17的填料中)，填料的型式及分量可用以改变各种模铸材料的特性，诸如导热系数及热膨胀系数，以满足模件的需求。
一种优选的模铸材料为转移模铸粉，诸如Hysol MG48F(由纽约州奥利安城的Dexter公司供应)或Plaskon SMT-B-1(由加州阿发达城的Amoco电子材料公司可供应)。将优选的模铸材料24施加于挠性涂覆晶粒背面，并置于一模型/层合器中(图3)。芯片及模型组合置于层合器中，将其预热至约200℃，然后施加真空约一分钟。一旦模型组合温度到达150℃时，施加每平方寸(psi)50磅的压力于不锈钢板上，压迫模铸化合物于模板形状中，并迫使多余的材料流出模板中所构制的出口孔。模铸材料24在压力下在200℃中固化30分钟。模型/层合器然后冷却至100℃以下，且压力降低至大气压力，并移出塑胶模铸件并加以修整(图1(b)及(c)中的区域300)。此时，已固化的塑胶模铸件可作进一步的HDI处理。
图1(d)为图1(c)装置的横断面，显示在模型22已移离模铸材料24，及基片12已修正及与基底构件10分离后埋置的芯片。
图1(e)为图1(d)装置的断面图，显示一多层HDI结构26置于模铸基体24上，并含有芯片20及14。HDI26结构包含一第一互连层28，含有一介质层12b，具有通孔30a，并支持一电导体布线图案32a；一第二层互连层29含有一介质层35，具有通孔30b，并支持一电导体布线图案32b。如需要，可施设其他互连层。构制及填塞通孔30a及30b的方法，构制电导体32a及32b的布线图案的方法，及制造一个或更多互连层19的方法说明于1992年11月3日哥兹卡等人的美国专利5,161,093号，1989年5月30日艾查伯格等人的美国专利4,835,704号，及1988年11月8日艾查伯格等人的美国专利4,783,695号，这些专利均转让给同一受让人，在此且列作参考。
当图1(e)所示的多芯片模件工作时，芯片14产生热。矽的膨胀系数普通约为4ppm/℃，而普通铸材料24的热膨胀系数则约为14ppm/℃。故此，当芯片14温度上升时，由于芯片14及模铸材料24间的膨胀不同，模件内的应力亦增加。挠性材料17具有低模数，且由於置於各芯片之间(在最大应力所在处)，故该材料能伸展，屈服，及消散此应力，使此应力不致到达高模数模铸材料。例如，一普通挠性材料(诸如由阿州凤凰城的微矽公司所供应的SPI135)具有模数约为100,000，而一普通铸材料(诸如Plaskon SMT-B-1)具有模数约为2,000,000。
多芯片模件内有其他应力源，低模数的挠性材料17可用於此。例如，一些模铸材料24在Z轴向(自模件的顶至底)具有较大收缩，此倾於使模件翘曲。克服此收缩的先有技术方法为在模铸材料24已固化后，由机械处理该模件，以产生可接受的模件。然而，使用挠性材料17，亦可大为降低这类其他的应力源，从而大为增加可再生一平面模件的能力。
图4为与图1(c)相似的断面图，含有热或热电插塞，显示如热插塞40置於芯片14的无源背面。这类插塞由银环氧树脂(未显示)粘合於芯片上，以供接地之用。本发明的一重大优点为热插塞40可用以发散芯片的背面上的热，同时使用挠性材料来确保整个模件内的应力最小。在所有先有技术的方法中，很难制造能装有热插塞的可靠及无应力的模件。
热插塞40所需的导热系数随模件的散热特性，所计划应用的环境，及电路的计划寿命而不同，虽然高导热系数的填料，诸如石墨，银环氧树脂，或钻石等足够用於大部份高功率应用，但在极高功率密度的情况下，诸如超过每模件100瓦的情形，热插塞34很有用。热插塞40可包含任何传导性材料，例如包括钼或铜或其混合物，诸如掺有铝的碳化矽基质，由Lanxide公司所制。如图4所示，模型22的高度不宜超过附着於芯片14上的热插塞40。热插塞40及模型22的选择使所制成的衬底及热插塞之外的边缘在同一平面中。
虽然以一些优选实施例来详细说明本发明，但本发明技术领域的一般技术人员可作许多修改及更改。故此，本发明仅由所附权利要求而非由此处所示的实施例限制。

Claims (21)

1.一种制造集成电路模件的方法，其特征在于包括以下步骤：
将一绝缘基片置于一基底构件上，该基片包含一聚合物薄膜，该薄膜具有一置于聚合物薄膜的一面上的粘合剂涂层，该聚合物薄膜的一面与所述基底构件相对；
面向下将具有接触垫的多个芯片面向下地置于所述基片的粘合剂涂层上；
将至少一层挠性材料置于所述多个芯片之间及周围；
施加基体模铸材料于所述芯片及挠性材料层周围；
固化该基体模铸材料；
使所述基底构件与所述基片分离；
构制多个穿过所述基片的通孔，多个通孔的一些与多个芯片上的预定接触垫对齐；及
设置一电导体布线图案使之延伸穿过所述基片中的多个预定通孔以制成一集成电路模件。
2.根据权利要求1所述的方法，还包括以下步骤：
将一模型置于芯及挠性材料层周围；将衬底模铸材料加于模型内；然后在衬底模铸材料固化后，使模型移离衬底模铸材料。
3.根据权利要求1所述的方法，其中，所述衬底模铸材料可选自聚醚亚胺树脂，聚四氟乙烯，环氧树脂，苯环丁烯，丙烯酸酯，聚氨基甲酸乙酯，及聚亚胺的群组。
4.根据权利要求3所述的方法，其中，所述衬底模铸材料中含有填料，其可选自微粒，纤维，网，垫片，板等。
5.根据权利要求4所述的方法，其中，该填料系选自玻璃，SiC，AIN，钻石，石墨，Al2O3，金属，及其混合物的群组中。
6.根据权利要求1所述的方法，其中，至少一挠性材料层的第一层包含选自紫外线可固化及热可固化的丙烯酸酯，及紫外线可固化及热可固化的环氧树脂，聚亚胺，及环氧树脂/聚亚胺混合物的群组。
7.根据权利要求6所述的方法，其中，该至少一挠性材料层中包含填料，其可选自微粒，纤维，网，垫片，板等，且其中所述的填料选自玻璃，SiC，AIN，钻石，石墨，Al2O3，金属，及其混合物的群组中。
8.根据权利要求6所述的方法，其中，该至少一挠性材料层的另一层包含选自矽酮，紫外线可固化及热可固化的丙烯酸酯，紫外线可固化及热可固化的环氧树脂，聚亚胺，及环氧树脂/聚亚胺混合物的群组中。
9.根据权利要求1所述的方法，其中，该模型包含一联合模型/层合器，且其中，衬底模铸材料包含一转移模铸材料。
10.根据权利要求1所述的方法，还包括以下步骤：
在施加衬底模铸材料之前，固定一热插塞于至少一个芯片的背面。
11.一种集成电路模件，其特征在于包括：
多个芯片，每一芯片具有一置于其一面上的接触垫，以及所有芯片接触垫大致在同一平面上；
至少一挠性材料层，置于各芯片周围及之间，并自芯片的该面延伸至距芯片背面的距离的一大部分；
包围该挠性材料的固化的衬底模铸材料；
一介质层，置于所述芯片及所述固化的衬底模铸材料的面上，该介质层包含多个通孔，所述多个通孔的至少一些分别与预定的接触垫对齐；及
一电导体布线图案，延伸穿过所述介质层中的多个预定的通孔。
12.根据权利要求11所述的模件，其中，该固化衬底模铸材料包含选自热塑性物，热固性物，聚醚亚胺树脂，聚四氟乙烯，环氧树脂，苯环丁烯，丙烯酸酯，聚氨基甲酸乙酯，及聚亚胺的群组中。
13.根据权利要求12所述的模件，其中，所述衬底模铸材料中含有填料，其选自微粒，纤维，网，垫片，板，及其混合物的群组中。
14.根据权利要求13所述的模件，其中，该填料系选自玻璃，SiC，AIN，钻石，石墨，Al2O3，金属，及其混合物的群组中。
15.根据权利要求11所述的模件，其中，该至少一挠性材料层的第一层可选自紫外线可固化及热可固化丙烯酸盐，紫外线可固化及热可固化环氧树脂，聚酰亚胺以及环氧树脂和聚酰亚胺的混合物。
16.根据权利要求15所述的模件，其中，该至少一层挠性材料包括填充材料，该填充材料可选自微粒、纤维、网、栅、板、以及它们的组合，而且其中的填充材料可选自玻璃、SiC、AIN、钻石、石墨、Al2O3、金属、及其组合。
17.根据权利要求15所述的模件，其中，该至少一层挠性材料的附加层可选自硅，紫外线可固化和热可固化的丙烯酸盐，紫外线可固化和热可固化的环氧树脂和聚烯亚胺混合物。
18.根据权利要求11所述的模件，其中，所述的衬底成型材料包括传输成型材料(transfer molding material)。
19.根据权利要求11所述的模件，还包括一个热插塞，该热插塞在至少通过所述硬化的衬底成型材料的反面之前从至少所述芯片之一的背面延伸。
20.根据权利要求19所述的模件，其中所述的热插塞包括一种导电材料。
21.根据权利要求20所述的模件，其中所述的热插塞包括选自铜、钼、和掺杂有铝的碳化硅机体的材料。
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