CN1168538A

CN1168538A - Semiconductor device and manufacturing methods thereof

Info

Publication number: CN1168538A
Application number: CN97103164A
Authority: CN
Inventors: 山崎舜平; 福永健司
Original assignee: Semiconductor Energy Laboratory Co Ltd
Current assignee: Semiconductor Energy Laboratory Co Ltd
Priority date: 1996-02-09
Filing date: 1997-02-09
Publication date: 1997-12-24
Anticipated expiration: 2017-02-09
Also published as: KR970063720A; CN1504820A; TW322591B; US6194762B1; US20010007368A1; US5864151A; CN1139132C; CN1134068C; KR100286194B1; KR100453285B1; US6753211B2; CN1284241C; CN1227416A

Abstract

In a circuit configuration comprising an n-channel thin-film transistor and a p-channel thin-film transistor integrally produced on a single substrate, a lightly-doped drain (LDD) region is formed selectively in the n-channel thin-film transistor, and damages to semiconductor layers caused when implanting impurity ions are balanced between the n- and p-channel thin-film transistors. This configuration achieves a balance between the n- and p-channel thin-film transistors and thereby provides high characteristics CMOS circuit.

Description

Semiconductor device and manufacture method thereof

The present invention relates to the structure and the manufacture method thereof of semiconductor device, wherein p raceway groove and n channel thin-film transistor are formed on the same substrate.The present invention be more particularly directed to comprise the circuit structure and the manufacture method thereof of complementary metal oxide semiconductors (CMOS) (CMOS) device that places the thin-film transistor on the glass substrate.

Make in the used routine techniques of thin-film transistor a kind of, silicon layer is formed on the glass substrate, and this silicon layer is used to make thin-film transistor.Active matrix liquid crystal display apparatus manufactory majority has adopted this technology at present.

Usually, LCD constitutes in the middle of liquid crystal is clipped in a pair of glass substrate.When voltage is added in formation with the liquid crystal layer of a large amount of pixels of cells arranged in matrix on the time, the light characteristic of liquid crystal changes.As a result, liquid crystal display displays goes out and the corresponding image of institute's making alive.

Active matrix liquid crystal display generally is provided with thin-film transistor and constitutes in the above-mentioned pixel with cells arranged in matrix.The electric charge that these thin-film transistor controls are fed to discrete pixel and export from discrete pixel.

The active matrix liquid crystal display circuit (being called peripheral drive circuit) of ordinary construction is made of integrated circuit (drive IC) basically, this circuit is used for driving by the capable thin-film transistor of taking advantage of hundreds of row form to be arranged at the active matrix district of hundreds of, and described integrated circuit for example utilizes that carrier band welds automatically (TAB), and technology links to each other with the outside of glass substrate.

A problem of this structure is that drive IC is loaded on the outside of glass substrate outward, makes the complex process of this active matrix liquid crystal display.For example, each drive IC becomes very complicated with aiming at of working condition testing equipment.Another problem is when externally drive IC being installed, all can produce a jut on each active matrix liquid crystal display.When active matrix liquid crystal display was assembled into various electronic equipment, this can damage the current potential in its multiple application.

A kind of method that addresses the above problem is directly to form the peripheral drive circuit self with thin-film transistor on glass substrate simultaneously.This method can form the integrated device structure.And, can produce simplified manufacturing technique and strengthen reliability and enlarge the beneficial effect of its range of application.

In active matrix liquid crystal display, need to constitute the peripheral driver circuit with cmos circuit with the peripheral driver circuit that integrally forms like this.Cmos circuit is a kind of basic electronic circuit, and wherein n raceway groove and p channel transistor are linked together the formation complementary structure.

Be presented in an example making the cmos circuit conventional method on the glass substrate with reference to Fig. 4 (A)-4 (D) below.

At first, shown in Fig. 4 (A), growth constitutes the silicon oxide film 402 of basalis on glass substrate 401.Then, deposit can be that crystallizing silicon layer also can be the

active layer

403 and 404 of amorphous silicon layer on silicon oxide film 402, and form to cover

active layer

403 and 404 and as another silicon oxide film 405 of gate insulation layer.In Fig. 4 (A), active layer 403 is the island districts that constitute n channel thin-film transistor active layer, and active layer 404 is the island districts that constitute p channel thin-film transistor active layer.

Then, shown in Fig. 4 (B), form by the grid of forming as the electric conducting material of silicide and so on 406 and 407, and on the whole surface of workpiece shown in Fig. 4 (C), inject phosphonium ion.As a result, numeral 408,410,411 and 413 represented parts become n type district.The dosage that phosphonium ion injects is 1 * 10 ¹⁵/ cm ²-2 * 10 ¹⁵/ cm ², injection condition is that to make surperficial phosphate ion concentration be 1 * 10 ²⁰/ cm ²Or it is higher.

Subsequently, form photoresist mask 414, selectively cover the n channel thin-film transistor, and to inject the boron ion than the high 3-5 of above-mentioned phosphonium ion implantation dosage dosage doubly, shown in Fig. 4 (D).Conduction type or p type that this makes n type district 411 and 413 (Fig. 4 (C)) changeabout.Form source region 415, drain region 416 and the channel region 412 of p channel thin-film transistor with self-aligned manner.Need above-mentioned this heavily doped reason to be, district 415,412 and 416 must form the p-i-p knot.In structure shown in Fig. 4 (D), numeral 408,409 and 410 is represented source region, channel region and the drain region of n channel thin-film transistor respectively.

In the above-mentioned manufacture method, need not to form the photoresist mask at treatment step shown in Fig. 4 (C).Although this helps simplified manufacturing technique, there is following problem in this method.

At first, under high doping foreign ion is injected the variation that photoresist mask 414 causes photoresist material self property, this probability that will cause taking place in the production process to lose efficacy increases.More particularly, after doping, can not remove the photoresist material, or after removing photoresist, still part photoresist material can residually be arranged.

The second, can not ignore the existence of the cut-off current that flows through 416 knots of channel region 412 and drain region.This be because, in order to change conduction type, the channel region 412 adjacent drain regions 416 of the p channel thin-film transistor shown on the right of Fig. 4 (D) are the doped regions of high impurity concentration, have wherein added more than the high foreign ion of the required doping of ordinary production p channel device.

The 3rd, owing to do not wish to have the mobility of the boron ion of injection,, cause at all and can't realize basic electrical characteristics, or usually can not realize these electrical characteristics so there are some boron ions to mix channel region 412 inevitably.

The 4th, the required highly doped amount ion injection of processing step shown in Fig. 4 (D) can make ion implantor or plasma doping machine overload.Cause in these equipment because pollution and its maintenance cause variety of issue.

The 5th problem is that highly doped amount ground injects ion may cause the process time lengthening.

The 6th problem takes place with laser annealing the time.Usually, finish the processing step shown in Fig. 4 (D) after, remove photoresist mask 414, to carry out annealing process in order to activate dopant and implanting impurity ion district to be annealed then, use the laser radiation product.(the method is effective with low heat resistant glass substrate the time.) owing to distinguish the foreign ion amount doping of 415 and 416 usefulness much larger than

district

408 and 410, so the former degree of crystallinity can be badly damaged.Therefore,

district

408 and 410 with distinguish the light absorption between 415 and 416 these two groups of districts and the relation of wavelength and differ widely.In this case, the laser annealing effect between these two groups of districts is also extremely different, and this is disadvantageous.N channel thin-film transistor that Fig. 4 (D) left side and the right are showed and the electrical characteristics between the p channel thin-film transistor have very big-difference.

The method that provides the problems referred to above that produce when a kind of solution is injected formation n channel thin-film transistor and p channel thin-film transistor with highly doped amount ion at the same time of catalogue of the present invention.

Order more specifically of the present invention has, and remedies when constituting cmos circuit with thin-film transistor the adverse effect of electrical characteristics difference between the n channel thin-film transistor and p channel thin-film transistor, thereby high performance cmos circuits is provided.

According to the present invention, a kind of semiconductor device comprises: be integrally formed in n channel thin-film transistor (NTFT) and p channel thin-film transistor (PTFT) on the single substrate, wherein lightly doped drain (LDD) district selectively forms in the n channel thin-film transistor, the source region of p channel thin-film transistor and drain region be only with the doping impurity that produces p conductivity, formed near the source region and the drain region of p channel thin-film transistor by the district of the doping impurity that produces n and p conductivity.

Describe in detail hereinafter with reference to concrete enforcement.For example, in Fig. 3 (B), the n channel thin-film transistor that is positioned at the left side constitutes a cmos circuit with the p channel thin-film transistor that is positioned at the right.In this CM0S circuit structure, 124 of lightly doped drains that are made of the low impurity concentration district place between the channel region and drain region of left side n channel thin-film transistor.The effect of this lightly doped drain is to reduce cut-off current by the field intensity that adjusting is added between channel region and drain region.It also is used for greatly reducing the thin-film transistor carrier mobility by the resistance that increases between its source and leakage.

When making semiconductor with silicon, the exemplary impurity that produces n conductivity is phosphorus (P), and the exemplary impurity that produces p conductivity is a boron.

The p channel thin-film transistor of above-mentioned cmos circuit structure shown in Figure 3 is without any the special buffering area as the lightly doped drain.Yet, in n and/or p channel thin-film transistor, provide the skew grid region by the dielectric film that is formed on each gate side.The effect in skew grid region is identical with lightly doped drain.

Among the embodiment afterwards, shown in Fig. 1 (E), when ion injected, anode oxide film 114 and 115 was made mask, and formed the skew grid region, and as measured on the side of grid, its width almost equates with the thickness of anode oxide film.If the width in these skew grid regions is too little, just they do not have the effect in skew grid region.

Other important feature of semiconductor device of the present invention is as follows.In the technology shown in Fig. 1 (E),

district

128 and 130 is owing to sheltered and be not doped in phosphonium ion technology by

anode oxide film

112 and 113, and these districts are doped with boron ion (referring to Fig. 3 (B)) in after this doping process shown in Fig. 2 (C).Therefore, these districts only contain the impurity that produces p conductivity.The present inventor divides these

districts

128 and 130 in the another name p channel thin-film transistor to be source and drain region.

In addition, in above-mentioned phosphonium ion doping process shown in Fig. 1 (E), with phosphonium ion doping and source and

drain region

128 and 130 adjacent districts 127 and 131.Therefore, these districts contain two kinds of impurity that form n type and p type conduction type.The present inventor clearly distinguishes these

districts

127 and 131 with source region 128 and drain region 130, and they are called contact disc, because they only are used as the connection electrode that electrically contacts with source and drain region.

Therefore, semiconductor device of the present invention is characterised in that the source region of p channel thin-film transistor and drain region are clipped in respectively by between one of district of the doping impurity that produces n conductivity and p type type and the channel region.

If with the doping impurity n that forms single conduction type and/or the channel region of p ditch thin-film transistor, then channel region can be controlled threshold voltage effectively, this voltage is one of important electrical characteristics of thin-film transistor.For example, the channel region that this can be by being added to the boron ion that forms p conductivity the n channel thin-film transistor and the channel region that the phosphonium ion that forms n conductivity is added to the p channel thin-film transistor realized.

In distortion of the present invention, semiconductor device comprises: be integrally formed in n channel thin-film transistor and p channel thin-film transistor on the single substrate, wherein being offset the grid region is formed in the n channel thin-film transistor, its width is greater than the width that is formed at the skew grid region in the p channel thin-film transistor, the source region of p channel thin-film transistor and drain region be only with the doping impurity that produces p conductivity, formed near the source region and the drain region of p channel thin-film transistor by the district of the doping impurity that produces n conductivity and p conductivity.

In another kind of distortion of the present invention, semiconductor device comprises: the active matrix district that contains the n channel thin-film transistor that is provided with by rectangular, peripheral drive circuit with the n channel thin-film transistor that drives the active matrix district, active matrix district and peripheral drive circuit are formed on the single substrate, wherein peripheral drive circuit comprises that one includes the n of interconnection formation complementary structure and the circuit of p channel thin-film transistor, lightly doped drain and/or skew grid region selectively form in each n channel thin-film transistor of peripheral drive circuit, the source region of the p channel thin-film transistor of peripheral drive circuit and drain region are formed by close this source region, the district of the doping impurity that produces n conductivity and p conductivity and drain region only with the doping impurity that produces p conductivity.

In another distortion of the present invention, semiconductor device comprises: the active matrix district that contains the p channel thin-film transistor that is provided with by rectangular, peripheral drive circuit with the p channel thin-film transistor that drives the active matrix district, active matrix district and peripheral drive circuit are formed on the single substrate, wherein peripheral drive circuit comprises the circuit that is made of complementary structure n and the interconnection of p channel thin-film transistor, lightly doped drain and/or skew grid region selectively form in each n channel thin-film transistor of peripheral drive circuit, the source region of each p channel thin-film transistor of peripheral drive circuit and active matrix and drain region are formed by close this source region, the district of the doping impurity that produces n conductivity and p conductivity and drain region only with the doping impurity that produces p conductivity.

According to the present invention, making the method that wherein n channel thin-film transistor and p channel thin-film transistor be integrally formed in the semiconductor device on the single substrate may further comprise the steps: the first step, but on the gate side that constitutes by the anodic oxidation material, selectively form the anode oxide film of loose structure; Second step, make mask with anode oxide film, mix the impurity that produces n conductivity; In the 3rd step, remove anode oxide film; In the 4th step, selectively shelter the zone that forms the p channel thin-film transistor with photoresist; The 5th step, make mask with the photoresist that grid and the 4th step are applied, mix the impurity that produces n conductivity, under the zone at anode oxide film place, form lightly doped drain; In the 6th step, remove the photoresist that applies in the 4th step; The 7th step, selectively shelter the zone that forms the n channel thin-film transistor with photoresist, the 8th step, make mask with grid and added photoresist of the 7th step, mix the impurity that produces p conductivity; Wherein, in the 8th step, only the district with the doping impurity that produces p conductivity is formed under the anode oxide film location, and only forms with the impurity doped region that produces p conductivity with the impurity doped region that forms n type and p type conductivity is close.

In above-mentioned second, five, eight steps, will speed up foreign ion and inject by gate insulation layer, mix the impurity that produces n conductivity or p conductivity.This just can reduce the damage to the active layer of thin-film transistor.

Making the method that n channel thin-film transistor and p channel thin-film transistor be integrally formed in the semiconductor device on the single substrate may further comprise the steps: the first step forms the anode oxide film of loose structure on by the gate side that can anodised material constitutes; Second step, make mask with anode oxide film, mix the impurity that produces n conductivity; In the 3rd step, remove anode oxide film; In the 4th step, selectively shelter the zone that forms the n channel thin-film transistor with photoresist; The 5th step, make mask with grid and photoresist, mix the impurity that produces p conductivity, wherein, in second step, the skew grid region selectively forms in the n channel thin-film transistor, and its width is limited by the anode oxide film of loose structure.

Identical with a structure that specific embodiment adopted shown in Figure 5, the feature of said structure is,

skew grid region

515 and 517 actual size are that the width by the anode oxide film 505 of loose structure limits.If another meticulous and fine and close anode oxide film 500 is very thick, then it also helps to be offset the formation of

grid region

515 and 517.

In making a modified method of crystal silicon film, the technology of making the crystal silicon film of the active layer that is used for forming n and p channel thin-film transistor may further comprise the steps: the first step forms the metallic element that quickens crystallization on amorphous silicon film; In second step,, amorphous silicon film is changed into crystal silicon film by heat treatment; In the 3rd step,, on the crystal silicon film top, form thermal oxide layer by in the atmosphere that contains the halogen family element, heating; The 4th step, remove thermal oxide layer, wherein, at third step, the gettering that passes through to be carried out is operated, and metallic element remaining in the crystal silicon film is absorbed into thermal oxide layer.

Be preferably in 500-700 ℃ the temperature range and carry out above-mentioned second step, in 700-1200 ℃ temperature range, carry out third step.

To describe the present invention originally in detail with following 1-10 embodiment below.

Fig. 1 (A)-1 (E) is the schematic diagram of displaying according to the processing step of the manufacturing CMOS structural membrane transistor circuit of first embodiment;

Fig. 2 (A)-2 (D) is the schematic diagram of displaying according to the processing step of the manufacturing CMOS structural membrane transistor circuit of first embodiment; These steps are the steps after the step shown in Fig. 1 (A)-1 (E);

Fig. 3 (A) and 3 (B) are the schematic diagram of displaying according to the processing step of the manufacturing CMOS structural membrane transistor circuit of first embodiment; These steps are the steps after the step shown in Fig. 2 (A)-2 (D);

Fig. 4 (A)-4 (D) is a schematic diagram of showing the processing step of making conventional cmos structural membrane transistor circuit;

Fig. 5 (A)-5 (D) is the schematic diagram of displaying according to the processing step of the manufacturing CMOS structural membrane transistor circuit of second embodiment;

Fig. 6 (A)-6 (D) is the schematic diagram of displaying according to the processing step of the manufacturing CMOS structural membrane transistor circuit of the 7th embodiment;

Fig. 7 (A)-7 (E) is the schematic diagram of displaying according to the processing step of the semiconductor layer of the formation thin-film transistor of the 9th embodiment.

First embodiment

Fig. 1 (A)-1 (E), Fig. 2 (A)-2 (D) and Fig. 3 (A)-3 (B) have showed the processing step according to the manufacturing thin-film transistor of first embodiment, wherein are used in the thin-film transistor that forms on the glass substrate and constitute the CMOS structure.

At first, shown in Fig. 1 (A), on glass substrate 101, form the silicon oxide film 102 that constitutes bottom.Use suitable technique, for example, the silicon oxide film 102 of about 3000 dusts of sputtering method or plasma chemical vapour deposition (CVD) method grow thick.For example available healthy and free from worry 7059 or healthy and free from worry 1737 glass plates make glass substrate 101.In addition, the quartz substrate of also available high-fire resistance energy is made light-transmissive substrates, though this substrate is more expensive.

After having formed silicon oxide film 102, be used for forming the silicon thin film of the active layer of thin-film transistor after being produced on.In the present embodiment, the thick amorphous silicon film (not shown) of 500 dusts of at first growing is made initiation layer.Make the also available low pressure hot CVD of the both available plasma CVD method of amorphous silicon film method.

After having formed unshowned amorphous silicon film, it is transformed into the crystal silicon film (not shown).This transformation by laser according to the heat treatment amorphous silicon film or by laser according to and heat treated combination realize.In the crystallization treatment process, can be used in the method that forms the metallic element that quickens crystallization on the amorphous silicon film surface.The details of this crystallization method sees open 6-232059 of Japan's special permission and 6-244103 for details.

Make such acquisition but the not shown crystal silicon film composition that goes out forms the semiconductor layer 104 of n channel thin-film transistor and the semiconductor layer 105 of p channel thin-film transistor, shown in Fig. 1 (A).

Then, use plasma CVD method, deposition thickness is at another silicon oxide film 103 of (generally between the 1000-1500 dust) between the 500-2000 dust, and this film is as gate insulation layer.Also available oxygen silicon nitride film, silicon nitride film or other dielectric film constitute gate insulation layer in addition.

At this moment, just obtained structure shown in Fig. 1 (A).For easy, present embodiment is described with example as single group n and p channel thin-film transistor.But the thin-film transistor circuit that generally is used for active matrix liquid crystal display generally comprises above n and the p channel thin-film transistor that is formed on the glass substrate of organizing of hundreds of.

Referring to Fig. 1 (B), will constitute the aluminium film 106 of

grid

11 and 12 after the deposit.The scandium that this aluminium film 106 contains 0.2wt% prevents to form hillock and whisker.Aluminium film 106 can be formed by sputtering method or electron-beam vapor deposition method.Hillock and whisker are respectively the thrusts of spine and needle-like, and they are because the improper growth of aluminium forms.The existence of hillock and whisker can cause between adjacent wire or vertically go up the short circuit between close wiring of separating or get lines crossed.In the distortion of present embodiment, can use can anodised tantalum or other metal replacement aluminium.

After having formed aluminium film 106, with electrolyte anodic alumina films 106 surfaces, wherein aluminium film 106 is made anode.Just formed the thin anode oxide film 107 of meticulous and compact texture with this anode oxidation process.The electrolyte that is used for present embodiment contains 3% tartaric 1,2 ethylene glycol with the ammonia neutralization to be made.The favourable part of this anode oxidation process is, can obtain the anode oxide film of fine chemistry structure, can control institute's making alive and regulate its thickness.In the present embodiment, the thickness setting of anode oxide film 107 is about 100 dusts.Anodic oxygen film 107 is used for improving the adhesiveness of the photoresist mask that will form in the step after this shown in Fig. 1 (B).

After having obtained this structure, form photoresist mask 108 and 109.Then,

mask

108 and 109 makes aluminium film 106 and anode oxide film 107 compositions with photoresist, obtains figure 110 and 111, shown in Fig. 1 (C).

Figure 110 and 111 is retentions of aluminium film 106, promptly in 3% oxalic acid solution they is carried out anodic oxidation at electrolyte, wherein makes anode with figure 110 and 111.In this anode oxidation process, because the reserve part of the anode oxide film 107 of meticulous and compact texture and

photoresist mask

108 and 109 be still on the top of figure 110 and 111, so only selectively anodic oxidation figure 110 and 111 side.After anodic oxidation, form the

anode oxide film

112 and 113 of loose structure.These

anode oxide films

112 and 113 can grow into several approximately micron thickness.

In the present embodiment,

anode oxide film

112 and 113 thickness setting are about 7000 dusts.After this anodised degree of depth has determined the actual size with the low doping concentration district of explanation.By experience as can be known, these porous

anodic oxide films

112 and 113 are preferably long thick to the 6000-8000 dust.Can control their thickness by regulating the anodised time cycle.

Just above-mentioned

grid

11 and 12 have been formed this moment.Obtaining shown in Fig. 1 (D) removing

mask

108 and 109 after the structure.

Use the surface that contains workpiece shown in electrolyte anodic oxidation Fig. 1 (D) that 3% tartaric 1,2 ethylene glycol makes by ammonia neutralization again.In this anode oxidation process, electrolyte penetrates in porous anodic oxide film 112 and 113.As a result, formed the anode oxide film of the meticulous and compact texture of representing by numeral among Fig. 1 (E) 114 and 115.Anode oxide film 114 and 115 thickness setting are the 500-4000 dust, can control their thickness by regulating the alive time cycle.The reserve part of previously mentioned anode oxide film 107 is inhaled into or is merged into anode oxide film 114 and 115.

Then, use the whole surface of workpiece shown in the phosphonium ion doping Fig. 1 (E) that produces n conductivity.This doping process adopts plasma doping method or ion doping method, and dosage is 0.2 * 10 ¹⁵/ cm ²-5 * 10 ¹⁵/ cm ²High dose, but dosage is more preferably 1 * 10 ¹⁵/ cm ²-2 * 10 ¹⁵/ cm ²

Form the district 116 to 119 that high concentration is injected phosphonium ion by doping process shown in Fig. 1 (E).

Remove the

anode oxide film

112 and 113 of loose structure then with the acid that is mixed with aluminium.Directly the active area under

anode oxide film

112 and 113 is intrinsic basically, because any ion is not injected in these districts.

Subsequently, shown in Fig. 2 (A), form photoresist mask 120, cover the device components that constitutes the p channel thin-film transistor, shown in 2 (B), again with 0.1 * 10 ¹⁴/ cm ²-5 * 10 ¹⁴/ cm ²Low dosage inject phosphonium ion, implantation dosage preferably 0.3 * 10 ¹⁴/ cm ²-1 * 10 ¹⁴/ cm ²This means that the phosphonium ion injection shown in Fig. 2 (B) is to carry out with the doping that is lower than the injection of phosphonium ion shown in Fig. 1 (E).As a result,

district

122 and 124 becomes with the lightly doped low doping concentration of phosphonium ion district, becomes with the more heavily doped high-dopant concentration of phosphonium ion district and distinguish 121 and 125.

By doping process shown in Fig. 2 (B), district 121 becomes the source region of n channel thin-film transistor, and

district

122 and 124 becomes the low doping concentration district, and district 125 becomes the drain region of n channel thin-film transistor.And being become by digital 123 districts that represent is the channel region of intrinsic substantially.It should be noted that known zone 124 is generally lightly doped drain (LDD).

Although not shown, exist the phosphonium ion injection region of being interrupted by the anode oxide film between channel region 123 and low

doping concentration district

122 and 124 114.These districts are known as the skew grid region, and their thickness equals the thickness of anode oxide film 114.Because any ion is not injected in the skew grid region, so they are intrinsic basically.Yet owing to there is not gate voltage to add thereon, the skew grid region does not form conducting channel, just is used to reduce added electric field strength, and as suppressing the resistance element that circuit degenerates (not exclusively, but actual can think like this).Yet, it is to be noted, if skew grid region width is too little, just do not have the effect in skew grid region.

Then, shown in Fig. 2 (C), remove photoresist mask 120, form another photoresist mask 126, cover the device components that constitutes the n channel thin-film transistor.Then, with 0.2 * 10 ¹⁵/ cm ²-10 * 10 ¹⁵/ cm ²Dosage inject the boron ion, implantation dosage is preferably 1 * 10 ¹⁵/ cm ²-2 * 10 ¹⁵/ cm ²Boron among Fig. 2 (C) from dosage be higher than the dosage of phosphonium ion among Fig. 1 (E).

In fact the district by

numeral

127 and 131 expressions that forms in the doping process of Fig. 2 (C) is used as the contact disc that electrically contacts with extraction electrode.(after this these districts are called contact disc).Say that more specifically

district

127 and 131 had not only had any different with the source region but also with the drain region significantly, not as the n channel thin-film transistor shown in Fig. 2 (C) left side.

What numeral 128 and numeral 130 were represented is the source region and the drain region of the p channel thin-film transistor shown in the right among Fig. 2 (C).Only the boron ion being injected is the district of Intrinsical substantially, forms these districts 128 and 130.Therefore, do not have other conduction type ion in these districts, easy in other words controlled doping concentration forms good p-i knot.And, degenerate less because ion injects the crystallinity that makes these districts.

Although the skew grid region is formed in self aligned mode by anode oxide film 115, in fact they are also not really important in the p channel thin-film transistor.This be because by experience as can be known the degeneration of p channel thin-film transistor be subjected to the influence of any factor hardly.

As mentioned above, form the source region 128 and the drain region 130 of p channel thin-film transistor in self aligned mode.Do not have impurity to inject in the district of numeral 129 expressions, this district forms channel region.As what illustrated,

district

127 and 131 is respectively from the source region 128 and the contact disc of drain region 130 projected currents.

Although do not inject any impurity in the

channel region

123 and 129 in the present embodiment, said structure can change, and can use doping

impurity channel region

123 and 129, makes them have specific conduction type, is used to control threshold voltage.

After having finished the doping process shown in Fig. 2 (C), remove photoresist mask 126, obtain structure shown in Fig. 2 (D).In order to activate dopant and to make the annealing of foreign ion injection region, the whole surface of workpiece shown in laser radiation Fig. 2 (D).At this processing step, do not have in the source of the source of n channel thin-film transistor and drain region 121,125 and p channel thin-film transistor and the crystallinity between the drain region 128,130 to carry out laser radiation under the situation of big-difference very.The little reason of crystalline difference is what damage is the crystalline texture in the source of p channel thin-film transistor and drain region be not subjected to during the doping process of Fig. 2 (C) a cause.

Therefore, utilize the annealing of laser radiation among Fig. 2 (D) to source and drain region after, the annealing effect between two thin-film transistors can be revised this species diversity.In other words, can eliminate electrical characteristics different of n and p channel thin-film transistor.

After having obtained the structure shown in Fig. 2 (D), shown in Fig. 3 (A), the interlayer dielectric 132 that 4000 dusts of growing are thick.Interlayer dielectric 132 can be silicon oxide film, oxygen silicon nitride membrane, silicon nitride film or multilayer film.No matter use the silicide insulating material of which kind of type, all can form interlayer dielectric 132 by plasma CVD method or hot CVD method.

Then, form contact hole, and form the source electrode 133 and the drain electrode 134 of n channel thin-film transistor.What form simultaneously is the source electrode 135 and the drain electrode 136 of p channel thin-film transistor.At this moment, obtain structure shown in Fig. 3 (B).

Make the workpiece composition, the line that the drain electrode 134 of making n channel thin-film transistor and the drain electrode of p channel thin-film transistor are 136, and the

grid

11 and 12 of two kinds of thin-film transistors is interconnected, finish the CMOS structure.

Referring to Fig. 3 (B), low

doping concentration district

122 and 124 places the n channel thin-film transistor of this CMOS structure.

There is following effect in low doping concentration district 122 and 124:

Reduce cut-off current;

Prevent the thin-film transistor degeneration that hot carrier causes; And

The increasing source and leak between resistance, reduce the carrier mobility of n channel thin-film transistor thus.

The general considerations that runs into when using the CMOS structure shown in Fig. 3 (B) is, the reaction of the different generations of electrical characteristics between n and p channel thin-film transistor.When the crystal silicon film of discussing with the foregoing description, the mobility of charge carrier rate is at 100-150Vs/cm in the n channel thin-film transistor ²Yet available mobility is 30-80Vs/cm in the general p channel thin-film transistor ²And hot carrier can make the n channel thin-film transistor degenerate, although this problem is unimportant in the p channel thin-film transistor.Usually need not hang down cutoff current characteristic especially in the cmos circuit.

Under these conditions, the foregoing description uses n channel thin-film transistor wherein to comprise the CMOS structure of low

doping concentration district

122 and 124, thereby has the following advantages.Specifically, because the CMOS structure of present embodiment can reduce carrier mobility in the n channel thin-film transistor, and can prevent its degeneration, thus realized the overall balance of electrical characteristics between n and p channel thin-film transistor, improved the operating characteristic of cmos circuit thus.

In addition, importantly, semiconductor layer is covered by the silicon oxide film 103 of the gate insulation layer in the injection technology shown in pie graph 1 (E), 2 (B) and 2 (C) in the CMOS structure.Even this moment, implanting impurity ion also can be protected the injury-free and pollution of semiconductor layer surface.This is highly advantageous to and boosts productivity and device reliability.

It should be appreciated that the foregoing description does not all have with highly doped amount implanting impurity ion at any processing step.The effect of doing like this is to prevent photoresist mask change of properties, reduces the defective workmanship odds that changes and cause owing to its character.

Second embodiment

The second embodiment of the present invention provides a kind of thin-film transistor CMOS structure, wherein is offset the grid region and only is formed in the n channel thin-film transistor.Unlike the described skew of first embodiment grid region, the skew grid region of present embodiment is formed by the anode oxide film of loose structure.(in first example, the skew grid region utilizes the anode oxide film of the final reservation that meticulous and compact texture are arranged to form.)

The district is similar with low doping concentration, and representative instance is the LDD district, and there is following effect in the skew grid region:

Reduce cut-off current;

The increasing source and leak between resistance, reduce the carrier mobility of n channel thin-film transistor thus;

Prevent the thin-film transistor degeneration that hot carrier causes.

Fig. 5 (A)-5 (D) has showed the processing step of method of thin-film transistor circuit of the manufacturing CMOS structure of second embodiment.At first, by preparing the workpiece shown in Fig. 5 (A) with processing step identical shown in Fig. 1 (A)-1 (E).

Referring to Fig. 5 (A), numeral 500 expressions have the anode oxide film of meticulous and compact texture, and this film forms around grid.The thickness of this anode oxide film 500 can be set at the 500-4000 dust.In the present embodiment, the thickness of anode oxide film 500 is 600 dusts.

Setting middle digital 505 and 506 porous anodic oxide films of representing of Fig. 5 (A) thick is the 2000-4000 dust.The thickness of anode oxide film 505 has determined the actual size in the skew grid region that will form afterwards.Although the thickness of the anode oxide film that meticulous and compact texture are arranged 500 that is centered on by anode oxide film 505 also influences the actual size of the skew grid region strictness of being discussed among previous first embodiment, but because only about 600 dusts of its thickness are not considered the existence of anode oxide film 500 here.

At this moment, with 0.2 * 10 ¹⁵/ cm ²-5 * 10 ¹⁵/ cm ²High dose, preferably with 1 * 10 ¹⁵/ cm ²-2 * 10 ¹⁵/ cm ²Dosage, by the plasma doping method or from inject phosphonium ion in doping method.With this doping phosphonium ion heavily is injected into district 501 and 504.In other words, district 501 and 504 will form the high-dopant concentration district.

Remove porous anodic oxide film 505 and 506 then, obtain structure shown in Fig. 5 (B), wherein, numeral 507 and 508 is represented not Doping Phosphorus ion district.

Then, form photoresist mask 509, cover the n channel thin-film transistor, and inject the boron ion, shown in Fig. 5 (C).This doping process is with 0.2 * 10 ¹⁵/ cm ²-1 * 10 ¹⁵/ cm ²Implantation dosage, preferably 1 * 10 ¹⁵/ cm ²-2 * 10 ¹⁵/ cm ²Dosage, utilize plasma doping method or ion doping method to carry out.

The result of above-mentioned doping process is, the districts of numeral 510,511,513 and 514 expressions form p type districts, and the districts of numeral 512 expressions form and are the channel region of intrinsic substantially.Described identical with first embodiment, district 511 is as the source region, and district 513 is as the drain region, and

district

510 and 514 is used separately as with source region 511 and drain region 513 and forms the contact disc that electrically contacts.Because source region 511 and drain region 513 are all the intrinsic region before the doped with boron ion, so these districts change into p type district by the boron ion implantation technology of Fig. 5 (C) easily.Therefore, in this doping process, can select the boron ion of minimum dose for use.

The source region 511 of p channel thin-film transistor, channel region 512, drain region 513 and

contact disc

510 and 514 all form with aforesaid self-aligned manner.

Then, remove photoresist mask 509, obtain structure shown in Fig. 5 (D), the numeral 501 the expression be the source region, the numeral 502 the expression be the drain region, the numeral 516 the expression be the channel region of n channel thin-film transistor.And what

numeral

515 and 517 was represented is the district that constitutes above-mentioned skew grid region.

Skew grid region

515 and 517 is not subjected to the effect of electric field from grid, not as source or drain region yet.These district's effects of 515 and 517 are the electric field strength of regulating 516 of the electric field strength, particularly drain region 502 of 516 of source region 501 and channel regions and channel regions respectively.These

skew grid regions

515 and 517 all are to utilize the anode oxide film of loose structure to form with self-aligned manner.

On the other hand, there is not the skew grid region in the p channel thin-film transistor.Although (strictness says that the skew grid region is film formed by the anodic oxidation of the final reservation with meticulous and compact texture, because the skew grid region actual size in the p channel thin-film transistor is too little, ignores it here.)

Described identical with first implementation column, the said structure of second embodiment in fact reduced current-carrying in the n channel thin-film transistor mobility, prevented the degeneration of operating characteristic, thereby can improve the balance between n and p channel thin-film transistor.

The 3rd embodiment

The third embodiment of the present invention is the distortion of first embodiment.Specifically, inject doping process shown in Fig. 2 (B) of phosphonium ion and inject doping process shown in Fig. 2 (C) of boron ion in reverse order.Yet obvious the 3rd embodiment has the advantage identical with first embodiment, this means the concentration that can control phosphonium ion and boron ion respectively.

The 4th embodiment

The 4th embodiment is another distortion of first embodiment.Specifically, with heavy dose of (heavy doping) inject doping process shown in Fig. 1 (E) of phosphonium ion and with low dosage (light dope) inject phosphorus from doping process replace each other.

In following explanation, use Fig. 1 (A)-1 (E), 2 (A)-2 (D) and 3 (A)-3 (B) to the 4th embodiment, wherein with first embodiment in same or analogous parts represent with identical reference number.

After the step identical, obtained structure shown in Fig. 1 (E) with first embodiment, inject then phosphorus from.But this doping process is by carrying out with light dope condition identical shown in Fig. 2 (B) of first embodiment, thereby injects the district 116 and 119 that phosphonium ion forms in this technology the doping content lower than district described in first embodiment arranged.

Form photoresist mask 120,, shown in Fig. 2 (B), inject phosphonium ion again then to cover the device cell that will constitute the p channel thin-film transistor with same way as shown in Fig. 2 (A).Yet, in this case, by carrying out doping process with heavy doping condition identical shown in Fig. 1 (E) of first embodiment.Therefore, the

district

122 and 124 of this technology formation has the high concentration of dopant than the described district of first embodiment.

Subsequently, form n and p channel thin-film transistor by the mode identical with first embodiment.

According to present embodiment, the semiconductor layer 104 and 105 of n and p channel thin-film transistor is subjected to same ion implantation damage, and reason is to carry out heavy doping behind light dope.In other words, press and identical condition shown in Fig. 2 (D), by source region and the drain region annealing of laser radiation to two thin-film transistors, the annealing effect between two thin-film transistors can be eliminated the difference between them.In other words, in the 4th embodiment, can revise the different of electrical characteristics between n and p channel thin-film transistor.

In addition, the n channel thin-film transistor of present embodiment, doping content is different with first embodiment in its LDD district 124.Because present embodiment is to be higher than the doping implanting impurity ion of first embodiment, so the resistance in LDD district 124 reduces.Therefore, the 4th embodiment provide a kind of under the very important situation of current characteristics particularly advantageous CMOS structure.

The 5th embodiment

The 5th embodiment relates to a kind of structure, n channel thin-film transistor threshold voltage wherein in order to obtain meeting the requirements, and its raceway groove is assumed to light p conductivity.

The processing step of this embodiment each step with first embodiment that is shown in Fig. 1 (A)-1 (E), 2 (A)-2 (D) and 3 (A)-3 (B) basically is identical.Compare with first embodiment, the 5th embodiment is characterised in that, when growth is used as the amorphous silicon film of the initiation layer that forms semiconductor layer 104 and 105, has added a small amount of diborane (B ₂H ₆).The actual amount of diborane should be decided according to the required threshold voltage of n channel thin-film transistor.Say that more specifically the consumption of diborane should be decided to be makes the concentration of finally staying the boron element in the channel region about 1 * 10 ¹⁷/ cm ²-5 * 10 ¹⁷/ cm ²Scope in.

The advantage of this embodiment is, can pass through to add a small amount of diborane regulated at will threshold voltage.

The 6th embodiment

Above-mentioned the 5th embodiment has a kind of like this structure, even the channel region of n channel thin-film transistor is light p conductivity, to realize required threshold voltage.Yet, in the structure of the 3rd embodiment, can not freely control the threshold voltage of p channel thin-film transistor.

In order to address this problem, in this embodiment, under state shown in the figure (A), or before forming gate insulation layer, selectively lead with 104 and/or 105 implanting impurity ions to semiconductor prior to state shown in Fig. 1 (A).

For example, before forming gate insulation layer 103, shelter semiconductor layer 105, then with specific doping with boron ion-implanted semiconductor layer 104, make semiconductor layer 104 become light p type district.Subsequently, shelter semiconductor layer 104, phosphonium ion is injected semiconductor layer 105, make semiconductor layer 105 become light n type district with specific doping.

This embodiment provides a kind of structure that can regulate the threshold voltage of n and p channel thin-film transistor respectively.

According to the 5th embodiment, after foreign ion had been injected semiconductor layer 104 and/or 105, preferably heat treatment or laser radiation workpiece carried out annealing in process.Annealing helps the activator impurity ion and repairs the damage that the injection of foreign ion causes.

The 7th embodiment

The seventh embodiment of the present invention relates to a kind of structure, wherein except that the low doping concentration district 122 and 124 (Fig. 2 (B)) of first embodiment, also is formed with the skew grid region.

Usually, the skew good effect in grid region is that they can be used for the degeneration that prevents that hot carrier from causing, reduce cut-off current, particularly by the increase source and the resistance between leaking reduce carrier mobility, it is identical with the effect in low doping concentration district to be offset the grid region in other words, an exemplary is the LDD district.

Fig. 6 (A)-6 (D) shows the processing step of the manufacturing CMOS structural membrane transistor circuit of the 7th embodiment.Except that above-mentioned, the processing step of this embodiment is basic identical with first embodiment that is shown in Fig. 1 (A)-1 (E), 2 (A)-2 (D) and 3 (A)-3 (B).In addition, use with Fig. 1 (A)-1 (E), 2 (A)-2 (D) and 3 (A)-3 (B) in used identical reference number represent the parts identical with first embodiment.

Compare with first embodiment, the 7th embodiment is characterised in that, is formed with the

anode oxide film

601 and 602 of meticulous and compact texture respectively with big thickness shown in Fig. 6 (A), cover gate 11 and 12.Specifically, to grow to the 2000-4000 dust thick for anode oxide film 601 and 602.Although their thickness can also increase again, if too thick then anode oxidation process need be used the voltage that surpasses 300V, this can produce the problem of repeatability and processing safety.

Basically to form these anode oxide films with meticulous and

compact texture

601 and 602, just change institute's making alive according to required film thickness with the same way as described in first embodiment.Usually, thickness is big more, and then institute's making alive is high more.

Subsequently, form photoresist mask 120, cover the device cell that constitutes the p channel thin-film transistor, and inject phosphonium ion, shown in Fig. 6 (B).The injection of phosphonium ion is to be undertaken by the doping identical with first embodiment.The result of this doping process is to have formed source region 121, drain region 125 and channel region 123 in self aligned mode.This doping process has also formed low

doping concentration district

122 and 124, and wherein low doping concentration district 124 is as the LDD district.

In addition, on the dual-side of channel region 123, form a pair of skew grid region 603.These skew grid regions 603 are not as source or drain region.The general size in skew grid region 603 is by the thickness decision that is formed at grid 11 lip-deep fine anode oxide-films 601 in process shown in Fig. 6 (A).

After technical process is finished shown in Fig. 6 (B), remove photoresist mask 120, form another photoresist mask 126, cover the device cell that constitutes the n channel thin-film transistor.Then, shown in Fig. 6 (C), with the doping identical with first embodiment inject boron from.The result of this process is to have formed source region 128, drain region 130 and channel region 129 in self aligned mode.This doping process has also formed contact disc 127 and 131.In addition, shown in Fig. 6 (C), also formed the skew grid region 604 of suitable anode oxide film 602 thickness of a pair of size.

Remove photoresist mask 126 now, obtain structure shown in Fig. 6 (D), and use the laser radiation workpiece, it is annealed.

According to the CMOS structure of present embodiment, the n channel thin-film transistor shown in the left side comprise low

doping concentration district

122 and 124 and the skew grid region 603 combination.The present inventor is with combination called after high resistant leakage (HRD) district of this low doping concentration district with the skew grid region.Although the p channel thin-film transistor shown in the right is without any the low doping concentration district, it includes skew grid region 604.

If the thickness of fine anode oxide-

film

601 and 602 is diminished gradually, therefore the effect meeting that then is offset

grid region

603 and 604 reduces, and finally obtains the structure identical with first embodiment.

Yet, do not have the minimum thickness of determining

skew grid region

603 and 604 or the obvious line of demarcation that forms the minimum thickness that can be offset the required anode oxide film 601 in grid region and 602.Therefore, we can say, though in first embodiment, can ignore the existence that is offset the grid region, even in the structure of first embodiment between source and channel region and leak and channel region between in fact still have the skew grid region.

The 8th embodiment

The eighth embodiment of the present invention relates to a kind of structure, and wherein the peripheral drive circuit in active matrix district and driving active matrix district is integrally formed on the glass substrate.

Usually, a substrate that forms integrated active matrix liquid crystal display constitutes like this, be that at least one thin-film transistor of carrying out switching manipulation is arranged in each of several pixels of arranging with matrix form, the peripheral circuit that drives active square district is arranged in the periphery in active matrix district.All these circuit all are formed on single glass (or quartzy) substrate.

If apply the present invention to the active matrix liquid crystal display of this structure, then can in discrete pixel, form n channel thin-film transistor with low cutoff current characteristic, constitute peripheral circuit with cmos circuit with excellent characteristics.

Say that more specifically the 8th embodiment provides a kind of structure, wherein peripheral circuit has the CMOS structure shown in 1 (A)-1 (E), 2 (A)-2 (D) and 3 (A)-3 (B), and the n channel thin-film transistor shown in these figure is arranged in the active matrix district.

The thin-film transistor that is arranged in the active matrix district preferably should have alap cut-off current, because require them to make charge storage in the specific time cycle in discrete pixel electrode.The n channel thin-film transistor with low

doping concentration district

122 and 124 that is shown in the left side of Fig. 3 (B) is suitable for this purpose most.

On the other hand, cmos circuit commonly used constitutes peripheral drive circuit.Pattern of wants cmos circuit is with the electrical characteristics of the n that improves its performance and p channel thin-film transistor balance as much as possible.First embodiment that is shown in Fig. 1 (A)-1 (E), 2 (A)-2 (D) and 3 (A)-3 (B) is suitable for this purpose most.

The said structure of the 8th embodiment provides an integrated active matrix liquid crystal display, comprises n channel thin-film transistor circuit and peripheral drive circuit in the active matrix district, and two circuit all have the aforesaid characteristic that meets the requirements.

Although present embodiment has used have the low doping concentration district n channel thin-film transistor in (LDD district) according to the above description, also can use such as described in the second embodiment n channel thin-film transistor that is offset the grid region that contains.In addition, also can use n channel thin-film transistor as the described HRD of having of the 7th embodiment district.

In another distortion of the 8th embodiment, be provided with the p channel thin-film transistor in the active matrix district and replace the n channel thin-film transistor.The advantage of this distortion is, because the more anti-degeneration of p channel thin-film transistor, so improved the reliability of image display area.

The 9th embodiment

With identical described in above-mentioned first embodiment, when making the amorphous silicon film crystallization, can use the metallic element that quickens crystallization.(in the following description of the 9th embodiment, making the example of metallic element) with nickel.Yet well-known, behind crystallization processes, still residual in crystal silicon film have a certain amount of nickel.

Surpassed specified limit if contain nickel concentration in the active layer, then can the electrical characteristics of thin-film transistor have been had the opposite effect.(present inventor discovers, this limit is 5 * 10 ¹⁹/ cm ²)

The 9th embodiment provides the method for metal remained element in a kind of crystal silicon film of removing the semiconductor layer that constitutes thin-film transistor.Describe this embodiment in detail below with reference to Fig. 7 (A)-7 (E).

At first, preparation has the substrate 701 of insulating surface.This substrate 701 should have high-fire resistance.This is because treatment temperature once in a while can be above 1000 ℃ when forming crystal silicon film according to present embodiment.

In this embodiment, substrate 701 is quartz substrate, utilizes sputtering method, on the top of substrate 701, forms the thick oxygen silicon nitride membrane of 3000 dusts 702, makes resilient coating.

Then, utilize plasma CVD method or the low pressure hot CVD method thick amorphous silicon film 703 of 500 dusts of growing.For example, can use silane (SiH ₄) or disilane (Si ₂H ₆) do to form the gas of film.The amorphous silicon film 703 that low pressure hot CVD method forms obtains big crystal grain easily, because the possibility that nucleus occurs in the crystallization processes afterwards is less.

After amorphous silicon film 703 forms, in oxygen atmosphere, use the ultraviolet irradiation workpiece, on the surface of amorphous silicon film 703, to form oxide layer (not shown) as thin as a wafer.This oxide layer makes that wetability strengthened (Fig. 7 (A)) when surface of the work was introduced nickel in following solution application technology with explanation.

Then, the nickel salt solution that contains finite concentration nickel is dripped on the workpiece, form the moisture film 704 shown in Fig. 7 (B).If understand residual undesirable impurity after considering the heating that will illustrate afterwards, then the most handy nickel nitrate salting liquid is made nickel salt solution.Although also available nickel acetate solution because its carbon containing is easy to generate the carbide that remains on the silicon fiml after the heat treated afterwards, preferably need not.

In state shown in Fig. 7 (B), with circulator moisture film 704 is spread out, make that contained nickle atom directly contacts with the unshowned oxide layer that is formed on the amorphous silicon film 703 in the moisture film 704.

In inert atmosphere, under 450 ℃ of temperature, workpiece is carried out dehydrogenation handled about 1 hour, then,, heat treated 1-24 hour, make amorphous silicon film 703 crystallization 500-700 ℃ (being typically 550-600 ℃).Obtain the crystal silicon film 705 shown in Fig. 7 (C) in this way.

The previous nickle atom that directly contacts with the oxide layer of unshowned covering amorphous silicon film 703 is diffused in the amorphous silicon film 703 by oxide layer, as the catalyst that quickens crystallization.Specifically, nickel and pasc reaction form silicide, and this silicide is made nucleus then, around it crystallization will take place.By regulating the concentration of nickel salt solution in the above-mentioned solution application technology, just can easily control the nickel concentration that injects in the above-mentioned technology.

After the crystallization of heat treated is finished,, can further improve the degree of crystallinity of crystal silicon film 705 with laser or with the rayed workpiece of identical emittance.Can make the complete crystallization of fraction amorphous silicon still remaining after heat treated with this processing afterwards.

The crystal silicon film 705 that obtains like this with the further heat treatment of higher temperature.Particularly, this heat treated temperature is set at 700-1200 ℃ (being typically 800-1000 ℃), and the processing time is set at 1 and 12 hour (being typically 6 hours).Importantly in the heat treated shown in Fig. 7 (D), use the atmosphere that contains halogen family element (using chlorine (Cl) in the present embodiment).

The 9th embodiment is characterised in that, by in the atmosphere that contains the halogen family element, carrying out heat treated, can remove the nickel that remains in the crystal silicon film 705 former in.More specifically, this heat treated is utilized the gettering effect of halogen, residual nickle atom can be absorbed and be fixed in the thermal oxide layer 706 that is formed on the crystal silicon film 705.

The method for preparing the atmosphere that contains the halogen family element that is used for this embodiment is as follows.At first, in blanket of nitrogen, add the oxygen of 10vol%, add the hydrochloric acid (HCl) of 3vol% (with respect to the volume of oxygen) then.In this atmosphere, general under 950 ℃ temperature, carried out the heat treated shown in Fig. 7 (D) 6 hours.The reason that adds the oxygen of this low volume ratio is, if the ratio of oxygen is too high, the growth of oxide layer 706 is too fast, is difficult to carry out gettering fully.

Although select for use chlorine (Cl) to make halogen in this embodiment, and add with the form of hydrogen chloride gas, electricity can contain the atmosphere of halogen family element with other gas preparation.For example, can choose hydrogen fluoride (HF), hydrogen bromide (HBr), chlorine (Cl ₂), fluorine (F ₂) and bromine (Br ₂) in one or more.Can also use the hydroxide of halogen.

Under any circumstance, in the heating process process shown in Fig. 7 (D), remain in that nickel in the crystal silicon film 705 is former to be absorbed in the thermal oxide layer 706 in meeting.So just from crystal silicon film 705, removed nickel former in, and contained the crystal silicon film 707 of nickle atom hardly.

Exist hardly as dislocation and crystal defects such as piling up fault, can eliminate the silicon atom dangling bonds just between such silicon atom, carry out compound tense.This is because above-mentioned heat treated is to carry out under 950 ℃ of higher temperature.And still remaining dangling bonds can be interrupted by hydrogen contained in the crystal silicon film 707 and halogen atom.In crystal silicon film 707, there are hydrogen and halogen atom in other words.

After having finished the technology shown in Fig. 7 (D), remove thermal oxide layer 706 as gettering point.The purpose of doing like this is to prevent from that nickel is former to advance in the crystal silicon film 707 in anti-expansion.

Make crystal silicon film 707 be patterned into island shape, form the semiconductor layer 708 of n channel thin-film transistor and the semiconductor layer 709 of p channel thin-film transistor, shown in Fig. 7 (E).

By with can finish n and p channel thin-film transistor in the identical following steps described in first embodiment.

Because the

semiconductor layer

708 and 709 of the thin-film transistor that forms according to the above-mentioned technology of the 9th embodiment is containing metal element (be nickel in the present embodiment) hardly, so in fact they can degeneration or performance degradation not take place because of metallic element.In other words, present embodiment can utilize thin-film transistor to constitute the splendid circuit that comprises active matrix district and peripheral drive circuit of reliability.

The tenth embodiment

The tenth embodiment of the present invention relates to the method for the nickle atom in the said structure that a kind of further removal still remains in the 9th embodiment.

In this embodiment, in the oxidizing atmosphere that contains the halogen family element, the crystal silicon film that heat treated utilizes the crystallization process of nickel to obtain forms thermal oxide layer.Because this thermal oxide layer absorbs nickle atom, at last it will contain the nickel higher than crystal silicon film concentration former in.

After having formed thermal oxide layer, remove it.This operation can reduce nickle atom concentration remaining in the crystal silicon film fully.Utilize other metallic element and also can obtain same effect without the crystallization that nickel quickens silicon.

Be described more specifically present embodiment below by example, in the oxygen atmosphere that contains 3vol% hydrochloric acid (HCl), the crystal silicon film that heat treatment utilizes the crystallization process of nickel to obtain forms thermal oxide layer.

Thickness of oxide layer preferably is not less than 200 dusts.So just, can reduce the nickle atom concentration that remains in the crystal silicon film.

Become to assign to form thermal oxide layer owing to during heating treatment spent unsettled silicon,, improve the quality of its crystal structure so can reduce the defective in the crystal silicon film.

When the present invention is used for semiconductor devices, can produce following beneficial effect:

(1) since in office where manage that step is neither need to be with high doping implanted dopant, institute Can avoid the variation of photoresist character.

(2) only in the n channel thin-film transistor, form the low doping concentration district, just can reduce to cut End electric current.

(3) with two types thin film transistor (TFT) when consisting of the CMOS structure, can realize The balance of electrical characteristics between n and the p channel thin-film transistor.

(4) because the district of close channel region basically when implanting impurity ion produces p electric conductivity Intrinsic, so form easily p-i knot and make damage minimum to active area.

(5) owing to being covered with active layer with the insulating barrier such as silicon oxide film and so on, so can keep away Exempt from contingent pollution and surface damage when implanting impurity ion.

Claims

1. a semiconductor device comprises n channel thin-film transistor and p channel thin-film transistor, and each described transistor has the channel region between source and drain region and source and leakage at least, it is characterized in that,

Be to have lightly doped drain in the described n channel thin-film transistor;

Described p channel thin-film transistor comprises that also they contact with the drain region with its source region with the semiconductor region of n type and p type doping impurity; And

Doping impurity is only made with p type impurity in the source of described p channel thin-film transistor and drain region, makes them have a kind of conductivity of setting.

2. a semiconductor device has n channel thin-film transistor and p channel thin-film transistor at least, and described device comprises;

At least the first and second semiconductor islands on the substrate;

Insulating barrier on the described substrate, described insulating barrier covers described semiconductor island;

Described insulating barrier is in each described semiconductor island and covers between the grid on it, wherein,

Described first semiconductor island that constitutes described n channel thin-film transistor comprises:

First channel formation region under described grid,

Near a pair of first deviate region of described first channel region and

Constitute described second semiconductor island of described p channel thin-film transistor, comprising:

Second channel formation region under described grid,

Near a pair of second deviate region of described second channel formation region and

Near second source region and second drain region of described second deviate region, described second source region and second drain region only comprise p type impurity, and directly contact with described second channel formation region and

Near the two parts in described second source region and described the two or two drain region, described two parts contain n and p type impurity respectively,

Wherein said first deviate region is wideer than described second deviate region.

3. according to the semiconductor device of claim 1 or 2, it is characterized in that, constitute between one of described second source region of second semiconductor island of described p channel thin-film transistor and two parts that described second drain region comprises n and p type impurity and described second channel formation region respectively slottingly.

4. according to the semiconductor device of claim 1 or 2, it is characterized in that the described part that comprises n and p type impurity only is used as the connection electrode in described second source region and second drain region.

5. according to the semiconductor device of claim 1 or 2, it is characterized in that described first and second channel formation regions contain the impurity of determining a kind of conduction type.

6. according to the semiconductor device of claim 1 or 2, also comprise: the dielectric film that is formed at the gate side of described n and p channel thin-film transistor; And

The a pair of deviate region that under described dielectric film, forms.

7. according to the semiconductor device of claim 1 or 2, it is characterized in that the hydrogeneous and halogen of described first and second semiconductor islands.

8. semiconductor device, at least comprise the n channel thin-film transistor in the active matrix district and at least one pair of n and the p channel thin-film transistor of the complementary structure in the peripheral drive circuit district, described transistor in described peripheral drive circuit district is used for driving the described transistor in described active matrix district, it is characterized in that, each n channel thin-film transistor in active matrix district and peripheral drive circuit comprises

First semiconductor island on the substrate;

Insulating barrier on the described substrate, described insulating barrier cover described first semiconductor island;

Described insulating barrier is at described semiconductor island and cover between the first grid on it,

First channel formation region under described first grid,

At least one pair of light doping section or the deviate region that selectively form near described first channel formation region, described a pair of light doping section or a pair of deviate region contain n type impurity and

Respectively near described light doping section to or right first source region and first drain region of deviate region, and

The described p channel thin-film transistor of in described peripheral drive circuit each comprises,

Second semiconductor island on substrate,

Insulating barrier on described substrate, described insulating barrier cover described second semiconductor island,

Described insulating barrier is at described second semiconductor island and cover between the second grid on it,

Second channel formation region under described grid,

Near second source region and second drain region of described second channel formation region, described source region and described drain region only contain p type impurity, and directly contact described second channel formation region and

Near the two parts in described source region and described drain region, described two parts contain n and p type impurity respectively.

9. semiconductor device, at least comprise the n channel thin-film transistor in the active matrix district and the n and the p channel thin-film transistor of the complementary structure in the peripheral drive circuit district, transistor in described peripheral drive circuit district is used for driving the described transistor in described active matrix district, wherein, each n channel thin-film transistor in peripheral drive circuit area comprises

At least the first semiconductor island on the substrate;

First grid with described semiconductor island of described insulating barrier;

First channel formation region under described grid,

Near at least one pair of or light doping section or deviate region of described first channel formation region, described light doping section to or deviate region to contain n type impurity and

The described p channel thin-film transistor of in described active matrix district and described peripheral drive circuit each comprises,

Second semiconductor island on substrate,

Second channel formation region under described grid,

Near second source region and second drain region of described second channel region, described source region and described drain region only contain p type impurity, and directly contact described second channel formation region and

10. according to Claim 8 or 9 semiconductor device, it is characterized in that described second source region of described second semiconductor island and described second drain region are inserted in respectively between one of part of described a pair of n of containing and p type impurity and described second channel formation region.

11. according to Claim 8 or 9 semiconductor device, it is characterized in that described first and second channel formation regions contain a kind of impurity of determining a kind of conduction type.

12. according to Claim 8 or 9 semiconductor device, it is characterized in that the hydrogeneous and halogen of described a pair of semiconductor island.

13. a method of integrally making n and p channel thin-film transistor on substrate may further comprise the steps:

On described substrate, form first semiconductor island that constitutes described p channel thin-film transistor and second semiconductor island that constitutes the n channel thin-film transistor at least;

On each semiconductor island, form insulating barrier;

Form grid having on each described semiconductor island of described insulating barrier, but described grid comprises the anodic oxidation material;

The described grid of anodic oxidation forms porous anodic oxide film on the side of described grid, determine the district under described anode oxide film thus in each described island;

Making mask with described grid and described porous anodic oxide film mixes n type impurity for each described semiconductor island;

N type impurity has been mixed described remove semiconductor island after, remove described porous anodic oxide film;

Only shelter described first semiconductor island with first photoresist;

Utilize described first photoresist that n type impurity is mixed described second semiconductor island, thereby under described anode oxide film, form light doping section;

Remove described first photoresist;

Only shelter described second semiconductor island with second photoresist;

Make mask with grid, p type impurity is mixed described first semiconductor island, and cover described second semiconductor island with described second photoresist;

Only mix as the p type impurity of impurity in the district of described first semiconductor island under the wherein said anode oxide film, this district has a kind of conduction type,

Two parts of described first semiconductor island in the described district under the wherein close described anode oxide film are mixed with n and p type impurity.

14. a method of integrally making n and p channel thin-film transistor on substrate may further comprise the steps:

On each described semiconductor island, form insulating barrier;

Selectively form grid having on each described semiconductor island of described insulating barrier, but described grid comprises the anodic oxidation material;

Each is described except that behind the semiconductor island in that n type impurity has been mixed, and removes described porous anodic oxide film;

Only shelter described second semiconductor island with photoresist;

Make mask with described grid p type impurity is mixed described first semiconductor island, and cover described second semiconductor island with described photoresist;

Wherein described mix n type impurity step during, in described second semiconductor island, selectively form a pair of deviate region, the width of described deviate region is determined by described porous anodic oxide film.

15. the method according to claim 13 or 14 is characterized in that, will speed up foreign ion and injects by described insulating barrier and mix described n and p type impurity.

16. method according to claim 13 or 14, it is characterized in that, utilize porous anodic oxide film, form in the described district under the described anode oxide film of described second semiconductor island and mix drain region or skew grid region at least or gently, the described district under the described anode oxide film of described first semiconductor island forms source region and drain region.

17. the method according to claim 13 or 14 is characterized in that, is formed the crystal silicon film of the active layer that is used as described n and p thin-film transistor by following steps:

On described substrate, form amorphous silicon film;

On described amorphous silicon film, form the metallic element that quickens crystallization;

Utilize heat treatment to make described amorphous silicon film crystallize into crystal silicon film;

In the atmosphere that contains the halogen family element, heat-treat, on the top of described crystal silicon film, form thermal oxide layer; And

Remove described thermal oxide layer;

The described metallic element that wherein remains in the described crystal silicon film is absorbed in the described thermal oxide layer.

18. the method according to claim 17 is characterized in that, 500-700 ℃ of described heat treated that is used for crystallization, and the described heat treatment in 700-1200 ℃ of atmosphere of carrying out containing the halogen family element.

19. the method according to claim 17 is characterized in that, the described atmosphere that contains the halogen family element prepares by halogen is added in the oxidizing atmosphere.