CN1183169A - 用于微电子衬底的焊料突点结构 - Google Patents

用于微电子衬底的焊料突点结构 Download PDF

Info

Publication number
CN1183169A
CN1183169A CN96193624A CN96193624A CN1183169A CN 1183169 A CN1183169 A CN 1183169A CN 96193624 A CN96193624 A CN 96193624A CN 96193624 A CN96193624 A CN 96193624A CN 1183169 A CN1183169 A CN 1183169A
Authority
CN
China
Prior art keywords
solder
metal layer
prominent
layer
solder structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN96193624A
Other languages
English (en)
Other versions
CN1179412C (zh
Inventor
格林·A·莱恩
约瑟福·达尼尔·米斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unitive Internat Ltd.
Original Assignee
NORTH CAROLINA MICROELECTRONIC CENTER
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NORTH CAROLINA MICROELECTRONIC CENTER filed Critical NORTH CAROLINA MICROELECTRONIC CENTER
Publication of CN1183169A publication Critical patent/CN1183169A/zh
Application granted granted Critical
Publication of CN1179412C publication Critical patent/CN1179412C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49149—Assembling terminal to base by metal fusion bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Abstract

一种在微电子衬底(15)上形成集成的再分布路径的导体(17)和焊料突点(21)的方法,包括在衬底上形成下突点金属化层(16)的步骤和在下突点金属化层上形成焊料结构的步骤,其中焊料结构包括伸长部分(22B)和展宽部分(22A)。未被焊料结构覆盖的所述下突点金属化层的部分可以利用焊料结构做掩模选择性地除去。此外,使焊料从焊料结构的伸长部分流到展宽部分,从而形成突起的焊料突点。该步骤最好将焊料结构加热到它的液化温度以上,使表面张力引起的内部压力影响流动。还公开了不同的焊料结构。

Description

用于微电子衬底的焊料突点结构
本发明涉及微电子器件领域，特别涉及微电子器件的焊料突点。
高性能的微电子器件通常使用焊料球或焊料突点与其它微电子器件进行电互连。例如，超大规模集成电路(VLSI)芯片可以使用焊料球或焊料突点电连接到电路板或其它下一级封装衬底上。这种连接技术也称做“控制熔塌芯片连接-C4”或“倒装芯片”技术，在这里称作焊料突点。
该技术的显著进步公开在Yung转让给本发明的受让人的U.S.专利5,162,257“焊料突点的制造方法”中。在该专利中，下突点金属化(Underbump metallurgy)层形成在包括接触焊盘的微电子衬底上，焊料突点形成在与接触焊盘相对的下突点金属化层上。位于焊料突点与接触焊盘之间的下突点金属化层转变为金属间化合物，对于刻蚀焊料突点之间的下突点金属化层刻蚀剂来说，该金属间化合物为抗蚀剂。因此，保护了焊料突点的基底。
在许多情况下，需要在衬底上远离接触焊盘处设置焊料突点，并形成接触焊盘和焊料突点之间的电连接。例如，微电子衬底可以最初设计为接触焊盘排列在衬底的外边缘用于引线键合。此后，也许将微电子衬底用在需要焊料突点放置在衬底内部的应用中。为了能将焊料突点放置在衬底内距每个接触焊盘一段距离处，需要有互连或再分布路径的导体(redistribution routing conductor)。
Moore等人在U.S.专利5,327,013“集成电路管芯的焊料突点”中公开了一种在集成电路管芯上形成再分布路径的导体和焊料突点的方法。该方法包括形成导电的焊料可湿润的合成材料端。该端包括覆盖远离金属接触的钝化层的键合焊盘和由焊盘延伸到金属接触的滑槽(runner)。焊料体回流焊到键合焊盘上形成键合到焊盘的突点并通过滑槽电连接。
然而，在该方法中，将焊料合金的微小球体按压到键合焊盘上形成焊料突点。此外，在回流焊期间，限制了焊料沿滑槽的散布。在图示的实施例中，由阻焊的聚合材料形成的焊料中止层(solder stop)应用到滑槽上将焊料限制在键合焊盘上。
尽管已有以上提到的参考资料，但本领域仍然需要一种能有效地制造再分布路径的导体和焊料突点并能降低成本的方法。
因此本发明的目的在于提供一种形成再分布路径的导体的改进的方法。
本发明的另一个目的在于提供一种能和相关的焊料突点成一体地形成再分布路径的导体的方法。
本发明的这些和其它目的通过在微电子衬底上形成下突点金属化层和在下突点金属化层上形成包括伸长部分和展宽部分的焊料结构获得。可以用电镀法在掩模限定的下突点金属化层的所需部分处形成焊料结构。然后使用焊料结构做掩模将未被焊料覆盖的下突点金属化层的其它部分选择性地除去。因此，使用一个单独的掩模步骤就可以限定焊料结构和下突点金属化层。
然后使焊料流动。意想不到的是，焊料内的表面张力使流动的焊料在下突点金属化层伸长部分上形成薄焊料层，并在下突点金属化层的展宽部分上形成突起的焊料突点。因此，使用一个焊料淀积步骤后接焊料流动步骤(一般采用加热)可以形成包括薄的伸长部分和突起的展宽部分的焊料结构。
在一个实施例中，本发明包括在含有微电子衬底表面上的电接触焊盘的微电子衬底上形成再分布路径的导体的方法。该方法包括在表面上形成下突点金属化层的步骤，和与微电子衬底相对的下突点金属化层上形成焊料结构的步骤。下突点金属化层电接触接触焊盘，焊料结构包括伸长部分和展宽部分。
形成焊料结构的步骤最好包括形成含有延伸到电接触焊盘上的伸长部分的焊料结构的步骤。该焊料结构限定出下突点金属化层的第一(暴露的)和第二(未暴露的)部分，形成焊料结构的步骤后接选择性也除去未被焊料结构覆盖的下突点金属化层的第一(暴露的)部分的步骤。因此，形成焊料结构后，焊料结构可以做掩模层选择性地除去未被焊料覆盖的下突点金属化层的第一部分，因而省却了对焊料结构和下突点金属化层进行构图的单独的光刻步骤。
伸长的焊料部分最好有位于与接触焊盘相对的下突点金属化层上的一端和连接展宽部分的第二端。因此，焊料结构限定了下突点金属化层的各伸长部分和展宽部分，并且下突点金属化层的伸长部分的一端最好与接触焊盘电连接。应该明白，其它伸长的焊料部分从与接触焊盘相对的点的其它方向延伸到下突点金属化层上，而且伸长部分轻微地延伸越过与接触焊盘相对的点。
该方法还包括使焊料结构中的焊料从伸长部分流到展宽部分的步骤。因此，突起的焊料突点可以形成在焊料结构的展宽部分内，薄焊料层可以形成在焊料结构的伸长部分内。要完成该步骤最好将焊料加热到它的液化温度以上并将它限制在下突点金属化层的伸长部分和展宽部分内，以致表面张力引起的内部压力使焊料流到展宽部分上。可以在未被焊料结构覆盖的下突点金属化层第一(暴露的)部分上形成焊料阻挡层限制流动的焊料。
使焊料结构流动的步骤可以在下突点金属化层和焊料结构之间形成金属间化合物区。该金属间化合物区包括金属化层的成分和焊料结构的成分。对除去下突点金属化层的第一(暴露的)部分使用的刻蚀剂来说，该金属间化合物区为抗蚀剂，因而减少了焊料结构的钻蚀。
形成下突点金属化层的步骤最好包括：在微电子衬底上形成铬层，在铬层上形成铬和铜的相控层，以及在与铬层相对的相控层上形成铜层。该结构提供了将粘接到微电子衬底和接触焊盘以及焊料结构上的导电基底。形成下突点金属化层的步骤还包括在微电子衬底和铬层上形成钛层的步骤。
形成焊料结构的步骤包括：在下突点金属化层上形成构图的掩模层，在下突点金属化层的第二部分上形成焊料结构，并选择性地除去构图的掩模层。构图的掩模层最好覆盖下突点金属化层的第一部分，并限定焊料结构形成于其上的下突点金属化层的第二部分。
此外，形成焊料结构的步骤包括在下突点金属化层的第二部分上电镀焊料的步骤。通过形成延伸到微电子衬底上的下突点金属化层，下突点金属化层可以用做多个焊料结构的电镀电极。因此，多个焊料结构可以用一个电镀步骤形成，并且每个焊料结构具有统一的高度。
本发明还包括微电子衬底上的焊料突点结构，该微电子衬底包含具有暴露部分的电接触焊盘。该焊料突点结构包括微电子衬底上的下突点金属化结构，和与微电子衬底相对的下突点金属化结构的焊料结构。金属化结构(metallurgy structure)包括具有电接触接触焊盘的暴露部分的第一端的伸长部分，和连接伸长部分的第二端的展宽部分。焊料结构包括金属化结构上的伸长部分结构和金属化结构的展宽部分上的展宽部分。因此，焊料结构的展宽部分可以形成在微电子衬底而不是接触焊盘的部分上，并仍然与焊盘电连接。
焊料结构的伸长部分具有第一预定厚度，并且焊料结构的展宽部分具有第二预定厚度。第一预定厚度最好比第二预定厚度薄。因此，焊料结构的展宽部分最好形成突起的焊料突点，该焊料突点可以将微电子衬底电和机械地连接到印制电路板或下一级封装衬底上。作为选择，焊料结构的伸长部分和焊料结构的展宽部分可以有相同的预定厚度。
焊料突点结构还包括下突点金属化结构和焊料结构之间的金属间化合物区，该金属间化合物区包括下突点金属化结构的成分和焊料结构的成分。
作为选择，焊料突点结构可以包括微电子衬底上的下突点金属化层，并电接触接触焊盘的暴露部分。该焊料突点结构还包括与微电子衬底相对的下突点金属化层上的焊料结构。焊料结构包括具有与电接触焊盘暴露部分相对的第一端的伸长部分和连接伸长部分的第二端的展宽部分。该下突点金属化层可以和焊料结构延伸到微电子衬底上，该焊料结构限定了下突点金属化层的第一(暴露的)和第二(未暴露的)部分。这种连续的下突点金属化层可以用做电镀的电极。
此外，结构可以包括下突点金属化层的第一(暴露的)部分上的焊料阻挡层。在以上讨论过的焊料流动步骤期间，该焊料阻挡层用于容纳焊料。
因此，下突点金属化层可以形成在微电子衬底上，并用做电镀包括伸长部分和展宽部分的焊料结构的电极。然后将焊料结构用做掩模选择性地除去未被焊料结构覆盖的下突点金属化层的部分。因而使用一个光刻步骤就可以对焊料结构和下突点金属化层进行构图。此外，焊料可以从焊料结构的伸长部分流到展宽部分，因而形成突起的焊料突点。这最好由加热焊料到它的液化温度以上使表面张力引起的内部压力影响流动获得。因此，制造出稳定的多级焊料结构。
图1-5为根据本发明制造再分布路径的导体期间不同阶段微电子衬底剖面的侧视图。
图6-10为分别对应于图1-5制造再分布路径的导体期间不同阶段微电子衬底的顶视图。
现在结合附图详细地介绍本发明，在图中显示了本发明的优选实施例。然而本发明也体现为许多不同的形式，不应限于这里介绍的实施例；相反，在这里提供实施例是为了使本发明公开充分和完整，并使本领域的普通技术人员领会本发明的范围。在图中，为清楚起见放大了层的厚度和区域。相似的元件采用了相同的数字。
如侧视图图5和对应的顶视图图10所示，本发明涉及包括再分布路径的导体和突起的焊料突点的微电子结构11。微电子结构包括衬底15上的接触焊盘14和钝化层12。再分布路径的导体17和焊料突点21每个分别包括下突点金属化层16A-B和焊料层22A-B的部分。
再分布路径的导体17包括每个伸长的下突点金属化部分16B上的相对伸长的焊料部分22B。焊料突点21包括每个展宽的下突点金属化部分16A上的展宽的焊料部分22A。如图5所示，当展宽焊料部分22A突起时，伸长的焊料部分22B相对薄些。
因此，焊料突点21可以设置在衬底上距接触焊盘14一段距离的点处，再分布路径的导体17提供它们之间的电连接。这种设置的优点在于具有接触焊盘14在一个预定位置处的布局的衬底在第二位置处有一个相关的焊料突点。例如当衬底具有用于引线键合排列的接触焊盘布局时，需要将衬底用于倒装芯片应用中，这种设置就特别有用。如下面结合图1-10介绍的，焊料突点和再分布路径的导体可以同时制造。
如图所示，再分布路径的导体17可以是直的，也可以包括弯曲部分。此外，焊料突点21可以为图示的圆形或如矩形的其它形状。
焊料突点21和再分布路径的导体17最好同时形成。图1-5为不同阶段制造的微电子结构的剖面侧视图，而图6-10为对应于相同的微电子结构的顶视图。如图1和6所示，微电子结构11最初包括衬底15上的钝化层12和暴露的接触焊盘14。
衬底15可以包括一层半导体材料，例如硅、砷化镓、碳化硅、金刚石，或其它本领域的普通技术人员公知的衬底材料。同样这层半导体材料包括一个或多个电子器件，例如晶体管、电阻、电容，和/或电感。接触焊盘14包括铝、铜、钛、包括以上提到的金属的结合如AlCu和AlTi3的金属间化合物、或本领域的普通技术人员公知的其它材料。该接触焊盘最好与衬底内的电子器件相连。
钝化层12可以包括聚酰亚胺层、二氧化硅层、氮化硅层、或本领域的普通技术人员公知的其它钝化材料。如图所示，钝化层12可以覆盖与衬底15相对的接触焊盘14的上部边缘部分，露出每个接触焊盘的中间部分。本领域的普通技术人员应该明白，术语衬底15也可以定义成包括图1和6的钝化层12和接触焊盘14。
如图2和7所示，下突点金属化层16形成在钝化层上为焊料突点和接触焊盘14之间提供连接，并作为电镀电极。在随后的工艺步骤中，下突点金属化层16还保护接触焊盘14和钝化层12，并提供焊料附着的表面。下突点金属化层最好包括钝化层12和接触焊盘14上的铬层；铬层上的铬/铜的相控层；和相控层上的铜层。这种结构贴附并保护钝化层12和接触焊盘14，并为以后电镀的焊料凝供基底。
在申请日为1995年3月20并转让给本发明的受让人的U.S.专利中请“焊料突点的制造方法和含有钛阻挡层的结构”中公开的下突点金属化层还包括衬底和铬层之间的钛阻挡层。该钛阻挡层保护钝化层不受除去下突点金属化层的其它部分的刻蚀剂的损害，并防止在钝化层上形成导致焊料突点和再分布路径的导体之间短路的残留物。可以很容易地将钛阻挡层从钝化层上除去不会留下大量的残留物。
例如在Dishon的U.S.专利4,950,623“形成焊料突点的方法”、Yung的U.S.专利5,162,257“焊料突点制造方法”，和Mis等人的申请日为1995年3月20的U.S.专利申请“焊料突点的制造方法和含有钛阻挡层的结构”中公开了不同的下突点金属化层。这些参考文献都转让给本发明的受让人，在这里引入仅供参考。
焊料阻挡层18形成在下突点金属化层16上。该焊料阻挡层18最好包括下突点金属化层16上如钛或铬的焊料不可湿润材料层。如果在除去下突点金属化层16未被焊料覆盖的第一(暴露的)部分之前进行回流焊步骤，那么焊料阻挡层18将用于容纳焊料，这将在下面讨论。然后在焊料阻挡层18上形成掩模层20。掩模层包括光刻胶掩模或本领域的普通技术人员公知的其它掩模。
对掩模层20进行构图覆盖下突点金属化层的第一部分上的焊料阻挡层，并露出焊料突点和再分布路径的导体将形成其上的下突点金属化层16的第二部分上的焊料阻挡层的区域。然后除去焊料阻挡层未覆盖的部分因而露出下突点金属化层16的第二部分，如图3和8所示。特别是，未被焊料阻挡层和构图的掩模层覆盖的下突点金属化层16的第二部分包括展宽部分16A和伸长部分16B。
如图4和9所示，焊料层22最好电镀在下突点金属化层16的第二部分上。通过对连续的下突点金属化层16施加偏置电压并将微电子结构浸在含铅和锡的溶液中电镀焊料，这些本领域的普通技术人员都知道。这个电镀工艺可使焊料层同时形成在下突点金属化层16的多个第二部分上。焊料不会镀在掩模层20上。作为选择，可以通过作为焊膏的丝网印刷、蒸发法、电子束淀积、无电淀积或本领域的普通技术人员公知的其它方法施加焊料。此外，为了说明整个说明书使用了铅-锡焊料，但本领域的普通技术人员应该明白例如金焊料、铅-铟焊料，或锡焊料等其它焊料都可以使用。
焊料层22包括伸长部分22B和展宽部分22A。除去掩模层20后，可以加热微电子结构11使焊料从伸长部分22B流到展宽部分22A，因而在展宽部分22A上形成突起的焊料突点。如图5和10所示，焊料阻挡层18可防止焊料散布到下突点金属化层16的展宽部分16A和伸长部分16B以外。
当焊料加热到它的液化温度(含90％的铅和10％的锡的焊料大约为299℃)以上时，焊料流动，该工艺通常称做回流焊。在回流焊期间，焊料的表面张力在用于焊料突点的相对较宽的几何形状上的展宽部分22A内产生相对较低的内部压力，在用于再分布路径的导体的相对较窄的几何形状上的伸长部分22B内产生相对较高的内部压力。
为了平衡内部的压力差异，焊料从伸长焊料部分22B流向展宽焊料部分22A。因此，在展宽部分22A上形成突起的焊料突点，在再分布路径的导体上的伸长部分22B上形成相对较薄的层。当焊料冷却到它的液化温度以下时，焊料固化并维持原有形状，包括突起的焊料突点和再分布路径的导体上的薄层。
印制电路板制造领域中都知道通过丝网印刷将焊料均匀施加到PCB的焊区上，并且通过放大焊区部分，局部增加焊料水平。参见1995年1月“Electronic Packaging&Production”pp.40，42 Swanson的“PCBAssembly：Assembly Technology in China”。然而，对于这些知识，申请人首先意识到焊料可以均匀电镀到微电子衬底上，然后加热在衬底上产生突起的焊料突点和再分布路径的导体。
此外，Moore等人的U.S.专利5,327,013指出焊料合金的微小球体可以按压到焊盘上，并且由阻焊的聚合材料形成的中止层施加到滑槽上将焊料限制在键合焊盘上。该专利指出在回流焊期间，焊料沿滑槽的散布可由相对于焊盘缩小滑槽区的宽度来限制，但没有提示使焊料由滑槽流到焊盘因而形成多级焊料结构的滑槽区和键合焊盘的相关尺寸。此外，这些参考资料也没有提示具有伸长部分和展宽部分的焊料结构可用于掩模下突点金属化层，以便仅用一个掩模步骤就可以形成再分布路径的导体和焊料突点。
本发明的方法利用回流的(液体)焊料的表面张力引起的内部压力差在伸长部分22B上形成相对较薄的焊料层并且在展宽部分22A上形成突起的焊料突点。根据下面的公式可以决定一个焊料液滴的内部压力P：
               P＝2T/r其中T是液体焊料的表面张力，r是液滴的半径。
当液体焊料在如下突点金属化层的平坦可湿润表面上时，公式变为：
              P＝2T/r′在该公式中，r′是液体焊料的表观半径，表观半径为焊料暴露的表面定义的弯道半径(曲率半径)。表观半径取决于例如与焊料接触的下突点金属化层的第二部分的底层焊料可湿润层的宽度。因此，回流的焊料结构的内部压力反比于与焊料接触的下突点金属化层的第二部分的宽度。换句话说，具有较宽的下突点金属化部分上的焊料部分将具有较低的内部压力，而伸长的(较窄)下突点金属化部分的焊料部分将有较高的内部压力。当伸长部分22B和展宽部分22A的表观半径基本相等时，内部压力相等。
因此，当图示在图4和9中的均匀焊料层22加热到液化温度以上时，焊料由伸长部分22B流到展宽部分22A直到每部分有基本相同的表观半径，因此形成突起的焊料突点。如果在除去下突点金属化层16未被焊料结构覆盖的第一部分之前进行回流焊步骤，可以在焊料部分22A-B和邻近焊料的下突点金属化层16A-B间形成金属间化合物，其中金属间化合物为一般用于除去下突点金属化层的刻蚀剂的抗蚀剂。因此，在下一步骤除去下突点金属化层16未被焊料覆盖的第一部分期间，金属间化合物可以减少钻蚀，如转让给本申请的受让人的Yung的U.S.专利5,162,257“焊料突点制造方法”中讨论的。
最好，下突点金属化层16包括邻近焊料结构的铜层，并且焊料为铅-锡焊料。因此，使焊料流动的步骤将使焊料与铜发生反应形成邻近焊料结构的金属间化合物区，该金属间化合物区包括Cu3Sn。该金属间化合物区不易与一般用于除去下突点金属化层的刻蚀剂发生反应，因此减少了焊料结构的钻蚀。
然后最好使用焊料层22作为掩模选择性地刻蚀焊料阻挡层18和未被焊料覆盖的下突点金属化层16的第一部分。使用一种相对于焊料部分22A-B优先刻蚀下突点金属化层16的化学刻蚀剂。因此，不必需要附加的掩模步骤对下突点金属化层16构图。换句话说，形成掩模层20仅需对焊料阻挡层18进行构图的掩模步骤(图3和8)，在电镀步骤期间选择性地露出下突点金属化层16的第二部分(图3和8)，并在电镀步骤之后除去下突点金属化层16的第一部分(图5和10)。
另外，未被焊料部分22A和22B覆盖的下突点金属化层16的第一部分可以在使焊料流动之前选择性地除去。在这种情况下，伸长的22B和展宽的22A焊料部分分别仅支撑在下突点金属化层的伸长的16B和展宽的16A上，液体焊料对下突点金属化层可湿润，但对钝化层12不可湿润。因此，在焊料流动步骤期间，钝化层可含有焊料，可以省却焊料阻挡层18。
在另一种选择中，焊料阻挡层包括下突点金属化层16上的焊料不可湿润层和相对于下突点金属化层的焊料不可湿润层上如铜的焊料可湿润层，如转让给本申请的受让人的Mis等人的申请日为1995年3月20的U.S.专利申请“焊料突点的制造方法和含有钛阻挡层的结构”中所公开的。焊料可湿润层使焊料镀在焊料阻挡层的部分上以及未被焊料阻挡层或掩模覆盖的下突点金属化层的第二部分上。
因此，掩模层20可以将焊料阻挡层的部分以及下突点金属化层16的部分暴露出，因而可以电镀更大量的焊料。然后除去掩模层20和焊料可湿润层下面的部分。当加热焊料使其流动时，焊料下焊料可湿润层的剩下部分溶解到露出焊料不可湿润层的焊料中。因此，焊料退到可湿润的下突点金属化层的第二部分。
作为例子，下突点金属化层16的第一部分由焊料阻挡层18和掩模20覆盖。下突点金属化层16的第二部分未被覆盖，并且具有宽150μm长500μm的伸长部分16B，和直径(或宽度)为500μm的展宽部分16A，如图3和8所示。然后将均匀的35μm高的焊料层22电镀在包括伸长部分16A和展宽部分16B的下突点金属化层16的第二部分，如图4所示。该焊料含90％的铅和10％的锡。除去掩模层20之后，将焊料加热到它的液化温度(约299℃)以上，使焊料流动。
通过焊料不湿润的焊料阻挡层18将液化焊料限制在焊料可湿润的下突点金属化层的第二部分16A-B。由于焊料结构宽度可以改变，当高度统一时，焊料结构的内部压力并不一致。特别是，在原来的焊料高度下，伸长的焊料部分22B的内部压力较高(约1.283×104Pa或1.86psi)，展宽焊料部分22A的内部压力较低(3.848×103Pa或.558psi)。
因此，焊料由伸长的焊料部分22B流到展宽焊料部分22A，直到内部压力相等，因而在展宽焊料部分22A处形成突起的焊料突点，如图5和10所示。在图5和10中，焊料阻挡层18和未被焊料结构覆盖的下突点金属化层16的第一部分也被除去。
在这个实施例中，在内部压力约为3.4×103Pa(.493psi)时达到平衡。平衡时，伸长的焊料部分22B约10μm高，展宽焊料部分22A约130μm高，两个部分的曲率半径都约为281μm。因此，可以用一个掩模步骤形成两级焊料结构。当冷却时，该结构固化，并保持原来的形式。此外，当除去被焊料结构覆盖的下突点金属化层16的第一部分时，焊料高度为10μm伸长的焊料部分22B足以掩模各伸长的下突点金属化层部分16B。焊料结构的展宽部分的宽度(或如果展宽部分为圆形时为直径)至少两倍于焊料结构伸长部分的宽度，以便确保以上介绍的方法形成的焊料突点相对于伸长的焊料部分充分地突起，形成与印制电路板的充分的连接。
在附图和说明书中，公开了本发明典型的优选实施例，虽然使用了专门的术语，但仅为描述性的，并不是为了限定，本发明的范围由以下的权利要求限定。

Claims (20)

1.一种焊料突点结构，用于包括具有露出部分的电接触焊盘的微电子衬底，所述结构包括：
所述微电子衬底上的下突点金属化层，用于电接触所述电接触焊盘的露出部分；以及
与所述微电子衬底相对的所述下突点金属化层上的焊料结构，所述焊料结构包括伸长部分和展宽部分。
2.根据权利要求1的焊料突点结构，其中所述下突点金属化层在所述微电子衬底上延伸，所述焊料结构定义了所述下突点金属化层的第一和第二部分，所述下突点金属化层的第二部分包括伸长部分和展宽部分，它们分别对应于所述焊料结构的所述伸长部分和展宽部分。
3.根据权利要求2的焊料突点结构，还包括所述下突点金属化层的所述第一部分上的焊料阻挡层。
4.根据权利要求1的焊料突点结构，其中所述焊料结构的所述伸长部分具有第一预定厚度，并且所述焊料结构的所述展宽部分具有第二预定厚度。
5.根据权利要求4的焊料突点结构，其中所述第一预定厚度薄于所述第二预定厚度。
6.根据权利要求1的焊料突点结构，其中所述焊料结构的所述伸长部分具有邻近所述电接触焊盘的所述露出部分的第一端和连接所述焊料结构的所述展宽部分的第二端。
7.根据权利要求1的焊料突点结构，其中所述焊料结构的所述伸长部分和所述展宽部分具有共同的预定厚度。
8.根据权利要求1的焊料突点结构，其中所述焊料结构的所述展宽部分的宽度至少2倍于所述焊料结构的所述伸长部分的宽度。
9.根据权利要求1的焊料突点结构，其中所述下突点金属化层包括所述微电子衬底上的铬层，与所述微电子衬底相对的所述铬层上的铬和铜的相控层，与所述铬层相对的所述相控层上的铜层。
10.根据权利要求9的焊料突点结构，其中所述下突点金属化层包括位于所述铬层和所述微电子衬底之间的钛层。
11.根据权利要求1的焊料突点结构，还包括所述下突点金属化层和所述焊料结构之间的金属间化合物区，所述金属间化合物区包括所述金属化层的成分和所述焊料结构的成分。
12.一种在包括所述微电子衬底表面的电接触焊盘的微电子衬底上形成再分布路径的导体的方法，所述方法包括以下步骤：
在所述表面上形成下突点金属化层，用于电接触所述电接触焊盘；以及
在与所述微电子衬底相对的所述下突点金属化层上形成所述焊料结构，所述焊料结构包括伸长部分和展宽部分。
13.根据权利要求12的方法，还包括使所述焊料结构中的焊料从所述伸长部分流到所述展宽部分的步骤，从而在所述焊料结构的所述展宽部分中形成突起的焊料突点，和在所述焊料结构所述伸长部分中形成薄焊料层。
14.根据权利要求12的方法，其中所述伸长部分延伸到所述电接触焊盘上。
15.根据权利要求12的方法，其中所述焊料结构限定了未被所述焊料结构覆盖的所述下突点金属化层的第一部分和被所述焊料结构覆盖的所述下突点金属化层的第二部分，其中形成焊料结构的步骤后接选择性地除去所述下突点金属化层的所述第一部分的步骤。
16.根据权利要求12的方法，其中所述焊料结构限定了未被所述焊料结构覆盖的所述下突点金属化层的第一部分和被所述焊料结构覆盖的所述下突点金属化层的第二部分，所述的方法还包括以下步骤：
在所述下突点金属化层的所述第一部分上形成焊料阻挡层；以及
使所述焊料结构流动以便焊料从所述焊料结构的所述伸长部分流到所述焊料结构的所述展宽部分的步骤，从而在所述下突点金属化层的所述展宽部分上形成突起的焊料突点，和在所述下突点金属化层所述伸长部分中形成薄焊料层。
17.根据权利要求16的方法，其中使所述焊料结构流动在所述下突点金属化层和所述焊料结构之间形成金属间化合物区的所述步骤中，所述金属间化合物区包括所述金属化层的成分和所述焊料结构的成分。
18.根据权利要求12的方法，其中形成所述下突点金属化层的所述步骤包括以下步骤：
在所述微电子衬底上形成铬层；
在与所述微电子衬底相对的所述铬层上形成铬和铜的相控层；
在与所述铬层相对的所述相控层上形成铜层。
19.根据权利要求18的方法，其中形成所述下突点金属化层的所述步骤还包括在位于所述铬层和所述微电子衬底之间形成钛层的步骤。
20.根据权利要求12的方法，其中所述焊料结构限定了未被所述焊料结构覆盖的所述下突点金属化层的第一部分和被所述焊料结构覆盖的所述下突点金属化层的第二部分，其中形成所述焊料结构的所述步骤还包括以下步骤：
在所述下突点金属化层上形成构图的掩模层，所述构图的掩模层覆盖所述下突点金属化层的第一部分，限定所述下突点金属化层的第二部分；
在所述下突点金属化层的第二部分上形成所述焊料结构；以及
选择性地除去所述构图的掩模层。
CNB96193624XA 1995-04-05 1996-03-21 具有伸长部分和展宽部分的焊料结构及其形成方法 Expired - Fee Related CN1179412C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US41661995A 1995-04-05 1995-04-05
US08/416,619 1995-04-05

Publications (2)

Publication Number Publication Date
CN1183169A true CN1183169A (zh) 1998-05-27
CN1179412C CN1179412C (zh) 2004-12-08

Family

ID=23650663

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB96193624XA Expired - Fee Related CN1179412C (zh) 1995-04-05 1996-03-21 具有伸长部分和展宽部分的焊料结构及其形成方法

Country Status (10)

Country Link
US (3) US5892179A (zh)
EP (1) EP0819318B1 (zh)
JP (1) JP3549208B2 (zh)
KR (2) KR100425750B1 (zh)
CN (1) CN1179412C (zh)
AT (1) ATE240586T1 (zh)
AU (1) AU5316996A (zh)
DE (1) DE69628161T2 (zh)
HK (1) HK1008266A1 (zh)
WO (1) WO1996031905A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101459088B (zh) * 2007-12-13 2010-06-09 中芯国际集成电路制造(上海)有限公司 再分布金属层及再分布凸点的制作方法
CN101360388B (zh) * 2007-08-01 2010-10-13 全懋精密科技股份有限公司 电路板的电性连接端结构及其制法
CN101346039B (zh) * 2007-01-10 2011-01-12 李察·华德·鲁考斯基 一种可改善信号完整度的创新穿孔结构
US7884471B2 (en) 2004-08-27 2011-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Solder bump and related intermediate structure having primary and secondary portions and method of manufacturing same
CN104253100A (zh) * 2013-06-28 2014-12-31 精材科技股份有限公司 晶片封装体

Families Citing this family (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
JP3549208B2 (ja) 1995-04-05 2004-08-04 ユニティヴ・インターナショナル・リミテッド 集積再分配経路設定導体、はんだバイプならびにそれらにより形成された構造を形成する方法
US5851911A (en) 1996-03-07 1998-12-22 Micron Technology, Inc. Mask repattern process
US5902686A (en) * 1996-11-21 1999-05-11 Mcnc Methods for forming an intermetallic region between a solder bump and an under bump metallurgy layer and related structures
CA2294430C (en) * 1997-06-26 2016-02-02 Charles Schwab & Co., Inc. System and method for automatically providing financial services to a user using speech signals
EP0899787A3 (en) * 1997-07-25 2001-05-16 Mcnc Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby
US6441487B2 (en) * 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
EP1082884B1 (de) * 1998-06-02 2002-01-16 Siemens S.A. Verfahren zur herstellung von verdrahtungen mit lothöckern
US6085968A (en) * 1999-01-22 2000-07-11 Hewlett-Packard Company Solder retention ring for improved solder bump formation
US6380555B1 (en) * 1999-12-24 2002-04-30 Micron Technology, Inc. Bumped semiconductor component having test pads, and method and system for testing bumped semiconductor components
US6373137B1 (en) * 2000-03-21 2002-04-16 Micron Technology, Inc. Copper interconnect for an integrated circuit and methods for its fabrication
US6362087B1 (en) * 2000-05-05 2002-03-26 Aptos Corporation Method for fabricating a microelectronic fabrication having formed therein a redistribution structure
KR100668809B1 (ko) * 2000-06-30 2007-01-16 주식회사 하이닉스반도체 웨이퍼 레벨 패키지
TW494548B (en) * 2000-08-25 2002-07-11 I-Ming Chen Semiconductor chip device and its package method
DE60108413T2 (de) * 2000-11-10 2005-06-02 Unitive Electronics, Inc. Verfahren zum positionieren von komponenten mit hilfe flüssiger antriebsmittel und strukturen hierfür
US6666368B2 (en) 2000-11-10 2003-12-23 Unitive Electronics, Inc. Methods and systems for positioning substrates using spring force of phase-changeable bumps therebetween
US6418033B1 (en) 2000-11-16 2002-07-09 Unitive Electronics, Inc. Microelectronic packages in which second microelectronic substrates are oriented relative to first microelectronic substrates at acute angles
TW517334B (en) * 2000-12-08 2003-01-11 Nec Corp Method of forming barrier layers for solder bumps
JP4656275B2 (ja) * 2001-01-15 2011-03-23 日本電気株式会社 半導体装置の製造方法
JP2002222578A (ja) * 2001-01-26 2002-08-09 Nitto Denko Corp 中継フレキシブル配線回路基板
US6443631B1 (en) 2001-02-20 2002-09-03 Avanti Optics Corporation Optical module with solder bond
US6546173B2 (en) * 2001-02-20 2003-04-08 Avanti Optics Corporation Optical module
US20040212802A1 (en) * 2001-02-20 2004-10-28 Case Steven K. Optical device with alignment compensation
US6546172B2 (en) 2001-02-20 2003-04-08 Avanti Optics Corporation Optical device
US6956999B2 (en) 2001-02-20 2005-10-18 Cyberoptics Corporation Optical device
US6759319B2 (en) 2001-05-17 2004-07-06 Institute Of Microelectronics Residue-free solder bumping process
US6502231B1 (en) 2001-05-31 2002-12-31 Applied Micro Circuits Corporation Integrated circuit template cell system and method
US6550665B1 (en) * 2001-06-06 2003-04-22 Indigo Systems Corporation Method for electrically interconnecting large contact arrays using eutectic alloy bumping
US6541303B2 (en) * 2001-06-20 2003-04-01 Micron Technology, Inc. Method for conducting heat in a flip-chip assembly
US6762122B2 (en) 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding
EP1310436A1 (fr) * 2001-11-09 2003-05-14 SOLVAY POLYOLEFINS EUROPE - BELGIUM (Société Anonyme) Capsule à visser comprenant une composition à base de polymère de l'éthylène multimodal
US7310039B1 (en) 2001-11-30 2007-12-18 Silicon Laboratories Inc. Surface inductor
US6644536B2 (en) * 2001-12-28 2003-11-11 Intel Corporation Solder reflow with microwave energy
US7547623B2 (en) * 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
WO2004001837A2 (en) * 2002-06-25 2003-12-31 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
US7531898B2 (en) * 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
US7632750B2 (en) * 2006-07-07 2009-12-15 Semigear Inc Arrangement for solder bump formation on wafers
US6965160B2 (en) * 2002-08-15 2005-11-15 Micron Technology, Inc. Semiconductor dice packages employing at least one redistribution layer
WO2004019094A1 (en) * 2002-08-20 2004-03-04 Cyberoptics Corporation Optical alignment mount with height adjustment
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
US7141883B2 (en) * 2002-10-15 2006-11-28 Silicon Laboratories Inc. Integrated circuit package configuration incorporating shielded circuit element structure
US20040222511A1 (en) * 2002-10-15 2004-11-11 Silicon Laboratories, Inc. Method and apparatus for electromagnetic shielding of a circuit element
US7135780B2 (en) * 2003-02-12 2006-11-14 Micron Technology, Inc. Semiconductor substrate for build-up packages
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
TWI255538B (en) * 2003-06-09 2006-05-21 Siliconware Precision Industries Co Ltd Semiconductor package having conductive bumps on chip and method for fabricating the same
US6960820B2 (en) * 2003-07-01 2005-11-01 International Business Machines Corporation Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same
KR100546346B1 (ko) * 2003-07-23 2006-01-26 삼성전자주식회사 재배선 범프 형성방법 및 이를 이용한 반도체 칩과 실장구조
US7244671B2 (en) * 2003-07-25 2007-07-17 Unitive International Limited Methods of forming conductive structures including titanium-tungsten base layers and related structures
US7416106B1 (en) * 2003-09-29 2008-08-26 Emc Corporation Techniques for creating optimized pad geometries for soldering
US7049216B2 (en) * 2003-10-14 2006-05-23 Unitive International Limited Methods of providing solder structures for out plane connections
KR100994768B1 (ko) * 2003-12-08 2010-11-16 삼성전자주식회사 동영상 부호화를 위한 움직임 추정 방법 및 이를 구현하기위한 프로그램이 기록된 기록 매체
US7427557B2 (en) * 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
DE102004035080A1 (de) * 2004-05-27 2005-12-29 Infineon Technologies Ag Anordnung zur Verringerung des elektrischen Übersprechens auf einem Chip
JP2008501231A (ja) * 2004-05-28 2008-01-17 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ ２つのチップコンタクト群を備えるチップ
US7375411B2 (en) * 2004-06-03 2008-05-20 Silicon Laboratories Inc. Method and structure for forming relatively dense conductive layers
US7419852B2 (en) 2004-08-27 2008-09-02 Micron Technology, Inc. Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
DE102004046699A1 (de) * 2004-09-24 2006-04-13 Infineon Technologies Ag Anordnung zum Verbinden von Kontaktflächen durch eine sich verfestigende Flüssigkeit
US20060205170A1 (en) * 2005-03-09 2006-09-14 Rinne Glenn A Methods of forming self-healing metal-insulator-metal (MIM) structures and related devices
US7501924B2 (en) * 2005-09-30 2009-03-10 Silicon Laboratories Inc. Self-shielding inductor
US20070090156A1 (en) * 2005-10-25 2007-04-26 Ramanathan Lakshmi N Method for forming solder contacts on mounted substrates
US7932615B2 (en) * 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7723224B2 (en) * 2006-06-14 2010-05-25 Freescale Semiconductor, Inc. Microelectronic assembly with back side metallization and method for forming the same
TWI313037B (en) * 2006-12-12 2009-08-01 Siliconware Precision Industries Co Ltd Chip scale package structure and method for fabricating the same
CN101226889B (zh) * 2007-01-15 2010-05-19 百慕达南茂科技股份有限公司 重配置线路结构及其制造方法
US7834449B2 (en) * 2007-04-30 2010-11-16 Broadcom Corporation Highly reliable low cost structure for wafer-level ball grid array packaging
KR101350972B1 (ko) * 2007-05-18 2014-01-14 엘지디스플레이 주식회사 백라이트 유닛과 이를 포함하는 액정표시장치모듈
US7858438B2 (en) * 2007-06-13 2010-12-28 Himax Technologies Limited Semiconductor device, chip package and method of fabricating the same
US7872347B2 (en) 2007-08-09 2011-01-18 Broadcom Corporation Larger than die size wafer-level redistribution packaging process
FR2920634A1 (fr) * 2007-08-29 2009-03-06 St Microelectronics Grenoble Procede de fabrication de plots de connexion electrique d'une plaque.
FR2924302B1 (fr) * 2007-11-23 2010-10-22 St Microelectronics Grenoble Procede de fabrication de plots de connexion electrique d'une plaque
CN101355066B (zh) * 2008-05-26 2011-05-18 苏州晶方半导体科技股份有限公司 封装结构及其制造方法
US8643164B2 (en) 2009-06-11 2014-02-04 Broadcom Corporation Package-on-package technology for fan-out wafer-level packaging
US8362612B1 (en) 2010-03-19 2013-01-29 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US8441124B2 (en) * 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
TWI555100B (zh) 2010-07-26 2016-10-21 矽品精密工業股份有限公司 晶片尺寸封裝件及其製法
TWI423355B (zh) 2010-08-04 2014-01-11 矽品精密工業股份有限公司 晶片尺寸封裝件及其製法
TWI426587B (zh) 2010-08-12 2014-02-11 矽品精密工業股份有限公司 晶片尺寸封裝件及其製法
JP5537341B2 (ja) * 2010-08-31 2014-07-02 株式会社東芝 半導体装置
US8288203B2 (en) * 2011-02-25 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bump
US8648664B2 (en) 2011-09-30 2014-02-11 Silicon Laboratories Inc. Mutual inductance circuits
KR20140041975A (ko) 2012-09-25 2014-04-07 삼성전자주식회사 범프 구조체 및 이를 포함하는 전기적 연결 구조체
US8802556B2 (en) * 2012-11-14 2014-08-12 Qualcomm Incorporated Barrier layer on bump and non-wettable coating on trace
US9466590B1 (en) * 2015-11-13 2016-10-11 International Business Machines Corporation Optimized solder pads for microelectronic components
KR102315634B1 (ko) * 2016-01-13 2021-10-22 삼원액트 주식회사 회로 기판
US10120971B2 (en) * 2016-08-30 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and layout method thereof
US11158595B2 (en) * 2017-07-07 2021-10-26 Texas Instruments Incorporated Embedded die package multichip module

Family Cites Families (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3259814A (en) 1955-05-20 1966-07-05 Rca Corp Power semiconductor assembly including heat dispersing means
DE1182353C2 (de) 1961-03-29 1973-01-11 Siemens Ag Verfahren zum Herstellen eines Halbleiter-bauelements, wie Halbleiterstromtor oder Flaechentransistor, mit einer hochohmigen n-Zone zwischen zwei p-Zonen im Halbleiter-koerper
US3244947A (en) 1962-06-15 1966-04-05 Slater Electric Inc Semi-conductor diode and manufacture thereof
US3274458A (en) 1964-04-02 1966-09-20 Int Rectifier Corp Extremely high voltage silicon device
US3458925A (en) 1966-01-20 1969-08-05 Ibm Method of forming solder mounds on substrates
DE1614928A1 (de) * 1966-07-19 1970-12-23 Solitron Devices Verfahren zur Kontaktierung von Halbleiter-Bauelementen
DE1764096A1 (de) 1967-04-04 1971-05-27 Marconi Co Ltd Oberflaechen-Feldeffekt-Transistor
US3461357A (en) 1967-09-15 1969-08-12 Ibm Multilevel terminal metallurgy for semiconductor devices
NL159822B (nl) * 1969-01-02 1979-03-15 Philips Nv Halfgeleiderinrichting.
GB1288564A (zh) * 1969-01-24 1972-09-13
US3871015A (en) * 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform connector joints
US3871014A (en) * 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform solder wettable areas on the substrate
US3663184A (en) * 1970-01-23 1972-05-16 Fairchild Camera Instr Co Solder bump metallization system using a titanium-nickel barrier layer
DE2044494B2 (de) * 1970-09-08 1972-01-13 Siemens AG, 1000 Berlin u 8000 München Anschlussflaechen zum anloeten von halbleiterbausteinen in flip chip technik
US3760238A (en) * 1972-02-28 1973-09-18 Microsystems Int Ltd Fabrication of beam leads
JPS49135749U (zh) 1973-03-24 1974-11-21
US4113578A (en) * 1973-05-31 1978-09-12 Honeywell Inc. Microcircuit device metallization
US3959577A (en) 1974-06-10 1976-05-25 Westinghouse Electric Corporation Hermetic seals for insulating-casing structures
US3993123A (en) 1975-10-28 1976-11-23 International Business Machines Corporation Gas encapsulated cooling module
US4257905A (en) 1977-09-06 1981-03-24 The United States Of America As Represented By The United States Department Of Energy Gaseous insulators for high voltage electrical equipment
JPS5459080A (en) 1977-10-19 1979-05-12 Nec Corp Semiconductor device
US4168480A (en) 1978-02-13 1979-09-18 Torr Laboratories, Inc. Relay assembly
JPS55111127A (en) * 1979-02-19 1980-08-27 Fuji Electric Co Ltd Method for forming solder bump
JPS5678356U (zh) 1979-11-12 1981-06-25
US4273859A (en) 1979-12-31 1981-06-16 Honeywell Information Systems Inc. Method of forming solder bump terminals on semiconductor elements
JPS5773952A (en) * 1980-10-27 1982-05-08 Hitachi Ltd Chip for face down bonding and production thereof
JPS57197838A (en) * 1981-05-29 1982-12-04 Oki Electric Ind Co Ltd Semiconductor flip chip element
US4449580A (en) 1981-06-30 1984-05-22 International Business Machines Corporation Vertical wall elevated pressure heat dissipation system
JPS58146827A (ja) 1982-02-25 1983-09-01 Fuji Electric Co Ltd 半導体式圧力センサ
CH664040A5 (de) 1982-07-19 1988-01-29 Bbc Brown Boveri & Cie Druckgasisolierter stromwandler.
JPS59154041A (ja) * 1983-02-22 1984-09-03 Fuji Electric Corp Res & Dev Ltd 半導体装置の電極形成方法
JPS602011A (ja) 1983-06-14 1985-01-08 三菱電機株式会社 ガス絶縁電気装置
US4545610A (en) * 1983-11-25 1985-10-08 International Business Machines Corporation Method for forming elongated solder connections between a semiconductor device and a supporting substrate
US4661375A (en) 1985-04-22 1987-04-28 At&T Technologies, Inc. Method for increasing the height of solder bumps
JPS6116552A (ja) * 1985-06-21 1986-01-24 Hitachi Ltd 集積回路装置
US4878611A (en) * 1986-05-30 1989-11-07 American Telephone And Telegraph Company, At&T Bell Laboratories Process for controlling solder joint geometry when surface mounting a leadless integrated circuit package on a substrate
GB2194387A (en) 1986-08-20 1988-03-02 Plessey Co Plc Bonding integrated circuit devices
JPH0793304B2 (ja) * 1987-03-11 1995-10-09 富士通株式会社 バンプ電極の形成方法
JPS6461934A (en) * 1987-09-02 1989-03-08 Nippon Denso Co Semiconductor device and manufacture thereof
US4897508A (en) 1988-02-10 1990-01-30 Olin Corporation Metal electronic package
JPH01214141A (ja) 1988-02-23 1989-08-28 Nec Corp フリップチップ型半導体装置
US4840302A (en) 1988-04-15 1989-06-20 International Business Machines Corporation Chromium-titanium alloy
US4927505A (en) * 1988-07-05 1990-05-22 Motorola Inc. Metallization scheme providing adhesion and barrier properties
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
CA2002213C (en) 1988-11-10 1999-03-30 Iwona Turlik High performance integrated circuit chip package and method of making same
US5024372A (en) * 1989-01-03 1991-06-18 Motorola, Inc. Method of making high density solder bumps and a substrate socket for high density solder bumps
US4962058A (en) * 1989-04-14 1990-10-09 International Business Machines Corporation Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit
US5048747A (en) 1989-06-27 1991-09-17 At&T Bell Laboratories Solder assembly of components
US5135155A (en) 1989-08-25 1992-08-04 International Business Machines Corporation Thermocompression bonding in integrated circuit packaging
FR2663784B1 (fr) * 1990-06-26 1997-01-31 Commissariat Energie Atomique Procede de realisation d'un etage d'un circuit integre.
JPH04150033A (ja) * 1990-10-12 1992-05-22 Sharp Corp 電子回路基板のバンプ並びに電子回路基板のバンプ及び回路パターンの形成方法
US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5194137A (en) * 1991-08-05 1993-03-16 Motorola Inc. Solder plate reflow method for forming solder-bumped terminals
US5160409A (en) * 1991-08-05 1992-11-03 Motorola, Inc. Solder plate reflow method for forming a solder bump on a circuit trace intersection
EP0598006B1 (en) 1991-08-05 1996-11-20 Motorola, Inc. Solder plate reflow method for forming a solder bump on a circuit trace
US5162257A (en) * 1991-09-13 1992-11-10 Mcnc Solder bump fabrication method
US5923539A (en) 1992-01-16 1999-07-13 Hitachi, Ltd. Multilayer circuit substrate with circuit repairing function, and electronic circuit device
US5371431A (en) 1992-03-04 1994-12-06 Mcnc Vertical microelectronic field emission devices including elongate vertical pillars having resistive bottom portions
US5281684A (en) * 1992-04-30 1994-01-25 Motorola, Inc. Solder bumping of integrated circuit die
JPH0637143A (ja) 1992-07-15 1994-02-10 Toshiba Corp 半導体装置および半導体装置の製造方法
US5448014A (en) 1993-01-27 1995-09-05 Trw Inc. Mass simultaneous sealing and electrical connection of electronic devices
US5479042A (en) 1993-02-01 1995-12-26 Brooktree Corporation Micromachined relay and method of forming the relay
KR940023325A (ko) * 1993-03-11 1994-10-22 토모마쯔 켕고 땜납층을 프리코팅해서 사용되는 회로기판 및 땜납층이 프리코팅된 회로기판
FR2705832B1 (fr) 1993-05-28 1995-06-30 Commissariat Energie Atomique Procédé de réalisation d'un cordon d'étanchéité et de tenue mécanique entre un substrat et une puce hybridée par billes sur le substrat.
JP3263875B2 (ja) 1993-08-24 2002-03-11 ソニー株式会社 表面実装型電子部品の製造方法及び表面実装型電子部品
US5802699A (en) 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
US5492235A (en) * 1995-12-18 1996-02-20 Intel Corporation Process for single mask C4 solder bump fabrication
US5557502A (en) 1995-03-02 1996-09-17 Intel Corporation Structure of a thermally and electrically enhanced plastic ball grid array package
US5547740A (en) * 1995-03-23 1996-08-20 Delco Electronics Corporation Solderable contacts for flip chip integrated circuit devices
US5760526A (en) 1995-04-03 1998-06-02 Motorola, Inc. Plastic encapsulated SAW device
JP3549208B2 (ja) 1995-04-05 2004-08-04 ユニティヴ・インターナショナル・リミテッド 集積再分配経路設定導体、はんだバイプならびにそれらにより形成された構造を形成する方法
US5773359A (en) * 1995-12-26 1998-06-30 Motorola, Inc. Interconnect system and method of fabrication
US5851911A (en) 1996-03-07 1998-12-22 Micron Technology, Inc. Mask repattern process
US5736456A (en) 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
US6025767A (en) 1996-08-05 2000-02-15 Mcnc Encapsulated micro-relay modules and methods of fabricating same
US5898574A (en) 1997-09-02 1999-04-27 Tan; Wiling Self aligning electrical component

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7884471B2 (en) 2004-08-27 2011-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Solder bump and related intermediate structure having primary and secondary portions and method of manufacturing same
CN101346039B (zh) * 2007-01-10 2011-01-12 李察·华德·鲁考斯基 一种可改善信号完整度的创新穿孔结构
CN101360388B (zh) * 2007-08-01 2010-10-13 全懋精密科技股份有限公司 电路板的电性连接端结构及其制法
CN101459088B (zh) * 2007-12-13 2010-06-09 中芯国际集成电路制造(上海)有限公司 再分布金属层及再分布凸点的制作方法
CN104253100A (zh) * 2013-06-28 2014-12-31 精材科技股份有限公司 晶片封装体
CN104253100B (zh) * 2013-06-28 2017-04-12 精材科技股份有限公司 晶片封装体

Also Published As

Publication number Publication date
KR19987003571A (en) 1998-11-05
AU5316996A (en) 1996-10-23
EP0819318A1 (en) 1998-01-21
US5892179A (en) 1999-04-06
DE69628161D1 (de) 2003-06-18
HK1008266A1 (en) 1999-05-07
DE69628161T2 (de) 2004-03-25
JPH11503566A (ja) 1999-03-26
US6329608B1 (en) 2001-12-11
CN1179412C (zh) 2004-12-08
JP3549208B2 (ja) 2004-08-04
ATE240586T1 (de) 2003-05-15
US6389691B1 (en) 2002-05-21
KR100425750B1 (ko) 2004-07-16
KR19980703571A (ko) 1998-11-05
EP0819318B1 (en) 2003-05-14
WO1996031905A1 (en) 1996-10-10

Similar Documents

Publication Publication Date Title
CN1179412C (zh) 具有伸长部分和展宽部分的焊料结构及其形成方法
US6452270B1 (en) Semiconductor device having bump electrode
US7906425B2 (en) Fluxless bumping process
US6570251B1 (en) Under bump metalization pad and solder bump connections
US7391112B2 (en) Capping copper bumps
US6011314A (en) Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps
US6740577B2 (en) Method of forming a small pitch torch bump for mounting high-performance flip-flop devices
US7777333B2 (en) Structure and method for fabricating flip chip devices
JP3393755B2 (ja) 低融点金属キャップを有するリフローはんだボールによる相互接続構造
US20020086520A1 (en) Semiconductor device having bump electrode
EP1387402A2 (en) Wafer-level method for fine-pitch, high aspect ratio chip interconnect
US9373596B2 (en) Passivated copper chip pads
US6583039B2 (en) Method of forming a bump on a copper pad
US20080308931A1 (en) Electronic Structures Including Barrier Layers Defining Lips
KR20010098699A (ko) 납 없는 범프 배선의 형성 방법
US6774495B2 (en) Solder terminal and fabricating method thereof
JP2004501504A (ja) 相互接続構造を形成するための方法及び装置
US6664176B2 (en) Method of making pad-rerouting for integrated circuit chips
US6805279B2 (en) Fluxless bumping process using ions
US7176117B2 (en) Method for mounting passive components on wafer
US6897141B2 (en) Solder terminal and fabricating method thereof
US6692629B1 (en) Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer
US20040099941A1 (en) Flip-chip device having conductive connectors
US6713320B2 (en) Bumping process
Greig Flip chip—the bumping processes

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: UNITY INTERNATIONAL LIMITED

Free format text: FORMER OWNER: MICROELECTRONICS CENTRE OF NORTH CAROLING

Effective date: 20010712

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20010712

Address after: The Netherlands Antilles

Applicant after: Unitive Internat Ltd.

Address before: North Carolina

Applicant before: North Carolina Microelectronic Center

C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee