CN1187890A - 提供远程pci槽扩展的装置和方法 - Google Patents
提供远程pci槽扩展的装置和方法 Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
Abstract
提供PCI槽扩展(21)的装置和方法。插入一个主PCI槽(10)中的异步PCI到PCI桥路(34)通过一条电缆式PCI总线(16)连接到一个扩展模块(4)。该桥路建立两个不同的时域。产生一个扩展时钟信号(18),其定时要为在整个扩展时钟域上一致到达而匹配。由此扩展的槽数可为主系统使用。
Description
1.发明领域
本发明涉及计算机系统的总线结构,具体说,本发明涉及使用PCI作为电缆总线扩展系统中可用的PCI槽的数目。
2.相关技术
外设部件互连(PCI)总线是高性能低等待时间I/O总线,它能使系统成本最低。计算机工业界很快广泛接受了PCI总线。PCI总线标准提供了高带宽和高度灵活性,这些性能独立于新的处理器技术和提高了的处理器速度,目前计算机系统设计师主要在设计用于PCI总线的速度敏感的外设,诸如图形加速器和SCSI磁盘驱动器控制器。
PCI规范已确切定义,特别参见PCI局部总线规范,修改版2.0,1993年4月30日。该规范反应了PCI能够以直到33MHz的任何频率运行。这种高水平的可能吞吐量使得PCI成为规模服务器(volume server)的理想选择。不幸的是,在这种速度下,PCI总线沿单一总线段只支持3-4个槽。这种槽数目在规模服务器市场对于实际应用来说低得不能接受。一些现有技术已解决这一问题,它把多个PCI总线级联到主母板上。不幸的是这样的级联增加了基本系统的成本,而且仍然不能提供规模服务器必需的槽扩展水平。此外,这种单机箱系统在用户需求改变时不容易扩展。
在多个模块化机箱之间以总线连接的可能性在PCI的意义上隐含某种独特的问题。具体说,使用可用的PCI到PCI桥路必须同步时钟系统宽度。因为PCI不需要标准的主时钟信号,所以不能使用锁相环来同步桥路的两侧。多机箱系统的剪切物理尺寸使单时钟域的这种同步甚至更成问题。这些问题要求必须定制设计电路来提供机箱外的槽扩展。
另外,PCI总线的规范需要为所有支持的槽有4个低电平有效电平敏感的中断插脚,并定义这些中断作为硬件共享应用。这意味着多个PCI设备可以驱动同一中断线或者多个PCI中断线可以由不同的设备驱动,但是可能对系统中断控制器产生单一中断,它由一个共享的中断驱动程序服务,于是,随着必须共享中断的槽数目的增加,解决中断源需要的资源和开销也随着共享槽数目的增加而增加。
由此希望提供一种装置,它能使PCI槽扩展而无需不必要地增加主系统的成本。这种装置应能向前和向后兼容,不需为每一特定系统定制。扩展槽的性能必须维持在一个可接受的高水平上,同时系统的可扩展性应该易于满足日益增加的处理器能力的需求。还希望开发一种简化由这种所扩展的系统产生的中断的方式。
附图简介
图1表示本发明的主机模块和扩展模块的方框图;
图1A是本发明的电缆总线中的信号和所需插脚的表;
图2是本发明的模块接口的方框图;
图3是用于本发明扩展模块的时钟生成电路的图;
图4是列出适用于本发明的电缆的性能指标的表;
图4A是表示为本发明的两个可能操作点的定时预算表。
发明概述
本发明提供扩展可用于主系统的PCI槽数目的装置和方法。通过使用一个异步PCI到PCI桥路,隔离主机时域和扩展时域。响应在扩展模块中产生和控制的时钟信号的电缆式PCI总线用于在独立的主机箱和扩展机箱之间传送信号。因为扩展系统不依赖于主机时钟或者主系统的功能,因此适于集成在现有系统中,而且并不增加基本主系统的成本。从而本发明在需求改变时很容易扩展。
在一个实施例中,除槽扩展外,本发明还提供中断扩展。这是通过提供连到扩展卡上的主APCI总线的设备和提供将由扩展PCI槽产生的PCI中断编码到在扩展母板上的APCI中的设备而实现的。这种扩展将减少与由扩展槽共享的中断服务关联的总开销。
本发明的详细描述
本发明提供一种方法和装置,它使用电缆式PCI总线提供扩展可用于主系统的PCI槽的数目。为说明起见,叙述特定的细节以提供对本发明的彻底理解。然而,熟悉本技术领域的人理解,通过阅读本说明书,本发明可以不用这些细节实现。此外,公知的元件、设备、处理步骤等等未加叙述以避免模糊本发明。
图1表示了包括了本发明的系统的方框图。该主系统位于一个主机箱1内,它包括一个主母板3。该主母板有由系统总线7连接到存储器6的CPU5。该母板上提供桥路8以桥接系统总线7和主PCI总线9。在33MHz下,PCI性能指标仅允许在单一总线段上有3-4个槽10。通过在主PCI总线9上至少一个槽10中安装一个扩展卡11,能够扩展系统总体的槽数目。
扩展卡11有一个基本扩展桥路(PEB)12(下面参考图2详细叙述)和一个电缆接头15,一个示例实施例使用100个插脚的电缆接头。扩展卡还提供一个可选的APCI连接器14以允许卡11连接到APCI总线(在主母板3上未示出)上。这允许足够的信号导体容纳所有PCI需要的信号的并行传输线和足够的接地。图1A是一个相关PCI信号表。根据沿电缆16的传播速度和电缆偏斜选择电缆16。最好选择最小偏斜而有最大传播速度的电缆16。电缆16用作在PEB16的扩展侧和辅助扩展桥路(SEB)19(下面详细叙述)之间的点对点PCI总线。电缆16的两端都要以近似等于该电缆的特性阻抗的阻抗端接。在示例实施例中,使用特性阻抗为88±5欧姆的6英尺HIPPI电缆。HIPPI电缆满足ANSI标准,包括50个双绞线,从而提供合适数目的信号线。也可以使用较小的电缆和较少插脚的连接器,但是这将在某种程度上限制其功能。
扩展机箱2包括一个扩展母板4,电缆16通过连接器17连接在其上。PCI总线从连接器连到SEB。扩展系统中的定时由时钟发生器18提供,它与主机时钟(未示出)异步而独立。辅助PCI总线(SPB)20上可用的槽21的数目由产生的时钟信号的速度决定。在25MHz下,有8-12槽可用;而在33MHz下,只有3-4槽可用。
在本发明的范围内希望和可能把多个扩展模块连接到单一主模块上(每一可用的PCI槽插一卡)。从一个扩展模块级联一个扩展模块也在本发明的范围之内。
图2更清楚地叙述PEB12、电缆16和SEB19之间的关系。图2分为3个时钟域。主时钟域30,扩展时钟域32和一个可选APCI时钟域31。本发明使用主模块和扩展模块之间的一个异步桥路33。一个PCI到PCI桥路包括一个基本总线接口和一个辅助总线接口。在异步桥路的情况下,基本总线接口负责主时钟,而辅助接口负责扩展时钟,从而在主时钟域30和扩展时钟域32之间产生一个异步边界13。在最基本的水平下,这可以为每一相关信号使用一对D触发器而实现。实际上为保证时钟速率变化场合下数据的有效性,最好在这两个接口之间提供某种存储。边界内和边界外的4×16字节的队列认为是适当的。有关进一步的细节参见PCI到PCI的桥路规范,修订版1.0,1994年4月15日。
在一个示例实施例中,主PCI总线连接到扩展卡上PEB中包含的一个异步PCI到PCI桥路33上。桥路33的主机侧在主时钟域30中运行,而扩展侧与扩展时钟域32同步。PEB12还包括一个多路分离器38以便多路分离从扩展系统来的支持4个PCI的中断。在PEB12中还可以提供一个可选APCI总线接口36,从而扩展扩展系统可用的中断。这种接口必须部分以APCI时钟域31、部分以扩展时钟域32异步运行,值得注意的是该选项不符合PCI规范。在共同未决的申请“集成PCI到PCI桥路的I/O处理器结构”中的智能I/O单元支持这些功能。因此,本发明设想的一个实施例使用这样的一个智能I/O单元作为PEB12。
异步桥路33的扩展端通过电缆式PCI总线16连接到扩展母板41上的SEB19上。电缆16包括PCI总线信号44,扩展域时钟信号40,一个SINT#39。SINT#39不是标准的PCI线,而是传送串行化的标准PCI中断的一条线。串行化标准PCI中断的一种方法是连续使4个标准PCI中断信号与PCI时钟同步,并在发生变化时通过在SINT#上的接口使用如图5所示的由一个开始位(低)、INTA#、INTB#、INTC#、INTD#、奇校验位和一个中止位(高)组成的协议发送信息。如果一个中断在I/OAPCI上未屏蔽,那么就不应该在SINT#信号上对INT#线进行串行化(亦即它应该解释为是不活动的)。在这种情况下,I/OAPCI将负责分配中断给主模块。SINT#协议在复位期间被连续驱动(所有中断都不活动)。中断串行器还在16个不活动时钟后发送一个新消息。
PEB使用SINT#解码INTA#、INTB#、INTC#、INTD#的当前值。每当中断多路分离器方框观察到SINT#变低,则它捕获接下来4个时钟的数据,并且如果奇偶校验(开始位后第5个时钟)正确,那么使用该数据更新4个中断输出的当前值。如果检测到奇偶性不正确,则忽略该数据。该中断串行化过程为每一级扩展子系统在最坏情况下引起9个时钟的延迟(2个用于同步,7个用于发送),它在25MHz下为360ns。这只是串行化中断的一个简单的方式。对于本技术领域一般技能的人员来说,可以想到其它的串行化方案,这样的方案可以考虑用于本发明。
在电缆16的扩展端,SEB19包含PCI到PCI桥路34,它可以是同步的也可以是异步的。SEB19还可选包含一个I/OAPCI35,它扩展可由该扩展系统使用的中断数目,并减少或者消除轮询,在组合的主、扩展系统中所有的PCI槽仅共享提供4个PCI的中断时需要这种轮间。最后,提供一个中断控制设备37要么在电缆16到多路选择器的范围控制PCI支持的中断,或者,如果提供的话,控制槽中断进入I/O APCI35,后者接着沿电缆16将该中断传送到APCI总线接口36。再次考虑使用在共同未决申请中叙述的智能I/O单元来实现SEB19。另外,在扩展母板4上有时钟发生设备18和辅助PCI总线45。
在图2中,在辅助PCI总线45上显示了8个槽21。PCI不定义最大槽数,它只刚性定义电气特征。具体说,PCI定义时钟偏斜+主板上要输出的时钟+在目的地的建立时间+调整时间≤时钟周期。在下面叙述的时钟发生方案中分配给调整的时间用作沿电缆16向下的飞行时间,从而减少在主模块和扩展模块之间的事务处理的等待时间。由于每一槽21的引入增加系统的容量,从而不利地影响状态之间的事务处理速度,亦即调整时间,因此较慢的时钟增加了可用于调整的时间,从而相应地增加了系统可以处理的负载(槽)的数目。如果运行在25MHz下的话,可考虑提供8-12槽。
图3表示本发明的时钟发生,振荡器50产生一个最高33MHz的所希望的频率的时钟信号。可以看出,不一定使用振荡器产生时钟信号,可以使用任何产生具有希望频率的信号的常规的方法。在示例实施例中,振荡器50产生25MHz的时钟信号。
本发明需要多个从单一信号源产生的时钟复制。图3表示通向电缆16和10条其它信号线58的时钟信号。这对右面的槽21和SEB19来说是足够的。在电缆15的主接口端和扩展机箱接口58使用的时钟必须在时钟偏斜定时要求内到达。为此目的,沿每一线使用低偏斜时钟驱动器51以便使沿不同线的偏斜最小,并在本地线和远程接口之间引入一个延迟元件。通过使在电缆16到主(远程)接口15中的传播延迟与延迟元件52匹配,有可能分别在接口15和58处实现希望的时钟同步。为选择一个合适的延迟线52值,存在两种可选方案,一种是要么将到该电缆的该信号延迟为电缆中的传播延迟来延迟本地线或者将到该电缆的该信号延迟为它的时钟信号周期减去该传播延迟的时间。图3说明沿本地线引入的延迟元件52。打算使用一种无源延迟线或者合适的高速缓冲器实现希望的延迟。扩展母板4和SEB19上的槽21之间的最大时钟偏斜是2ns。图4反应满足PCI规范的可能的选择。重要的是每一时钟信号线应该尽可能紧密匹配。于是,沿每一线使用同一数目的缓冲器驱动器51。阻抗56应该与扩展母板4上的时钟迹线的特性阻抗匹配。此外,从缓冲器51到它们的目的地的印刷电路板迹线的长度应该尽可能紧密匹配,包括从驱动电缆连接的缓冲器来的迹线。这可以通过增加所有迹线的长度以匹配自然长度最长的迹线而实现。最关键的长度匹配是在通向SEB19的时钟和通过电缆16驱动PEB12的时钟之间的长度匹配。适当选择延迟线52的值将改善这一匹配。
电气连接方案使用桥路芯片(亦即PEB和SEB)连接到使用串联端接的电缆。这一端接是外部的。串联端接值等于电缆阻抗减去驱动器阻抗。电缆的源端用1/2电压入射波形驱动,该电压入射波形由于在电缆末端所遇到的数值为1的反射系数加倍而成为全电压波形。在驱动电缆时,串联端接形成半波入射波形,它遇到系数为1的反射。在使用6英尺电缆的实施例中,这种电缆的特性阻抗是88±5欧姆。相应地,适当的端接阻抗可以参考所选择的驱动器的阻抗而选择。
还可能把时钟发生器18放在扩展卡11上。尽管上述同样的规则可应用于这种安排,然而维持需要的信号协调随着要协调的远程信号数目的增加而更成问题。尽管如此,这种安排仍然在本发明的范围和考虑之内。
在上述说明中,参考具体的实施例叙述了本发明,然而十分明显,可以对其进行各种修改而不离开在所附权利要求中说明的本发明的更宽的精神和范围,相应地本说明书和附图应该视为是说明性的而非限制性的。因此,本发明的范围只应由所附权利要求限制。
Claims (21)
1.一种提供PCI槽扩展的的装置,包括:
一个扩展卡,所述卡具有在其上配置的一个异步PCI到PCI桥路,该桥路有主机侧和扩展侧,用以连接到一块主母板;
具有多个PCI槽的扩展板;
一个电缆式PCI总线,用于连接该扩展卡到该扩展母板;
一个时钟发生器,用于提供时钟信号给扩展母板和异步PCI到PCI桥路的扩展侧。
2.如权利要求1所述装置,其中,所述时钟发生器配置在扩展母板上。
3.如权利要求2所述装置,其中,时钟发生器产生一个25MHz的信号。
4.如权利要求2所述装置,其中,
扩展母板进一步包括一个辅助扩展桥路;
连接电缆信号到具有多个槽的一个扩展PCI总线。
5.如权利要求4所述装置,其中,
辅助扩展桥进一步包括一个中断控制电路和一个I/OAPCI;
扩展卡进一步包括一个APCI接口。
6.如权利要求1所述装置,其中,所述异步桥路是一个智能I/O单元。
7.如权利要求4所述装置,其中,辅助扩展桥路是一个智能I/O单元。
8.一个提供扩展的PCI槽数目的模块化计算机系统,包括:
一个主模块,具有其上配置CPU的主母板;
一个配置在该主母板上、响应主时钟并具有多个主PCI槽的PCI总线;
一个扩展卡,用于连接多个主PCI槽中的一个;
一个具有扩展母板的扩展模块,所述扩展母板具有带多个扩展PCI槽和响应一个扩展时钟信号的一个扩展PCI总线;
一个电缆式PCI总线,用于连接主模块和扩展模块。
9.如权利要求8所述模块化计算机系统,进一步包括
一个基本扩展桥路,用于提供该电缆式总线和该主PCI总线之间的接口;
一个辅助扩展桥路,用于提供该电缆式总线和该扩展PCI总线之间的接口;
配置在该扩展模块之内的一个时钟发生器,用于产生所述扩展时钟信号。
10.如权利要求9所述模块化计算机系统,其中:
所述基本扩展桥路包括一个异步PCI到PCI桥路和一个多路分离器;
所述辅助扩展桥路包括一个PCI到PCI桥路和一个中断控制单元。
11.如权利要求9所述模块化计算机系统,其中,所述扩展时钟信号是25MHz。
12.如权利要求9所述模块化计算机系统,其中,所述电缆式总线包括一根每端有100针接头的100个电缆导线。
13.如权利要求9所述模块化计算机系统,其中,所述基本扩展桥路是一个智能I/O单元。
14.如权利要求10所述模块化计算机系统,其中,所述基本扩展桥路进一步包括;
一个APCI接口单元;
所述辅助扩展桥路进一步包括一个I/OAPCI单元。
15.在一个计算机系统中提供PCI槽模块化扩展的方法,包括的步骤有:
在主模块的一个PCI槽中安装一块扩展卡;
用电缆连接所述扩展卡到一个扩展模块;
产生一个独立于主时钟信号的扩展时钟信号;
在该扩展卡上隔离该主时钟信号和扩展时钟信号;
在沿电缆的模块之间用电缆实现PCI传输。
16.如权利要求15所述方法,其中,所述隔离步骤是由一个异步PCI到PCI桥路实现的。
17.如权利要求15所述方法,其中,所述生成步骤进一步包括协调扩展时钟信号到达多个本地和远程接口的步骤。
18.如权利要求15所述步骤,其中,所述电缆是作为一个点对点的PCI总线端接和操作的。
19.如权利要求17所述方法,包括:
在所述扩展卡上提供一个APCI总线接口;
在所述扩展模块内放置一个I/O A PCI单元;
把在所述扩展模块中产生的中断传递给主APCI总线。
20.如权利要求15所述方法,其中,一个智能I/O单元执行所述隔离步骤。
21.提供PCI槽扩展的装置,包括:
为安装在一个主系统PCI槽中而隔离主时域和扩展时域的设备;
在一预定距离内传输时钟信号的设备;
为所述扩展时域产生时钟信号的设备;
一个响应所述扩展时域时钟的扩展PCI总线,所述扩展总线具有多个PCI槽;
其中,有从扩展总线传输更多PCI信号到所述隔离设备的设备和所述隔离设备在所述时域之间传递信号。
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US08/490,778 | 1995-06-15 | ||
US08/490,778 US5696949A (en) | 1995-06-15 | 1995-06-15 | System for PCI slots expansion using asynchronous PCI-to-PCI bridge with clock generator for providing clock signal to the expansion mother board and expansion side of bridge |
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CN1187890A true CN1187890A (zh) | 1998-07-15 |
CN1098492C CN1098492C (zh) | 2003-01-08 |
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CN96194775A Expired - Fee Related CN1098492C (zh) | 1995-06-15 | 1996-06-17 | 提供远程pci槽扩展的装置和方法 |
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US (3) | US5696949A (zh) |
EP (1) | EP0832458B1 (zh) |
JP (1) | JPH11514112A (zh) |
KR (1) | KR100291051B1 (zh) |
CN (1) | CN1098492C (zh) |
AU (1) | AU6281896A (zh) |
DE (1) | DE69636519D1 (zh) |
HK (1) | HK1009866A1 (zh) |
WO (1) | WO1997000481A1 (zh) |
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- 1996-06-17 CN CN96194775A patent/CN1098492C/zh not_active Expired - Fee Related
- 1996-06-17 KR KR1019970709312A patent/KR100291051B1/ko not_active IP Right Cessation
- 1996-06-17 AU AU62818/96A patent/AU6281896A/en not_active Abandoned
- 1996-06-17 DE DE69636519T patent/DE69636519D1/de not_active Expired - Lifetime
- 1996-06-17 JP JP9503396A patent/JPH11514112A/ja not_active Ceased
-
1997
- 1997-09-15 US US08/929,624 patent/US5954821A/en not_active Expired - Lifetime
-
1998
- 1998-09-22 HK HK98110832A patent/HK1009866A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100291051B1 (ko) | 2001-08-07 |
HK1009866A1 (en) | 1999-06-11 |
US5696949A (en) | 1997-12-09 |
US5954821A (en) | 1999-09-21 |
KR19990022843A (ko) | 1999-03-25 |
DE69636519D1 (de) | 2006-10-19 |
EP0832458A1 (en) | 1998-04-01 |
JPH11514112A (ja) | 1999-11-30 |
AU6281896A (en) | 1997-01-15 |
EP0832458B1 (en) | 2006-09-06 |
US5835784A (en) | 1998-11-10 |
CN1098492C (zh) | 2003-01-08 |
EP0832458A4 (en) | 2002-07-24 |
WO1997000481A1 (en) | 1997-01-03 |
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