CN1195188A - 扩散阻挡层的淀积方法 - Google Patents

扩散阻挡层的淀积方法 Download PDF

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CN1195188A
CN1195188A CN98105911A CN98105911A CN1195188A CN 1195188 A CN1195188 A CN 1195188A CN 98105911 A CN98105911 A CN 98105911A CN 98105911 A CN98105911 A CN 98105911A CN 1195188 A CN1195188 A CN 1195188A
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tantalum
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CN1204607C (zh
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阿加伊·加因
伊利沙白·威茨曼
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34Nitrides
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

采用金属有机化学淀积可以形成难熔金属氮化物和难熔金属硅氮化物层(64)。特别地,采用乙基三(二乙基酰胺基)钽(ETDET)和氨(NH3)通过化学汽相淀积可形成氮化钽(TaN)(64)。加入硅烷(SiH4),还可以形成钽硅氮化物(TaSiN)层(64)。上述薄膜均可在硅片温度低于400摄氏度时形成,并且都有较低的含碳(C)量。因此,本发明的实施例可以用来制造氮化钽(TaN)或钽硅氮化物(TaSiN)层(64),该层具有较好的保形性和扩散阻挡性。

Description

扩散阻挡层的淀积方法
本发明一般涉及半导体器件工艺,尤其涉及在半导体器件上提供扩散阻挡层。
目前半导体器件所需速度已超过200兆赫兹。为制造下一代半导体器件,要将铜(Cu)用于互连。采用铜将引起的问题之一是铜不能直接接触二氧化硅,这是因为铜很容易扩散穿通二氧化硅层。因此,在现有工艺中一般铜的所有面均被扩散阻挡层所包围。
铜的扩散阻挡层包括大量材料,如氮化硅,各种难熔金属氮化物(TiN,TaN,WN,MoN)和难熔硅氮化物(TiSiN,TaSiN,WSiN)或难熔金属-半导体-氮化物层。在所有这些阻挡层中,最有前途的两种是氮化钽(TaN)和钽硅氮化物(TaSiN)。这些材料通常用溅射的方法淀积。但是,溅射通常对侧壁台阶覆盖较差,所谓台阶覆盖是指在特定表面上淀积层厚度与在半导体器件上表面上淀积层厚度之比。当溅射氮化钽(TaN)和钽硅氮化物(TaSiN)时,若高宽比为3∶1,则0.35微米通孔的台阶覆盖为5%到20%。如此低的台阶覆盖增加了阻挡材料不够厚从而无法沿深孔的底部和侧壁形成有效扩散阻挡层的危险。为了沿开口侧壁得到足够材料,可以在最上表面淀积更厚的一层,但是这会导致互连电阻的增加,因此是不可取的。
利用化学汽相淀积(CVD)形成氮化钽。用于生成氮化钽的先质(precursor)包括卤化钽,例如五氯化钽。采用卤化钽而导致的问题是卤化物与铜反应而腐蚀互连。另一种先质是五(二甲基胺)钽(Ta(Nme2)5)。当采用这种先质淀积氮化钽时,实际生成化合物Ta3N5的绝缘层。因为绝缘层阻挡了上互连层和下互连层的电学连接,所以绝缘层不能用于接触孔和通孔。
还有另外一种已知的先质是叔丁基亚氨-3-二乙氨基钽[(TBTDET),Ta=NBu(NEt2)3]。这种化合物可以用来生成TaN。但是,采用这种先质也有问题。特别是适当地淀积低阻薄膜需要淀积温度高于600℃。如此高的温度在背端金属化时与低k介质是矛盾的,并且将在背端材料之间引入导致热失配的高应力。采用TBTDET先质引起的另一个问题是在薄膜中将掺入过多的碳(C)。该化合物通常含有25%原子的碳。如此高的碳含量将增加薄膜的电阻,并降低薄膜密度,削弱薄膜对较厚材料的扩散阻挡效果。采用TBTDET在低于600℃的温度下淀积的氮化钽,其电阻率为12,000微欧姆-厘米。具有如此高电阻率的薄膜(期望小于1,000微欧姆-厘米)是不能用于有效的互连结构的。
采用四氯化钛(TiCl4)进行钛硅氮化物(TiSiN)的CVD已被证实。但并不期望存在该化合物,因为在形成TiSiN的过程中出现了氯,其腐蚀了用于互连的铜或其它材料。
因此,需要一种采用有机-金属先质在低温下淀积氮化钽和TaSiN的方法,该方法即满足良好的电阻率,又具有优良的阻挡特性。
本发明以实例的方式说明,但并不局限于附图,其中相同的标号代表相同的部分,图中:
图1是半导体器件衬底的部分剖面图,在器件的衬底上有层间绝缘层,在绝缘层上开孔暴露出在衬底中的掺杂区;
图2是图1的剖面根据本发明的一个实施例形成用于互连材料后的剖面图;
图3是在图2中的衬底上形成与衬底中掺杂区的镶嵌互连;
图4是在图3中衬底上形成层间绝缘层并开孔后的顶视图;
图5是图4中衬底的剖面图,形成了到下互连层的孔;
图6是在图5中衬底上形成了与下互连层的互连的剖面图;
图7是在图6中衬底上形成了大体上的完整器件后的剖面图。
熟练的技术人员知道图中的元件被简化了,并且没有按比例绘制。例如,图中一些元件的尺寸相对于其它部分有些夸大,这是为了使本发明的实施例易于理解。
采用金属有机物化学淀积形成难熔金属氮化物和难熔金属硅氮化物层。特别是利用乙基三(二乙基酰胺基)钽[(ETDET),(Et2N)3Ta=NEt]和氨(NH3)采用化学汽相淀积(CVD)形成氮化钽(TaN)。通过包含半导体源如硅烷,也可以形成钽硅氮化物(TaSiN)层。以上各层均可在硅片温度低于500摄氏度的条件下形成,薄膜中含有少量的碳(C)。因此,本发明的实施例可以用来形成相对稳定并具有良好扩散阻挡特性的氮化钽或钽硅氮化物层。
在本说明书中,化学汽相淀积是不同于溅射淀积的一种淀积方法。溅射淀积本质上是一种通过使等离子体直接轰击目标靶而在硅片表面淀积薄膜的物理淀积方法。从目标靶上轰击出来的材料基本上垂直地淀积于硅片上。而与此相对,化学汽相淀积是发生于衬底表面或附近的化学反应,在硅片暴露的表面上形成了薄膜。
采用ETDET/NH3和ETDET/NH3/SiH4分别形成氮化钽(TaN)和钽硅氮化物(TaSiN)。对于氮化钽,淀积通常在化学汽相淀积反应室内进行,气压通常为5-15乇的范围内。监控的淀积温度取决于被监控点的温度。如果监控加热器,温度一般在400-480摄氏度范围内。如果测量硅片温度,温度一般在350-400摄氏度范围内。
用氦气(He)引入ETDET作为载气流过导管引入。氦气(He)的流量在200-800sccm范围内。导管加热箱的温度维持在大约80摄氏度。通常,加热箱的温度维持在大约50-90摄氏度。在导管内ETDET的温度大约比加热箱的温度低10摄氏度。引入的氨气(NH3)的流量在200-500sccm的范围内时一般淀积速率大约为150-200埃/分钟。淀积速率也决定于反应物的组成。采用以上参数可以淀积含碳(C)量少于15%的氮化钽薄膜,一般含碳量不高于1%。当采用该薄膜作为阻挡层时,一般在暴露的衬底表面淀积的氮化钽薄膜厚度大约在200-300埃范围内,在高宽比为3∶1的孔下表面处,台阶覆盖大于50%。
已观察到氨的流量增强了所有温度范围内的淀积。若没有氨,即使在高的硅片温度下也只能观察到极有限的淀积或根本不可能观察到淀积。这与文献报道采用先质(TBTDET)淀积氮化钽不一样,其淀积不采用氨气(NH3)。
在化学汽相淀积系统中,在孔的底部淀积薄膜一般是更困难的,因此,底部的台阶覆盖是薄膜最薄部分的标志。对于金属表面和氧化物表面,氮化钽均具有良好的粘附性。这对于将该层集成到互连工艺中是非常重要的。该薄膜应该用来与半导体衬底内的含有栅电极或掺杂区的硅互连(电学上和物理上),在氮化钽和硅(Si)之间可以淀积钛以形成良好的欧姆接触。没有钛,由于氮化钽和p+硅之间较大的功函数差,在氮化钽和p+硅之间将形成相对较高的接触电阻。
淀积TaSiN的参数除了以下所述与上述参数相同。气压一般在0.1-1乇范围内。气体流量略微有所改变:在与上述淀积氮化钽条件相同的导管中,氦气(He)的流量大约在50-150sccm的范围内;氨气的流量大约为150-300sccm;硅烷的流量大约为1-10sccm。采用以上参数淀积的速率大约为150-250埃/分钟,其含碳量和粘附特性与氮化钽层基本一致。
不同的源气体可以作为硅源和氮化钽的先质。特别是,可以采用乙硅烷(Si2H6)或其它含硅气体。更进一步,还可以采用含有其它半导体源如锗的源气体。但是必须注意确保不会发生汽相反应。并且,淀积时硅片温度不应超过500摄氏度,基于上述考虑,一般应低于400摄氏度。TaN先质具有同样的关系。通常,乙基原子团与双键氮原子相连可以组成乙基[(Et2N)3Ta=NEt]或甲基[(Et2N)3Ta=NMe]原子团。通过导管的载气包括氦气(He),氩气(Ar),氮气(N2)或氢气(H2)。
通过化学汽相淀积氮化钽薄膜后,可以用现场等离子体处理薄膜,这样可以降低淀积薄膜的电阻率。不同的气体如氩气,氢气,氮气,硅烷和氨气,在等离子体处理时,可以单独采用也可以混合采用。例如,采用氩气一般可以以系数2或更多来降低薄膜电阻率。其它气体与氩气一起采用会有更好的效果,但这并不是必须的。采用硅烷将允许在薄膜中引入硅,这样将在晶格中形成TaSiN。这种处理方法可以控制薄膜中硅和氮的比例。以上气体的流量在100-1000sccm的范围内;气压在100毫乇-15乇的范围内;等离子体功率在100-2000瓦特范围内。等离子体处理也可以周期性地进行,即,淀积/等离子体处理/淀积。并且,为在薄膜中引入硅,采用硅烷对薄膜进行热退火可以代替等离子体处理。该工艺将在淀积结束后使硅烷气体流过加热的硅片。退火条件与等离子体处理的条件基本一致除了没有等离子体。
采用了实例以更好地理解本发明的实施例,其中通过化学汽相淀积材料形成了两层互连。图1是在形成互连之前,部分半导体器件衬底10的剖面图。半导体器件衬底10是单晶半导体晶片,半导体在绝缘体上的半导体晶片或其它用于制造半导体器件的衬底。场隔离区12形成于半导体器件衬底10上。掺杂区14是晶体管的源/漏区,其位于衬底10与场隔离区12相邻处。栅绝缘层22和栅电极24覆盖了衬底10和掺杂区14的部分。层间绝缘层26淀积于半导体器件衬底10上。层间绝缘层26可以包括非掺杂,掺杂或掺杂与非掺杂二氧化硅薄膜的混合。在特定的实施例中,非掺杂二氧化硅薄膜被硼磷硅玻璃层(BPSG)所覆盖。在层26平坦化后,通过层间绝缘层26形成开孔28暴露掺杂区14。如图1所示,孔28包括与掺杂区14接触相对较窄的接触部分,以及形成互连的相对较宽的互连沟槽。在图1的实例中,与沟槽部分相比接触部分的高宽比为3∶1。这是当前常规工艺中双镶嵌工艺形成镶嵌互连的实例。
在层间绝缘层26上和孔28中淀积用于接触和互连的材料。如图3所示,图中是半成品器件,形成了钛膜32或其它难熔金属薄膜,该薄膜与掺杂区14接触。该薄膜一般厚度为100-400埃。然后,在层32上形成了氮化钽或TaSiN层34。淀积氮化钽或TaSiN层34采用如前所述的淀积参数。该层的厚度在200-300埃范围内。导电层36形成在孔中的剩余部分内并覆盖在层34上。导电层36一般包括铜(Cu),铝(Al),钨(W)或其它类似物质。在该特定的实施例中,导电层36是铜。然后,抛光半成品器件,去除层间绝缘层26上的层32,34和36。如图3所示,这样就形成了用于互连的接触部分和互连部分42和44。
在第一层间绝缘层26上和互连层42和44上淀积并且图形化第二层间绝缘层56。图4和图5分别是图形化第二层间绝缘层的顶视图和剖面图。第二层间绝缘层56包括掺杂或非掺杂氧化物。图形化形成了通孔52和互连沟槽54。其它通孔和互连沟槽也形成,但在图4和图5中并没有画出。
如图6所示,采用前述淀积方法的一种淀积氮化钽或TaSiN薄膜64。层64接触下层互连42。层64的厚度大约在200-300埃的范围内,材料与层36相似的第二导电层66覆盖在层64上。通过抛光去除层64和层66覆盖于第二层间绝缘层上并在互连沟槽以外的部分以得到如图6所示的结构。层64和层66组合在一起构成了半导体器件的位线62。如图7所示,在第二层互连上覆盖钝化层72就形成了大体上完整的器件70。在另一个实施例中,还可再形成其它的绝缘层和互连层,但是图中并没有画出。
采用本发明的实施例有许多优点。采用化学汽相淀积形成氮化钽或TaSiN的反应是在硅片温度低于大约500摄氏度的条件下完成的,一般低于400摄氏度。因此,该工艺可满足低k介质,并且不会在薄膜内引起高应力。引入的碳杂质少于15%原子百分比,一般为1%或更少。因此,该薄膜没有孔,并且与采用TBTDET作为先质相比,该薄膜具有更好的扩散阻挡特性。碳含量的减少使得采用化学汽相淀积形成氮化钽薄膜的电阻率与采用TBTDET的当前工艺相比至少降低了一个数量级。另外,本实施例的另一个优点是相对易于集成到现有的工艺过程中。
综上所述,本发明提供了一种淀积扩散阻挡层的工艺,该工艺用于制造半导体器件,其具有前述所有优点。虽然本发明是参考特定直观的实施例描述的,但是这并不意味本发明局限于直观的实施例。熟练的技术人员可以不违背本发明的精神而对本发明进行变动和修改。因此,本发明内的这种变动和修改均应包括在本发明的附加权利要求书中。

Claims (5)

1.一种制造半导体器件的方法,其特征在于包括以下步骤:
将半导体衬底放入化学汽相淀积(CVD)反应室中;
将金属有机先质引入(CVD)反应室;
将半导体源引入(CVD)反应室;并且
与金属有机先质反应使半导体源形成难熔金属-半导体-氮化物层(34)。
2.根据权利要求1的方法,其中,难熔金属-半导体-氮化物层(34)的碳原子含量少于约15%原子百分比。
3.根据权利要求1的方法,其中,难熔金属-半导体-氮化物层(34)的台阶覆盖率大于约50%。
4.一种制造半导体器件的方法,其特征在于包括以下步骤:
将半导体衬底放入化学汽相淀积反应室中;
将先质引入化学汽相淀积反应室,其中,该先质
包括[(R1)2N]3-Ta=NR2,其中R1包括乙基,R2包括乙基和甲基中的一种;
将氨引入化学汽相淀积反应室;并且
使先质与氨发生反应形成含有钽和氮的层(34)。
5.一种制造半导体器件的方法,其特征在于包括以下步骤:
在半导体器件衬底上形成第一绝缘层(26),其中第一绝缘层有孔(28);
采用化学汽相淀积淀积第一难熔金属-半导体-氮化物层(34);并且
在形成第一难熔金属-半导体-氮化物层(34)后,形成第一导电层(36),其中第一导电层包括铝或铜。
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