CN1196186C - 剥除时间反馈控制以减少剥除后晶体管栅极临界尺寸变化 - Google Patents

剥除时间反馈控制以减少剥除后晶体管栅极临界尺寸变化 Download PDF

Info

Publication number
CN1196186C
CN1196186C CNB018125603A CN01812560A CN1196186C CN 1196186 C CN1196186 C CN 1196186C CN B018125603 A CNB018125603 A CN B018125603A CN 01812560 A CN01812560 A CN 01812560A CN 1196186 C CN1196186 C CN 1196186C
Authority
CN
China
Prior art keywords
divests
instrument
grid
width
rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB018125603A
Other languages
English (en)
Other versions
CN1441962A (zh
Inventor
J·S·蓝斯佛得
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN1441962A publication Critical patent/CN1441962A/zh
Application granted granted Critical
Publication of CN1196186C publication Critical patent/CN1196186C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/418Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS], computer integrated manufacturing [CIM]
    • G05B19/41865Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS], computer integrated manufacturing [CIM] characterised by job scheduling, process planning, material flow
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/30Nc systems
    • G05B2219/32Operator till task planning
    • G05B2219/32096Batch, recipe configuration for flexible batch control
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/30Nc systems
    • G05B2219/45Nc applications
    • G05B2219/45031Manufacturing semiconductor wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

本发明提供一种用于减少栅极宽度变化的方法。此方法包含有提供其中形成有栅极(230)且在此栅极(230)的至少部分表面上形成有防反射涂敷层(240)的晶片。此栅极(230)具有宽度。量测栅极(230)的宽度。决定用于移除此防反射涂敷(240)的剥除工具(130)的剥除率。将所量测到的栅极(230)宽度与目标栅极临界尺寸相比较以便依据剥除率决定过度蚀刻的时间。根据过度蚀刻的时间修正剥除工具(130)的操作方法。处理线(100)包含有第一度量工具(120)、剥除工具(130)和处理控制器(150)。此第一度量工具(120)用于量测在晶片上所形成的栅极(230)宽度。此栅极(230)的至少部分表面上形成有防反射涂敷层(240)。此剥除工具(130)用于移除防反射涂敷层(240)。此处理控制器(150),用于决定剥除工具(130)的剥除率,比较栅极(230)的宽度和目标栅极的临界尺寸以便依据剥除率决定过度蚀刻时间,且依据过度蚀刻时间修正剥除工具(130)的操作方法。

Description

剥除时间反馈控制以减少剥除后晶体管栅极临界尺寸变化
技术领域
本发明涉及半导体装置制造的领域,尤其涉及使用剥除时间的反馈控制以减少于晶体管栅极上剥除后临界尺寸变化的方法和装置。
背景技术
半导体技术中持续的趋势为制造更多和/或更快的半导体装置。此趋势使得极大规模集成电路(ULSI)能够继续减少装置和电路的尺寸和特征。举例而言,在具有场效晶体管的集成电路中,一个非常重要的处理步骤为形成用于各晶体管的栅极,在此特别重视其栅极的尺寸。在许多应用中,性能特性(例,切换速度)和晶体管的尺寸为装置的沟道长度的函数,其大约对应于晶体管栅极的宽度。因此,举例而言,具有较小沟道长度的较窄装置倾向于产生性能较高的晶体管(例,较快速),此自然而然地使尺寸变小。
通常,栅极是通过利用传统的光刻技术绘制由栅极材料(例,多晶硅)所组成的处理层而形成的。依据传统的实施例,有时候会使用防反射涂敷(ARC)以便减少在光刻技术进行期间因反射而引起刻痕。通常,ARC层是位于多晶硅层上。光阻层则是形成于ARC层上。ARC层降低反射且允许在光阻层上具有更多的有效图案,其最终可导致在多晶硅层上形成更多有效的栅极。ARC层的材料可以是氮氧化硅(siliconoxynitride)和多氮化硅(silicon rich nitride)。
在栅极形成之后,利用如在热氢氟酸(HF)剥除之后紧接着热磷酸盐(H3PO4)剥除的蚀刻程序将ARC层移除。前面的氢氟酸剥除是相当短暂的且其作用是用于移除因为曝露于空气中而在ARC层的表面上增长的硅氧化物薄层。在多晶硅栅极的曝露表面上亦形成有此种硅氧化物,但不是利用氢氟酸剥除移除。氢氟酸剥除,不是特别适用于移除二氧化硅,但可移除覆盖在栅极上表面的ARC层。
氢氟酸剥除亦稍微蚀刻多晶硅栅极,因此会减少其临界尺寸。氢氟酸槽用于移除ARC层的剥除率会改变其使用寿命。因此,在剥除工具的操作方法中所使用的剥除时间包含有特定数量的过度蚀刻时间以便确保所有ARC层均已移除,就算此槽是处于衰退最严重的时期。槽的剥除率随着所蚀刻晶片数目增加因为反应物的集结而衰退。此槽亦因为槽中氢氟酸氧化状态的相对浓度随时间改变而衰退。因此,在槽刚开始使用的早期所处理的晶片将以较高的速率剥除,导致于栅极的临界尺寸减少愈多。槽的剥除率的变动将直接导致于栅极的临界尺寸变化。而栅极的临界尺寸变化将导致于装置的速度、泄漏、及其它晶体管性能参数变动。通常,所增加的变动会降低生产力、产量、及利润。
本发明用于克服或至少降低前文中所提及的一个或多个问题所产生的影响。
发明内容
本发明一方面提供用于减少栅极宽度变动的方法。此方法包含有提供其中形成有栅极且在此栅极的至少部分表面上形成有防反射涂敷层的晶片。此栅极具有宽度。量测栅极的宽度。决定适合于移除此防反射涂敷的剥除工具的剥除率。将所量测到的栅极宽度与栅极临界尺寸的指针相比较以便依据剥除率决定过度蚀刻的时间。依据过度蚀刻的时间修正剥除工具的操作方法。
本发明另一方面为处理线包含有第一度量工具、剥除工具、和处理控制器。使用第一度量工具以便量测在晶片上所形成的栅极宽度。此栅极具有在栅极至少部分表面上所形成的防反射涂敷层。使用剥除工具以便移除防反射涂敷。使用处理控制器决定用于剥除工具的剥除率、将所量测到的栅极宽度与栅极临界尺寸的指针相比较以便依据剥除率决定过度蚀刻的时间、及依据过度蚀刻的时间修正剥除工具的操作方法。
附图说明
通过参考下列详细说明及其所伴随的附图可了解本发明,其中相同的参考数字标示相同的组件,且其中:
图1显示依据本发明所说明的一个实施例的处理线的简化方块图;
图2A至2B显示在晶体管形成中各处理步骤的概要截面图以便说明图1的处理控制器的操作;
图3A至3B显示在晶体管形成中各处理步骤的概要截面图以便说明图1的处理控制器的操作;和
图4显示依据本发明所说明一个实施例用于降低栅极宽度变动的方法的简化方块图。
虽然本发明可接受各种修正及其它形式,在此等图标中显示特殊实施例作为范例且将在文中详细说明。可是,应该了解此特殊实施例的说明并不是用于将本发明限制于所揭发的特殊形式,但相反地,本发明希望涵盖由本发明所附权利要求定义的精神和目的内的所有修正、均等、及其它形式。
具体实施方式
下文中将说明本发明的实施例。为了文体的清晰,在此说明书中并未说明实际应用的所有特征。当然希望在此种实际实施例的发展中,必须先决定各种特殊应用的需求以便达到发明者的特殊目的,如可与相关系统和相关商业限制兼容,这些可能会随着不同的应用而有所改变。再者,应了解到此研发结果虽然复杂且费时,但对具有此方面技艺者而言将因本发明的揭示而变成不过是例行工作。
现参考图1,显示依据本发明而提供的用于处理晶片110的处理线100的简化方块图。处理线100包含有前置剥除的度量工具120、剥除工具130、后置剥除的度量工具140、及处理控制器150。使用剥除工具130以便移除绘图之后在晶体管栅极出现的ARC层,如硅氧化层。在此所显示的剥除工具130为单一工具,但在实际应用中,剥除工具130可能有用于执行多个剥除操作的多个剥除工具,这些操作可以是氢氟酸剥除和磷酸盐剥除。
处理控制器150从度量工具120、140接收数据且调整剥除工具130的操作方法以便降低离开晶体管栅极的临界尺寸变化。在所显示实施例中,度量工具120、140为扫描用电子显微镜。虽然,在此显示不同的度量工具120、140,但是可使用单一种工具作为前置剥除和后置剥除的量测。同时,每一种度量工具120、140可能包含有超过一种以上的度量工具。举例而言,前置剥除度量工具120量测栅极的宽度(例,使用扫描电子显微镜)且同时量测ARC层的厚度(例,使用光学探针式的厚度量测工具)。
在所显示的实施例中,处理控制器150为计算机,其具有的软件规划成可实现上述功能。可是,如具此方面技艺者所了解的,亦可使用设计成可实现特殊功能的硬件控制器。再者,由处理控制器150所执行的功能,如此处所说明的,可以是由分布在系统各处的多个控制器装置执行。除此之外,处理控制器150可以是独立的控制器,其存在于剥除工具130之内,或可以是集成电路制造公司用于控制操作系统之一部份。本发明的部分及其相关细节说明是以计算机内存内数据位的操作的软件或算法及符号表示法的方式呈现。通过这些说明及其表示式具有此方面技艺者将可有效地将其本身工作的本质传达给其它具此方面技艺者。在此所使用及一般使用的算法相信是可导致所希望结果的有条理的步骤程序。这些步骤为需要对实际物理量进行实际操作的步骤。通常,虽然并不是绝对必要,这些物理量的形式为能够储存、传输、组合、比较、及进行其它操作的光、电子或磁的信号。有时候证明为了方便,主要是为了可共同使用,这些信号最好是以位、值、组件、符号、特性、专用术语、编号等表示。
可是应该记住的是所有上述及相似术语均是为了与相关物理量相关连且为这些物理量提供方便的卷标。除非特别提及其它,或可从讨论明显得知,如”处理”或”使用计算机计算”或”计算”或”判定”或”显示”等等,表示计算机系统或类似电子计算装置的动作和处理,其处理如计算机系统缓存器及内存内电气物理量等的数据且将其转换成其它数据,此数据可以是计算机系统内存或缓存器或其它讯息储存装置、传输或显示装置内的物理量。
能够用于执行上述处理控制器150的功能的软件系统范例为由KLA-Tencor公司所提供的Catalyst系统。Catalyst系统使用与国际半导体装置和材料(Semiconductor Equipment and Material Intemational SEMI)计算机整体制造(Computer Integrated Manufacturing,CIM)组织兼容的系统技术且是依据Advanced Process Control(APC)组织。SEMI的CIM(SEMI E81-0699-暂时申请说明书,用于CIM组织的主要结构)和APC(SEMI E93-0999-暂时申请说明书,用于CIM组织的AdvancedProcess Control Component)是对外公开的。
图2A至2B和图3A至3B显示晶体管形成中各处理步骤的概要截面图。在图2A中,显示其中形成有具浅沟槽隔离(STI)结构210的基体200。在基体200上形成栅极隔离层220。在栅极隔离层220上形成栅极230。栅极隔离层220使栅极230和基体200隔离。在栅极230绘制图案期间,提供防反射涂敷(ARC)层240以便减少在进行光刻技术期间因反射而引起的凹槽。用于栅极的目标临界尺寸250是以虚线表示。注意目标临界尺寸250小于栅极230的实际宽度(W),如虚线252所标示的。
图1的前置剥除量测工具120量测栅极230的宽度且提供此测量值给处理控制器150。如图2B中所显示,处理控制器150调整剥除工具130用于移除ARC层240的方法且继续蚀刻栅极230直到其宽度与目标临界尺寸250相吻合。下文中将更详细说明处理控制器150的用于调整剥除工具130的方法的功能。
在图3A中所显示的范例中,目标临界尺寸250大于栅极230的实际宽度(W),如虚线252所标示的。依据前置剥除量测工具120的测量值,处理控制器150调整剥除工具130用于移除ARC层240的方法,但是一旦达到最小剥除时间即停止蚀刻以便降低栅极230过度蚀刻的量(参考图3B)。栅极230的宽度仍旧会稍微减少,但是将过度蚀刻时间减少以便避免将栅极230的宽度减少过多。
总而言之,处理控制器150决定用于移除ARC层240的最小剥除时间和用于将栅极230宽度降低至目标临界尺寸250的过度蚀刻时间。假如栅极230的宽度在剥除之前已经较目标临界尺寸250窄,则将过度蚀刻时间设定为零。处理控制器150为剥除工具130所采用的方法在最小剥除时间和过度蚀刻时间之间选择较大值。
处理控制器150可使用一个或多个用于决定最小剥除时间和过度蚀刻时间的模式。这些模式包含有以相当简单的方程式为基础的模式(例,线性、指数、加权平均等等)或较复杂的模式,如类神经网络模式、主要组件分析(PCA,principal component analysis)模式、或潜在结构预测(PLS,projection to latent structures)模式。这些模式的特殊应用是随着选择用于建立模式的技术而改变,且此特殊应用对具此方面技艺者而言是显而易见的。因此,为了说明的简洁性和方便性,此特殊细节在此将不详细说明。
处理控制器150可以反馈控制模式或前馈控制模式操作。在反馈模式中,处理控制器150接收栅极230之前置剥除和后置剥除的宽度量测以便决定剥除率。为了其后所处理的晶片110,利用剥除率和如栅极230宽度和目标栅极临界尺寸等的输入数据决定其后所处理的晶片110的过度蚀刻时间。指数式加权平均用于计算因为槽衰退而在剥除工具130内必须明显降低的剥除率。处理控制器150亦从前置剥除的度量工具120接收输入的ARC层240的厚度。ARC层240的厚度可用于决定最小剥除时间。另一方面,亦可以用固定的最小剥除时间,且只要过度蚀刻时间大于最小剥除时间则可通过处理控制器150将过度蚀刻时间和剥除工具130的方法结合。
处理控制器150可调整剥除工具的方法以便改变用于氢氟酸槽和磷酸盐槽的剥除时间。通常,氢氟酸槽的剥除时间明显地小于磷酸盐槽的剥除时间,所以可更改处理控制器150使其仅修正用于磷酸盐槽的剥除时间。
处理控制器150可依据插槽内的晶片样本的量测以一个插槽为单位调整剥除工具130的操作方法。另一方面,处理控制器150可接收来自每一个晶片的量测并以一个晶片为单位调整剥除工具130的操作方法。特殊频率的选择是依据在所输入的栅极宽度上呈现的变动量和所希望的准确度。
在前馈模式的操作中,处理控制器150使用预测式模式建立技术以便预测剥除工具130的剥除率。所预测的剥除率可与输入的栅极230宽度及目标栅极临界尺寸一起使用以便决定过度蚀刻时间。同时,亦可结合输入的ARC层240厚度以便决定最小剥除时间。来自后置剥除的度量工具140的反馈可用于周期性更新此模式。执行反馈量测的频率小于输入晶片110的量测。预测式模式的输入可能包含有在剥除工具130内所使用的槽的使用时间(即,用于根据衰退时间推算)和剥除工具130内所处理的晶片数目(即,用于表示因为反应物的集结所导致的衰退)。
现参考图4,显示依据本发明所说明的实施例而提供的用于降低栅极宽度变动的方法的简化流程图。在方块400中,提供具有栅极形成于其间且在此栅极的至少一部分表面上形成有防反射涂敷的晶片。在方块410中,量测栅极的宽度。在方块420内决定为了移除防反射涂敷而选用的剥除工具的剥除率。可利用预测式性能模式决定此剥除率,或另一方面,可依据先前所处理晶片之前置剥除和后置剥除的栅极宽度量测而决定剥除率。在方块430中,将栅极宽度与目标临界尺寸相比较以便依据剥除率决定过度蚀刻时间。在方块440中,可依据过度蚀刻时间修正剥除工具的操作方法。
如上所述,控制剥除工具130的操作可降低栅极230后置剥除的临界尺寸的变化,同时可提供移除ARC层240所需的最小剥除时间。通过使用及时控制模式可有效降低此变化,且处理线100的生产量和最终产品的品质可提升。所增加的生产量和所减少的变动直接导致于利润的增加。
上述所揭露的特殊实施例仅作为说明用,因为可利用对具此方面技艺者而言是根源于在此所提出的原则的不同但等效方式修正及实现本发明。再者,并不希望限制在此所显示的结构或设计细节,除了在下文申请专利范围内所说明的。因此很明显地可改变或修正前文所揭露的特殊实施例且所有的这些变动均视为是在本发明的目的和精神范围内。因此,将在本发明权利要求内提出在此所请求的保护。

Claims (10)

1.一种用于减少栅极宽度变化的方法,包含有:
提供其中形成有栅极(230)且在此栅极(230)的至少部分表面上形成有防反射涂敷层(240)的晶片(110),此栅极(230)具有宽度;
量测栅极(230)的宽度;
决定用于移除此防反射涂敷(240)的剥除工具(130)的剥除率;
将所量测到的栅极(230)宽度与目标栅极临界尺寸相比较以便依据剥除率决定过度蚀刻的时间;
依据过度蚀刻时间修正剥除工具(130)的操作方法。
2.如权利要求1所述的方法,其中决定剥除工具(130)的剥除率包含有:
建立剥除工具(130)的性能模式;和
依据剥除工具(130)的特性和性能模式预测剥除率。
3.如权利要求1所述的方法,其中剥除工具(130)的剥除率的决定包含有依据先前所处理晶片的前置剥除的厚度和后置剥除的厚度决定剥除率。
4.如权利要求1所述的方法,还包括:
量测防反射涂敷层(240)的厚度;
依据防反射涂敷层(240)的厚度决定最小剥除时间;和
依据过度蚀刻时间和最小剥除时间的最大值修正剥除工具(130)的操作方法。
5.如权利要求2所述的方法,还包括:
处理在剥除工具(130)内的晶片;
在晶片处理后量测栅极的宽度;和
依据晶片处理后所量测到的栅极(230)宽度更新性能模式。
6.一种处理线(100),包含有:
第一度量工具(120),用于量测在晶片上所形成栅极(230)的宽度,此栅极(230)的至少部分表面上形成有防反射涂敷层(240);
剥除工具(130),使用该剥除工具移除防反射涂敷层(240);
第二度量工具(140),用于在剥除工具(130)中晶片处理后量测栅极(230)的宽度;和
处理控制器(150),用于决定剥除工具(130)的剥除率,比较栅极(230)的宽度和目标栅极临界尺寸以便依据剥除率决定过度蚀刻时间,且依据过度蚀刻时间修正剥除工具(130)的操作方法。
7.如权利要求6所述的处理线(100),其中处理控制器(150)用于储存剥除工具(130)的性能模式且依据剥除工具(130)的特性和性能模式预测剥除率。
8.如权利要求6所述的处理线(100),处理控制器(150)用于依据先前所处理晶片的前置剥除的厚度和后置剥除的厚度决定剥除工具(130)的剥除率。
9.如权利要求6所述的处理线(100),其中第一度量工具(120),用于量测防反射涂敷层(240)的厚度,其中此处理控制器(150)用于依据防反射涂敷层(240)的厚度决定最小剥除时间,并依据过度蚀刻时间和最小剥除时间的最大值修正剥除工具(130)操作方法。
10.如权利要求7所述的处理线(100),其中处理控制器(150)用于依据晶片处理后所量测到的栅极(230)宽度更新性能模式。
CNB018125603A 2000-07-12 2001-07-03 剥除时间反馈控制以减少剥除后晶体管栅极临界尺寸变化 Expired - Fee Related CN1196186C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/614,666 US6461878B1 (en) 2000-07-12 2000-07-12 Feedback control of strip time to reduce post strip critical dimension variation in a transistor gate electrode
US09/614,666 2000-07-12

Publications (2)

Publication Number Publication Date
CN1441962A CN1441962A (zh) 2003-09-10
CN1196186C true CN1196186C (zh) 2005-04-06

Family

ID=24462231

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB018125603A Expired - Fee Related CN1196186C (zh) 2000-07-12 2001-07-03 剥除时间反馈控制以减少剥除后晶体管栅极临界尺寸变化

Country Status (8)

Country Link
US (1) US6461878B1 (zh)
EP (1) EP1303874A2 (zh)
JP (1) JP2004503104A (zh)
KR (1) KR100836945B1 (zh)
CN (1) CN1196186C (zh)
AU (1) AU2001273203A1 (zh)
TW (1) TWI282134B (zh)
WO (1) WO2002005300A2 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7261745B2 (en) * 2003-09-30 2007-08-28 Agere Systems Inc. Real-time gate etch critical dimension control by oxygen monitoring
US20050221513A1 (en) * 2004-03-31 2005-10-06 Tokyo Electron Limited Method of controlling trimming of a gate electrode structure
US6852584B1 (en) * 2004-01-14 2005-02-08 Tokyo Electron Limited Method of trimming a gate electrode structure
US6980873B2 (en) 2004-04-23 2005-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for real-time fault detection, classification, and correction in a semiconductor manufacturing environment
US20080281438A1 (en) * 2004-04-23 2008-11-13 Model Predictive Systems, Inc. Critical dimension estimation
US7437404B2 (en) 2004-05-20 2008-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for improving equipment communication in semiconductor manufacturing equipment
US7069098B2 (en) * 2004-08-02 2006-06-27 Advanced Micro Devices, Inc. Method and system for prioritizing material to clear exception conditions
US7296103B1 (en) 2004-10-05 2007-11-13 Advanced Micro Devices, Inc. Method and system for dynamically selecting wafer lots for metrology processing
US7076321B2 (en) * 2004-10-05 2006-07-11 Advanced Micro Devices, Inc. Method and system for dynamically adjusting metrology sampling based upon available metrology capacity
KR20160045299A (ko) * 2014-10-17 2016-04-27 도쿄엘렉트론가부시키가이샤 기판 처리 장치, 연계 처리 시스템 및 기판 처리 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5503707A (en) * 1993-09-22 1996-04-02 Texas Instruments Incorporated Method and apparatus for process endpoint prediction based on actual thickness measurements
JP3633062B2 (ja) * 1994-12-22 2005-03-30 株式会社デンソー 研磨方法および研磨装置
US5646870A (en) 1995-02-13 1997-07-08 Advanced Micro Devices, Inc. Method for setting and adjusting process parameters to maintain acceptable critical dimensions across each die of mass-produced semiconductor wafers
US5637185A (en) * 1995-03-30 1997-06-10 Rensselaer Polytechnic Institute Systems for performing chemical mechanical planarization and process for conducting same
US5591299A (en) * 1995-04-28 1997-01-07 Advanced Micro Devices, Inc. System for providing integrated monitoring, control and diagnostics functions for semiconductor spray process tools
KR0161887B1 (ko) * 1995-12-26 1999-02-18 문정환 용기를 갖는 습식에치 장치의 에치 종말점 측정방법
US5639342A (en) 1996-03-15 1997-06-17 Taiwan Semiconductor Manufacturing Company Ltd. Method of monitoring and controlling a silicon nitride etch step
TW346649B (en) * 1996-09-24 1998-12-01 Tokyo Electron Co Ltd Method for wet etching a film
US5913102A (en) 1997-03-20 1999-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming patterned photoresist layers with enhanced critical dimension uniformity
US5926690A (en) 1997-05-28 1999-07-20 Advanced Micro Devices, Inc. Run-to-run control process for controlling critical dimensions
US6191038B1 (en) * 1997-09-02 2001-02-20 Matsushita Electronics Corporation Apparatus and method for chemical/mechanical polishing
US6194230B1 (en) * 1998-05-06 2001-02-27 International Business Machines Corporation Endpoint detection by chemical reaction and light scattering
US6228769B1 (en) * 1998-05-06 2001-05-08 International Business Machines Corporation Endpoint detection by chemical reaction and photoionization
US6190494B1 (en) * 1998-07-29 2001-02-20 Micron Technology, Inc. Method and apparatus for electrically endpointing a chemical-mechanical planarization process
US6197604B1 (en) * 1998-10-01 2001-03-06 Advanced Micro Devices, Inc. Method for providing cooperative run-to-run control for multi-product and multi-process semiconductor fabrication
KR100649387B1 (ko) 1999-06-22 2006-11-27 브룩스 오토메이션 인코퍼레이티드 초소형전자 제조에 사용하기 위한 공정수행 간 제어기
US6368879B1 (en) 1999-09-22 2002-04-09 Advanced Micro Devices, Inc. Process control with control signal derived from metrology of a repetitive critical dimension feature of a test structure on the work piece

Also Published As

Publication number Publication date
EP1303874A2 (en) 2003-04-23
TWI282134B (en) 2007-06-01
JP2004503104A (ja) 2004-01-29
WO2002005300A3 (en) 2002-04-11
US6461878B1 (en) 2002-10-08
KR100836945B1 (ko) 2008-06-11
CN1441962A (zh) 2003-09-10
KR20030016397A (ko) 2003-02-26
WO2002005300A2 (en) 2002-01-17
AU2001273203A1 (en) 2002-01-21

Similar Documents

Publication Publication Date Title
CN1258811C (zh) 控制蚀刻选择性的方法和装置
US6859746B1 (en) Methods of using adaptive sampling techniques based upon categorization of process variations, and system for performing same
JP4971050B2 (ja) 半導体装置の寸法測定装置
US6818561B1 (en) Control methodology using optical emission spectroscopy derived data, system for performing same
US7939450B2 (en) Method and apparatus for spacer-optimization (S-O)
US6133132A (en) Method for controlling transistor spacer width
CN1196186C (zh) 剥除时间反馈控制以减少剥除后晶体管栅极临界尺寸变化
TW557474B (en) Method and apparatus for determining process layer conformality
CN106444365B (zh) 晶圆刻蚀的控制方法及晶圆制造方法
US7272460B2 (en) Method for designing a manufacturing process, method for providing manufacturing process design and technology computer-aided design system
US6479200B1 (en) Method of controlling stepper process parameters based upon scatterometric measurements of DICD features
US20050233601A1 (en) System and method for controlling manufacturing processes, and method for manufacturing a semiconductor device
US7402257B1 (en) Plasma state monitoring to control etching processes and across-wafer uniformity, and system for performing same
US6895295B1 (en) Method and apparatus for controlling a multi-chamber processing tool
CN102854848A (zh) 有关未被抽样的工件的数据表示
US7533313B1 (en) Method and apparatus for identifying outlier data
US7035696B1 (en) Method and apparatus for poly gate CD control
CN100424501C (zh) 使用高产率频谱散射量测法以控制半导体工艺的方法
CN101572216B (zh) 控制刻蚀方法及刻蚀装置的控制装置
US6734088B1 (en) Control of two-step gate etch process
CN108063098B (zh) 有源区顶部圆滑度的模拟检测方法
US7200459B1 (en) Method for determining optimal photolithography overlay targets based on process performance and yield in microelectronic fabrication
US6617258B1 (en) Method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and system for accomplishing same
US6632692B1 (en) Automated method of controlling critical dimensions of features by controlling stepper exposure dose, and system for accomplishing same
JP2005038996A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: GLOBALFOUNDRIES

Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC.

Effective date: 20100705

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA, THE UNITED STATES TO: CAYMAN ISLANDS, BRITISH

TR01 Transfer of patent right

Effective date of registration: 20100705

Address after: Grand Cayman, Cayman Islands

Patentee after: Globalfoundries Semiconductor Inc.

Address before: American California

Patentee before: Advanced Micro Devices Inc.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20050406

Termination date: 20190703

CF01 Termination of patent right due to non-payment of annual fee